Back Propagation Algorithm in Verilog
Back Propagation Algorithm in Verilog
ABSTRACT
In this paper, a design method of neural
networks based on Verilog HDL hardware
description language, implementation is
proposed. A design of a general neuron for
topologies using back propagation algorithm
is described. The sigmoid nonlinear activation
function is also used. The neuron is then used
in the design and implementation of a neural
network using Xilinx Spartan-3e FPGA. The
simulation results obtained with Xilinx ISE
9.2i software.
The backpropagation algorithm is one
of the most useful algorithms of ANN training.
In this paper, we present the neuron implementation for the in topologies that are suitable
for this algorithm. The neuron is then used in a
multilayer
neural
network.
For
the
implementation, Verilog HDL language is
used. Verilog HDL is a hardware description
language which simplifies the development of
complex systems because it is possible to
model and simulate a digital system form a
high level of abstraction and with important
facilities for modular design.
The purpose of this work is to suggest and
analyze several neuron implementations, show
a way for the integration and control of the
neurons within a neural network, and describe
a way to implement a simple feedforward
neural network trained by BP algorithm using
Xilinx 9.2i.
Key words: Artificial Neural Network,
Backpropagation, Verilog HDL.
INTRODUCTION
A Neural Network is a powerful datamodeling tool that is able to capture and
represent complex input/output relationships.
The motivation for the development of neural
network technology stemmed from the desire
340
ISSN:2229-6093
Neelmani Chhedaiya ,Int.J.Computer Technology & Applications,Vol 3 (1),340-343
BACKPROPAGATION NETWORK
VERILOG HDL
In the semiconductor and electronic design
industry, Verilog is a hardware description
language (HDL) used to model electronic
systems. Verilog HDL, not to be confused with
Verilog HDL (a competing language), is most
commonly used in the design, verification, and
implementation of digital logic chips at the
register-transfer level of abstraction. It is also
used in the verification of analog and mixedsignal circuits.
Verilog HDL is a programming language that
has been designed and optimized for describing
the behavior of digital systems. Verilog HDL has
many features appropriate for describing the
behavior of electronic components ranging from
simple logic gates to complete microprocessors
and custom chips. Features of Verilog HDL
allow electrical aspects of circuit behavior (such
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ISSN:2229-6093
Neelmani Chhedaiya ,Int.J.Computer Technology & Applications,Vol 3 (1),340-343
METHODOLOGY
The proposed neural network has two layers with
four neurons each and sixteen synapses per layer.
Different situations may need neural networks of
different scales. Such a situation can be
overcome by combining a certain number of
such unit neural networks. Back propagation
algorithm logic has been divided into individual
modules and these modules have been
implemented in Verilog HDL using behavioral
modeling.
CONCLUSION
The proposed neural network has two layers with
four neurons each and sixteen synapses per layer.
Different situations may need neural networks of
different scales. Such a situation can be
overcome by combining a certain number of
such unit neural networks.
Back propagation algorithm logic has been
divided into individual modules and these
modules have been implemented in Verilog HDL
by using any one modeling.
This paper describes the Verilog HDL
implementation of a supervised learning
algorithm for artificial neural networks. The
algorithm is the Error Back propagation learning
algorithm for a layered feed forward network and
this algorithm has many successful applications
for training multilayer neural networks.
The simulation of the any one model by using
Verilog HDL shows that the implementation
creates a flexible, fast method and high degree of
parallelism for implementing the algorithm.
FUTURE SCOPE
An algorithm similar to back propagation
algorithm, which may be used to train networks
whose neurons may have discontinuous or nondifferentiable activation functions. These new
algorithms should also have the capability to
speed up the convergence of back propagation
algorithm. Modified forms of back propagation
algorithm such as Quick BP, RPROP, SARPROP, and MGF-PROP can provide a great
help.
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ISSN:2229-6093
Neelmani Chhedaiya ,Int.J.Computer Technology & Applications,Vol 3 (1),340-343
REFRENCES
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by Suzuki, K.; Nishio, A.; Kamo, A.;
Watanabe, T.; Asai, H.; Fac. of Eng., Shizuoka
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prediction
by
Wan-De
Weng; Rui-Chang Lin; Nat. Yunlin Univ. of
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Feedforward
Neural
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Implementation in FPGA Using Layer
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by S. Himavathi, D. Anitha, and A.
Muthuramalingam in May 2007
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FPGA: Issues and Application by A.
Muthuramalingam, S. Himavathi, E. Srinivasan
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