Advance in Electronic and Electric Engineering.

ISSN 2231-1297, Volume 3, Number 8 (2013), pp. 1013-1018

Research India Publications
http://www.ripublication.com/aeee.htm

Floating Point Arithmetic Unit Using Verilog

Lalita Gangwar1 and Rajan Chaudhary2
1,2

Department of Electronics and Communication,

Future Institute of Engineering and Technology
Bareilly, India.

Abstract
This research paper presents techniques for solving the Arithmetic
problems related to number systems. In this work a Floating-point
arithmetic unit, including following functions: addition, subtraction,
multiplication, division, square root and conversion of integer to
floating-point and conversion of floating-point to integer, is designed.
Further it is shown how these functions can be implemented, and how
these functions can be verified.
Here in this research paper it is tried to redesign the floating-point unit.
It includes all the software needed to generate custom Verilog coded
floating-point arithmetic unit. In general, it can be assumed that fixedpoint implementations have higher speed and lower cost, while
floating-point has higher dynamic range and no need for scaling, which
may be attractive for more complicated algorithms.

1. Introduction
In this paper, suggested a technique for solving the Arithmetic problems related to
number systems. In this designed a Floating-point arithmetic unit, including following
functioning: addition, subtraction, multiplication, division, square root and conversion
of integer to floating-point and conversion of floating-point to integer. And further
shown how these functions can be implemented, and how these functions can be
verified. Here it is tried to redesign the floating-point unit. It includes all the software
needed to generate custom verilog coded floating-point arithmetic unit. In general, it
can be assumed that fixed-point implementations have higher speed and lower cost,
while floating-point has higher dynamic range and no need for scaling, which may be
attractive for more complicated algorithms.

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2. Tools and Requirements

2.1 Modelsim Altera 6.4a
In this paper used the Modelsim Altera 6.4a to implement and simulate the logic of
floating-point arithmetic unit. The tool can be used to prepare a source file, edit and
compile it, and simulate the compiled version.
Editing and Compilation.
Simulation.

3. Methodology
It is started off by studying Computer Arithmetic. Next, analyzedthe IEEE standard
754 on binary floating point arithmetic. Listed a number of algorithms for high
performance floating point arithmetic. To handle the complexity, leveraged an existing
design in Verilog, learning a lot about both the languages in the process. Designed out
own testbench and in addition used the testing methodology adopted by the open cores
design and reran their tests. Finally synthesized the design using a real ASIC library
and wire load model. Arithmetic functions on floating point numbers consist of
addition, subtraction, multiplication and division. The functions are done with
algorithms similar to those used on sign magnitude integers (because of the similarity
of representation) -- example, only add numbers of the same sign. If the numbers are of
opposite sign, must do subtraction. Floating Point numbers are frequently used for
numerical calculations in computing systems. Arithmetic units for floating-point
numbers are more complex than fixed-point numbers. In this paper described the
simple algorithms for floating-point arithmetic such as addition, subtraction,
multiplication, and division in binary. Floating-point addition, multiplication and
division are briefly described.
3.1Floating-point addition/subtraction
Given two floating-point numbers, the sum is
(F1 x 2E1) + (F2 x 2E2) = F x 2E
The fraction part of the sum is the sum of fractions, and the exponent part of the
sum is remain same. We assumed that F1 and F2 are properly normalized; if they are
not normalized than first normalize the fraction part of sum.
3.1.1 Implementation of FPU adder
In this Float32Add is a block name that is provided for free in the form of Verilog
code. The code is difficult to read because of removed text formatting and identifiers
replaced with automatically generated strings. The fully functional code that should
work correctly in any simulation and synthesis tool can be designed. It can be simulate
it or synthesize it to FPGA or ASIC technology. Modifications of the code are
extremely difficult.

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3.1.2 Inputs and Outputs

The floating-point adder takes three inputs: the two floating point operands and a
control field. The control field is 5 bits long. The two least significant bits (LSBs)
define the rounding mode. Bit 2 is used to enable the hardware underflow trap handler.
Bit 3 is used to enable the hardware underflow trap handler. Bit 4 is used to select the
operation.
The adder has two outputs: the floating point result, and a flag field. The flag field
is also 5 bits long and has flags for the divide by zero (for compatibility with other
floating point components), invalid, inexact, overflow, and underflow exception flags.
3.2 Floating-point Multiplication
In this designed the single-precision multiplier for floating-point numbers. Use 23 bit
fractions and 9 bit exponents, with negative numbers represented in 2s complement.
Given two floating-point numbers, the product is
(F12E1) (F2 2E2) = (F1 F2) 2(E1+E2) = F 2E
The fraction part of the product is the product of fractions, and the exponent part of
the product is the sum of exponents. Assumed that F1 and F2 are properly normalized;
if they are not normalized than first normalize the fraction part of product.
3.3 Floating-point Division
In this designed the single-precision divider for floating-point numbers. Used 23 bit
fractions and 9 bit exponents, with negative numbers represented in 2s complement.
Given two floating-point numbers, the product is
(F12E1) (F2 2E2) = (F1 F2) 2(E1-E2) = F 2E
The fraction part of the division is the division of fractions, and the exponent part
of the division is the subtraction of exponents. Assumed that F1 and F2 are properly
normalized; if they are not normalized than first normalize the fraction part of division.
3.4 Floating-point Square root
Square root operation is hard to implement on FPGAs because of the complexity of the
algorithms. In this paper, presented a non-restoring square root algorithm and two very
simple single precision floating point square root implementations based on the
algorithms. The non-restoring square root algorithm also uses the twos complement
representation for the square root result. It is a non-restoring algorithm that does not
restore the remainder.

The ports description of floating-point square root and its features are as
follows:
Technology independent Verilog RTL design

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Lalita Gangwar & Rajan Chaudhary

Synchronous design optimized for area and performance
IEEE 754 single precision compliant
Exceptions supported
Denormal numbers supported including denormal arguments

4. Tool Used
4.1Modelsim Altera 6.4a
In this paper we use the Modelsim Altera 6.4a to implement and simulate the logic of
floating-point arithmetic unit. The tool can be used to prepare a source file, edit and
compile it, and simulate the compiled version.
Editing and Compilation.
Simulation.

5. Simulation and Synthesis

5.1 Simulation
After the implementation of RTL code of floating point arithmetic adder/ subtractor
simulated the RTL code in Modelsim 64a. The simulator generated a waveform of
floating-point adder/ subtractoris shown as.

Figure 3: Waveform generated through Simulator.

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5.2 Synthesis
Conversion of the code into hardware logic and fitting it into a FPGA or ASIC to
realize the circuit is termed Synthesis. Used the Mentor Graphics Synthesis tool
called Leonardo Spectrum for the purpose. There is another tool used for synthesis
purpose is Xilinx. The device selected to synthesize the design, is called the Target
Device. One can select any other suitable target device of Xilinx or other FPGA
vendors like Actel, Altera, Cypress, Lattice, Lucent, Quick logic, etc. The program
generates a summary of the synthesis activity and displays it as a Sum File. It gives a
report on the utilization of the Target Device by the design that was synthesized. It
also generates and display some timing information like Critical Path Timing.

6. Conclusions
The result of this paper is that successfully implemented the verilog code of floatingpoint adder/subtractor. The simulation result of this is also shown, after simulation is
done synthesized the floating-point adder code in Xilinx. A variety of Software tools
related to VLSI design is available. Discuss here two of them directly relevant to us
Modelsim and Leonardo Spectrum of Mentor Graphics. Modelsim has been used to
simulate the designs. Leonardo Spectrum has been used to obtain the synthesized
circuits presented. It would like to draw the attention of the researchers to the
following in this context
Only the essential aspects of the tools are presented.
For more details of the tools and the variety of facilities they offer, one can
refer to the respective user manuals and the Help menus.
Tools from other sources are similar in essentials. Any of them can be used.

References
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Digital Signal Processing with Field Programmable Gate Array by Dr. Uwe
Meyer-Baese.
Digital Systems Design using VHDL by Charles H. Roth.
Design Through Verilog HDL by T.R.Padmanabhan and B.Bala Tripura
Sundari.
Floating-Point Division and Square Root using a Taylor-series expansion
algorithm by Taek-Jun Kwon, Jeff Sondeen, Jeff Draper University of
Southern California / Information Sciences Institute.
http://www.hmc.edu/chips/fpadddocs.PDF
T.C. Chen, A Binary Multiplication J. Bannur and A. Varma, The VLSI
Implementation of A Square Root Algorithm, Proc. of IEEE Symposium on
Computer Arithmetic, IEEE Computer Society, Press, 1985. Pp159-165.
Peter-Michael seidel and Guy Even.On the Design of Floating-Point
Adders.In proceedings of the 15th IEEE symposium of Computer Arithmetic.

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Lalita Gangwar & Rajan Chaudhary