UNIT 1

1. Discuss the needs of HDL.

HDL is a language that describes the hardware of digital systems in a textual

form.
It resembles a programming language, but is specifically oriented to
describing hardware structures and behaviors.
The main difference with the traditional programming languages is HDLs
representation of extensive parallel operations whereas traditional ones
represents mostly serial operations.
The most common use of a HDL is to provide an alternative to schematics.
When a language is used for the above purpose (i.e. to provide an alternative
to schematics), it is referred to as a structural description in which the
language describes an interconnection of components.
Such a structural description can be used as input to logic simulation just as a
schematic is used.
Models for each of the primitive components are required.
If an HDL is used, then these models can also be written in the HDL providing
a more uniform, portable representation for simulation input.
HDL can be used to represent logic diagrams, Boolean expressions, and other
more complex digital circuits.

2. Explain the structure of VHDL and VERILOG modules.

VHDL:
It contains three parts library, entity, architecture.
Library : using built in packages
Entity: Declaration of design name and input, output ports.
Architecture: Defines the behaviour of entity.
Note: Syntax and example for each part.
Verilog:
Declaration of module(name, inputs and outputs)
Body of module(relationship between inputs and outputs)
3. Differentiate between an entity and a symbol.
Entity is specific the module and input and output, symbol specifies
operation of entity input and outputs.
4. Explain VERILOG data types.
NET, Vector, Register, Parameter, integer, array
5. Explain HDL data type.
(Scalar, Composite, Access , File and Other types)
6. Explain the composite and access types with example for example.
7. Describe VHDL scalar data types with example.
8. What is vector? Give an example for VHDL and VERILOG vector data types.
9. Compare VERILOG and VHDL data types.
10.Discuss different logical operations used in HDL.
11.With syntax and suitable example, explain the shift operator available in
VHDL and VERILOG.
12.Explain shift and rotate operations in HDL with an example.
Or
Write the result of all shift and rotate operations in VHDL after applying
them to a 7-bit vector A=1001010 for one position.

13.Write switch level description in VHDL for the inverter circuit with NMOS
and PMOS. Explain the advantages of this type description over other
type.
14.Write the result of all shift and rotate operations in VHDL after applying
them to a 7-bit vector A=1001010 for one position.
15.Mention different styles of description in HDL.
(Data flow, Behavioural, Structural, Switch level, Mixed type, Mixed
language.)
16.Write code for switch level description.
17.Discuss major difference between VERILOG and VHDL.
18.Write a short note on simulator and synthesis.
Unit 2
1. What do you mean by the data flow style of description? Explain its
features with a suitable example.
2. Explain the execution of signal assignment statements in HDL and
example.
3. Briefly discuss:
1. Constant declaration and assignment statement.
2. Signal declaration and assignment statement.
4. Design and Write VHDL/Verilog code for 2X2 bit combinational array
multiplication.
5. Draw the block diagram of a 3- bit carry look ahead adder and write data
flow description for its Boolean function verilog.
6. Write VHDL code for 2X1 multiplier with an active low enable in data flow
description.
7. Write the truth table of full adder and derive the Boolean function after
minimization for a full adder with active low enable. Write data flow
description using 2ns delay for any gate include XOR.
8. Obtain the expression for 2 bit comparator and write data flow description
for verilog and VHDL.
9. Write the data flow description VHDL for a system that has three 1 bit
inputs a(1), a(2), a(3) and a(1) least significant bit and 1 bit output b, b=1,
when only a(1)a(2)a(3) = 1, 3, 6, or 7. Drive the minimized Boolean
expression.
10.How do you assign delay time to the signal assignment statements.
11.Explain the use of data type vector with dataflow description.
Unit 3
1. Explain the execution of process statements.
2. Write VHDL code for 3 bit binary counter using CASE statement.
3. Distinguish between signal assignment statement and variable
assignment statement, with help of D latch VHDL code and simulation
waveform.
4. Explain verilog CASEX . Write verilog description of priority encoder using
CASEX statement.
5. With syntax, explain the sequential in HDL with example.
1. IF statement.
2. IF as ELSE-IF.

3. CASE statement
6. Explain the general format of Loop statements in HDL, with example,
(FOR LOOP, WHILE LOOP, REPEAT, FOREVER, NEXT AND EXIT).
7. Write the behavioural description for a half adder using verilog.
8. Write the VHDL description for SR filp-flop using CASE statement and
verilog declaration.
9. Explain BOOTH algorithm with flow chart. Write the VHDL description to
multi[ply two 4- bit number -5 and 7.
12.Write a verilog code to implement a 3 bit counter, with active high
synchronous using case statement.
13. Write a HDL code for JK Filp-Flop using case statement with positive edge
clock.
10.Write a VERILOG code for calculating the factorial of positive integer using
while loop.
11.Write the verilog description for a 4 bit priority encoder.
12.Write VHDL behavioural description of a tristate buffer. Use this as
component structure description of a 2 to 4 decoder with tristate output.
Unit 4
1.
2.
3.
4.
5.

Write structural description of an VHDL SR LATCH using NOR gates.

Write the structural description of D Latch using VERILOG and VHDL code.
Write a VHDL structural description for full adder, using two half adders.
Write the facts of structural description.
Compare structural coding in VERILOG and VHDL. Advantages of verilog
over VHDL.
6. Write verilog code for N bit magnitude comparator using generate
statement.
7. Write gate level description and verilog structural description for d Filpflop.
8. What is binding? With an example discuss binging between:
1. Entity and architecture
2. Library and component.
3. Entity and component.
4. Library and module.
9. Write the advantages of HDL structural description?
10.Write verilog structural description of full adder. Use this full adder to
design 3 bit comparator and write verilog structure for the same.
11.Write VHDL code using structural description for 2X1 multiplier with an
active low enable.
12.Explain
1. Generic statements
2. Parameter statements
3. Generate statements.
13.Write HDL code for N+1 bit magnitude comparator using
1. Generate and generic
2. Generate and paprameter.
Unit 5
1. What is the significance of procedures, function, tasks? Differentiate
between them.

2. Explain the use of Procedure in VHDL and TASK in VERILOG with

description :
1. N bit ripple carry adder.
2. Full adder using half adder.
3. Write HDL code to convert a unsigned binary vector to integer conversion
using procedure, task.
4. Write a code to convert the unsigned integer to (N=4) binary using
procedure.
5. Write HDL description to convert signed binary to the integer using task.
6. Explain the syntax of function in verilog and with an explain.
7. Write VHDL code for reading a string of characters from file and store in
an array.
Ex: collage
8. Write a VHDL function to find the greater of two signed number.
9. Explain the file declaration built in procedures for file processing(handling)
in VHDL.
10.Write a HDL code for signed vector multiplication using task declaration for
booth algorithm. D=A X B, where A and B are row vector with 3
elements.
11.Write a VHDL code to read a file consisting of four ASCII characters.
12.Write a code for finding the word with the lowest ASCII value using file
operation.
13.Write a note on verilog file processing.
14.Bring out the differences between function and procedures.
15.What do you understand by a file in HDL?
Note: Examples of files processing in page no.-328 NAZEIH M. BOTROS
Unit 6
1. Why mixed type description needed? Explain .
2. Explain the implementation of arrays in VHDL and VERILOG.
3. Explain the implementation of single dimensional and two dimensional
arrays in VHDL.
4. Write HDL code (verilog and VHDL) for finding greatest element of an
array.
5. Discuss VHDL package with example.
6. With a block diagram and function table of SRAM, Write VHDL code for
16X8 SRAM using mixed type description.
7. Write code for ALU using mixed type descrition.
8. Describe the development of HDL code for ALU and write the verilog code
for 16 bit ALU to perform 8 operation.
9. Write the block diagram and function table of 3SRAM. Using this write a
verilog code description for 16X8 SRAM.
10. How to attached a package to the VHDL module? Explain with example.
11.Explain with syntax VHDL package and package body.
12.Write a VHDL code for addition of two 5X5 matrices using a package.
13.Explain the fetch and execution cycles of of basic computer for following
oprations
HALT, ADD, MULT, NAND
Unit 7

1. Explain the necessity of mixed language description.

2. What are the limitations of Mixed language description.
3. Write mixed language description of master slave D filpflop by invoking
VHDL entity and from verilog module.
4. How do you invoke a verilog module from VHDL module.
5. Explain by consider Mixed level description of a full adder using two half
adders.
6. Write a VHDL code for 1 bit Full adder using structural description, and
invoking this code in a verilog to implement 3 bit adder with zero flag. If
zero flag set when output in zero.
7. Explain the process of invoking a verilog from VHDL module.
8. How to invoke a VHDL entity from verilog module? Explain with an
example.
9. Write mixed language description of JK flip-flop wit clear, invoke VHDL
entity from verilog module.
10.Describe full adder using two half adder invoking verilog module from
VHDL module.
11.Write mixed language description of a 3 bit adder with zero flag. If the
output of the adder is zero, the zero flag is set to 1; otherwise it is set to
0.
12.Write a mixed language description of an AND gate invoking verilog
modules from VHDL module.