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Passives

This lecture discusses passive devices that can be implemented in CMOS processes such as resistors, capacitors, and inductors. Resistors are difficult to implement precisely in CMOS due to non-idealities like temperature and voltage coefficients. N-well and polysilicon resistors are commonly used. Capacitors have options like metal-metal, metal-oxide-semiconductor (MOS), and metal-insulator-metal (MIM). MOS capacitors have high non-linearity and temperature dependence. Layout techniques like common centroid and dummy elements can improve matching. While inductors are not usually used for analog design due to their size, spiral inductors have been implemented on-chip for radio frequency applications.

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74 views18 pages

Passives

This lecture discusses passive devices that can be implemented in CMOS processes such as resistors, capacitors, and inductors. Resistors are difficult to implement precisely in CMOS due to non-idealities like temperature and voltage coefficients. N-well and polysilicon resistors are commonly used. Capacitors have options like metal-metal, metal-oxide-semiconductor (MOS), and metal-insulator-metal (MIM). MOS capacitors have high non-linearity and temperature dependence. Layout techniques like common centroid and dummy elements can improve matching. While inductors are not usually used for analog design due to their size, spiral inductors have been implemented on-chip for radio frequency applications.

Uploaded by

babadfe
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EECS240 Spring 2010

Lecture 2: CMOS Technology and


Passive Devices

Elad Alon
Dept. of EECS

Todays Lecture
EE240 CMOS Technology
Passive devices

Motivation
Resistors
Capacitors
(Inductors)

Next time: MOS transistor modeling

EECS240

Lecture 2

EE240 Process
90nm 1P7M CMOS

Minimum channel length: 90nm


1 level of polysilicon
7 levels of metal (Cu)
1.2V supply
Models for this process not real

Other processes you might see


Shorter channel length (45nm / 1V)
Bipolar, SiGe HBT
SOI
EECS240

Lecture 2

Process Options
Available for many processes
Add features to baseline process
E.g.

Silicide block option


High voltage devices (2.5V & 3.3V, >10V)
Low VTH devices
Capacitor option (2 level poly, MIM)

EECS240

Lecture 2

CMOS Cross Section


Metal

p- substrate

p+ diffusion

Poly

n- well

n+ diffusion

EECS240

Lecture 2

Dimensions

Drawing is not to scale!

EECS240

Lecture 2

Why Talk About Passives?

EECS240

Lecture 2

Resistors
No provisions in standard CMOS
Resistors are bad for digital circuits
Minimized in standard CMOS
But, often want big, well-controlled R for
analog
Sheet resistance of available layers:
Layer

Sheet resistance

Aluminum
Polysilicon
N+/P+ diffusion
N-well
EECS240

60 m/
5 /
5 /
1 k/
Lecture 2

How about an N-Well Resistor?

EECS240

Lecture 2

Silicide Block Option


Layer
N+ poly
P+ poly
N+ diffusion
P+ diffusion
N-well

R/

[/ ]
100
180
50
100
1000

TC [ppm/oC]
@ T = 25 oC

VC [ppm/V]

-800
200
1500
1600
-1500

50
50
500
500
20,000

BC [ppm/V]
50
50
-500
-500
30,000

Non-silicided layers have significantly larger sheet


resistance
Even with silicide block, many non-idealities:
Temperature coefficient: R = f(T)
Voltage coefficient: R = f(V)
Manufacturing Variations
EECS240

Lecture 2

10

Resistor Temp-Co. Example

EECS240

Lecture 2

11

Voltage Dependence

EECS240

Lecture 2

12

Voltage Coefficient
-

p substrate

p diffusion

n- well

n+ diffusion

V1

Example:
Diffusion resistor

V2

Applied voltage
modulates depletion
width
(cross-section of
conductive channel)

VB

Well acts as a shield


V1 V2
I

V + V2

Ro 1 + TC (T 25o ) + VC (V1 V2 ) + BC 1
VB
2

R=

EECS240

Lecture 2

13

Lecture 2

14

Compensation

EECS240

Resistor Matching
Types of mismatch:
Run-to-run variations
Global differences in thickness, doping, etc.
Systematic (e.g. contacts)
Random variations between devices

Run-to-run variations in absolute R value: 20+%


Can be problematic for termination, bias current, etc.

Best case: make circuit depend only on ratios


E.g., use feedback to control opamp gain
With careful layout, can get 0.1 1% matching

EECS240

Lecture 2

15

Systematic Variations from Layout


Example:
R

2R?

Use unit element instead:


2R

R
EECS240

Lecture 2

16

Common Centroid and Dummies


Example:

R1 : R2 = 1 : 2

gradient

Dummy
0.5 * R2 + R
R1
0.5 * R2 - R
Dummy

EECS240

Lecture 2

17

Resistor Layout (cont.)


Serpentine layout for large values:

Better layout (mitigates offset due to thermoelectric effects):

See Hastings, The art of analog layout, Prentice Hall, 2001.

EECS240

Lecture 2

18

MOSFETs as Resistors
Triode region (square law):
I D = Cox

W
V
VGS VTH DS VDS
L
2

for VGS VTH > VDS

Small signal resistance:


1
I D
W
=
= C ox (VGS VTH VDS )
R VDS
L
R

1
W
Cox (VGS VTH )
L

for VGS VTH >> VDS

Voltage coefficient:
VC =

1 R
1
=
R VDS VGS VTH VDS

EECS240

Lecture 2

19

MOS Resistors
Example: R = 1 M

1
W
Cox (VGS VTH )
L
1
W
=
L Cox R (VGS VTH )

Large R-values realizable in


small area
Very large voltage coefficient

=
100

VC V

DS

= 0V

=
=

EECS240

VGS

1
1
=
A
200

1
M

2
V
V2
1
VTH

1
= 0.5V 1
2V

Applications:
MOSFET-C filters: (linearization)
Ref: Tsividis et al, ContinuousTime MOSFET-C Filters in VLSI,
JSSC, pp. 15-30, Feb. 1986.

Biasing: (>1G)
Ref: Geen et al, Single-Chip
Surface-Micromachined Integrated
Gyroscope with 50o/hour Root Allen
Variance, ISSCC, pp. 426-7, Feb.
2002.
Lecture 2

20

Resistor Summary
No or limited support in standard CMOS
Large area (compared to FETs)
Nonidealities:
Large run-to-run variations
Temperature coefficient
Voltage coefficients (nonlinear)

Avoid them when you can


Especially in critical areas, e.g.
Amplifier feedback networks
Electronic filters
A/D converters
We will get back to this point
EECS240

Lecture 2

21

Capacitors
Simplest capacitor:

substrate

Whats the problem with this?

EECS240

Lecture 2

22

Capacitors
Improved capacitor:

substrate

Is this only 1 capacitor?

EECS240

Lecture 2

23

Capacitor Options
Type

C [aF/m2]

VC [ppm/V]

TC
[ppm/oC]

Gate

10,000

Huge

Big

1000

10

25

Metal-metal

50

20

30

Metal-substrate

30

Metal-poly

50

Big

Big

Poly-poly
(option)

Poly-substrate

120

Junction caps

~ 1000

EECS240

Lecture 2

24

MOS Capacitor
High non-linearity,
temperature coefficient
But, still useful in many
applications, e.g.:
(Miller) compensation
capacitor
Bypass capacitor
(supply, bias)

EECS240

Lecture 2

25

Capacitor Layout
Unit elements
Shields:
Etching
Fringing fields

Common-centroid
Wiring and interconnect
parasitics
Ref.: Y. Tsividis, Mixed Analog-Digital VLSI Design
and Technology, McGraw-Hill, 1996.

EECS240

Lecture 2

26

MIM Capacitors
Some processes have MIM cap as add-on option
Separation between metals is much thinner
Higher density

Used to be fairly popular


But not as popular now that have many metal layers
anyways

EECS240

Lecture 2

27

Capacitor Geometries

Horizontal parallel plate


Vertical parallel plate
Combinations

Ref: R. Aparicio and A. Hajimiri, Capacity Limits and Matching Properties of


Integrated Capacitors, JSSC March 2002, pp. 384-393.

EECS240

Lecture 2

28

MOM Capacitors

Metal-Oxide-Metal capacitor. Free with modern CMOS.


Use lateral flux (~Lmin) and multiple metal layers to realize high
capacitance values

EECS240

Lecture 2

29

MOM Capacitor Cross Section


Use a wall of metal and
vias to realize high
density
More layers higher
density
May want to chop off lower
layers to reduce Cbot

Reasonably good
matching and accuracy

EECS240

Lecture 2

30

Distributed Effects
Can model IC resistors as
distributed RC circuits.
Could use transmission line
analysis to find equivalent
2-port parameters.
Inductance negligible for
small IC structures up to
~10GHz.

EECS240

Lecture 2

31

Effective Resistance

High frequency resistance depends on W, e.g.:


W=1 10k resistor works fine at 1GHz
W=5 10k resistor drops to 5k at 1 GHz

May need distributed model for accurate freq


response
EECS240

Lecture 2

32

Capacitor Q

Current density drops as you go farther from


contact edge

EECS240

Lecture 2

33

Double Contact Strucutre

If contact on both edges,


R drops 4X
Can be a good idea even if not hitting distributed effects

EECS240

Lecture 2

34

What About Inductors?

Mostly not used in analog/mixed-signal design


Usually too big
More of a pain to model than Rs and Cs
But they do occasionally get used

Example inductor app.: shunt peaking


Can boost bandwidth by up to 85%!
Q not that important (L in series with R)
But frequency response may not be flat
EECS240

Lecture 2

35

Spiral Inductors

Used widely in RF circuits for small L (~1-10nH).


Use top metal for Q and high self resonance
frequencies.
Very good matching and accuracy if you model them right
EECS240

Lecture 2

36

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