Computer basics

Four bits together is known as Nibble, and Eight bits together is known as Byte.
A. Central Processor Unit (CPU) :
Central processor unit consists of two basic blocks :
o

The program control unit has a set of registers and control circuit to
generate control signals.

The execution unit or data processing unit contains a set of registers for
storing data and an Arithmatic and Logic Unit (ALU) for execution of
arithmatic and logical operations.

In addition, CPU may have some additional registers for temporary storage of
data.
B. Input Unit :
With the help of input unit data from outside can be supplied to the computer. Program or data is
read into main storage from input device or secondary storage under the control of CPU input
instruction.
Example of input devices: Keyboard, Mouse, Hard disk, Floppy disk, CD-ROM drive etc.
C. Output Unit :
With the help of output unit computer results can be provided to the user or it can be stored in
stograge device permanently for future use. Output data from main storage go to output device
under the control of CPU output instructions.
Example of output devices: Printer, Monitor, Plotter, Hard Disk, Floppy Disk etc.
D. Memory Unit :
Memory unit is used to store the data and program. CPU can work with the information stored
in memory unit. This memory unit is termed as primary memory or main memory module. These
are basically semi conductor memories.
There ate two types of semiconductor memories

Volatile Memory

Non-Volatile Memory : ROM (Read only Memory), PROM (Programmable ROM)

: RAM (Random Access Memory).

EPROM (Erasable PROM), EEPROM (Electrically Erasable

PROM).

Secondary Memory :

There is another kind of storage device, apart from primary or main memory,
which is known as secondary memory. Secondary memories are non volatile
memory and it is used for permanent storage of data and program.
Example of secondary memories:

Hard Disk, Floppy Disk, Magenetic

Tape
CD-ROM
Thumb drive (or pen drive)

------

These are magnetic devices,

-----------

is optical device
is semiconductor memory.

the CPU can work with the information available in main memory only.

To access the data from memory, we need two special registers one is known as Memory Data
Register (MDR) and the second one is Memory Address Register (MAR).
A memory module of capacity 16 X 4 indicates that, there are 16 location in the memory module
and in each location, we can store 4 bit of information.
We need two operation to work with memory.
This operation is to retrive the data from memory and bring it to
Operation:
CPU register
WRITE Operation: This operation is to store the data to a memory location from
CPU register
READ

To transfer the data from CPU to memory module and vice-versa, we need some connection.
This is termed as DATA BUS.
The size of the data bus indicate how many bit we can transfer at a time. Size of data bus is
mainly specified by the data storage capacity of each location of memory module.
We have to resolve the issues how to specify a particular memory location where we want to
store our data or from where we want to retrive the data.
This can be done by the memory address. Each location can be specified with the help of a
binary address.
If we use 4 signal lines, we have 16 different combinations in these four lines, provided we use
two signal values only (say 0 and 1).
To distingush 16 location, we need four signal lines. These signal lines use to identify a memory
location is termed as ADDRESS BUS. Size of address bus depends on the memory size. For a
n
memory module of capacity of 2 location, we need n address lines, that is, an address bus of
size n.
Memory is used to store the information in digital form. The memory hierarchy is given by:

Register

Cache Memory

Main Memory

Magnetic Disk

Removable media (Magnetic tape)

Internal memories are semiconductor memory. Semiconductor memories are categoried as

volatile memory and non-volatile memory
RAM: Random Access Memories are volatile in nature. As soon as the computer is switched off,
the contents of memory are also lost.
ROM: Read only memories are non volatile in nature. The storage is permanent, but it is read
only memory. We can not store new information in ROM.
Several types of ROM are available:

PROM: Programmable Read Only Memory; it can be programmed once as per user
requirements.

EPROM: Erasable Programmable Read Only Memory; the contents of the memory can
be erased and store new data into the memory. In this case, we have to erase whole
information.

EEPROM: Electrically Erasable Programmable Read Only Memory; in this type of

memory the contents of a particular location can be changed without effecting the
contents of other location.

Main Memory
The main memory of a computer is semiconductor memory. The main memory
unit of computer is basically consists of two kinds of memory:
RAM : Random access memory; which is volatile in nature.
ROM : Read only memory; which is non-volatile.
The permanent information are kept in ROM and the user space is basically in
RAM.
The smallest unit of information is known as bit (binary digit), and in one memory
cell we can store one bit of information. 8 bit together is termed as a byte.
The maximum size of main memory that can be used in any computer is
determined by the addressing scheme.

A computer that generates 16-bit address is capable of addressing upto 2 16 which is equal to
64K memory location. Similarly, for 32 bit addresses, the total capacity will be 2 32 which is equal
to 4G memory location. The data transfer between main memory and the CPU takes place
through two CPU registers.

MAR : Memory Address Register

MDR : Memory Data Register.

If the MAR is k-bit long, then the total addressable memory location will be 2k.
If the MDR is n-bit long, then the n bit of data is transferred in one memory cycle.

Binary Storage Cell:

The binary storage cell is the basic building block of a memory unit.

The binary cell sotres one bit of information in its internal latch.

Depending on the technology used to construct a RAM, there are two types of RAM

SRAM: Static
Random
DRAM: Dynamic Random Access Memory.

Access

Memory.

Dynamic Ram (DRAM):

A DRAM is made with cells that store data as charge on capacitors. The
presence or absence of charge in a capacitor is interpreted as binary 1 or 0.
Because capacitors have a natural tendency to discharge due to leakage current,
dynamic RAM require periodic charge refreshing to maintain data storage. The
term dynamic refers to this tendency of the stored charge to leak away, even with
power continuously applied.

Due to the discharge of the capacitor during read operation, the read operation of DRAM is
termed as destructive read out.
Static RAM (SRAM):
In an SRAM, binary values are stored using traditional flip-flop constructed with the help of
transistors. A static RAM will hold its data as long as power is supplied to it.
SRAM Versus DRAM :

Both static and dynamic RAMs are volatile, that is, it will retain the information as long as
power supply is applied.

A dynamic memory cell is simpler and smaller than a static memory cell. Thus a DRAM is
more
dense,
i.e., packing density is high(more cell per unit area). DRAM is less expensive than
corresponding SRAM.

DRAM requires the supporting refresh circuitry. For larger memories, the fixed cost of the
refresh circuitry is more than compensated for by the less cost of DRAM cells

SRAM cells are generally faster than the DRAM cells. Therefore, to construct faster
memory modules(like cache memory) SRAM is used.

A memory chip consisting of 16 words of 8 bits each, usually referred to as 16 x 8 organization.

Cache Memory
Analysis of large number of programs has shown that a number of instructions are executed
repeatedly. This may be in the form of a simple loops, nested loops, or a few procedures that
repeatedly call each other. It is observed that many instructions in each of a few localized areas
of the program are repeatedly executed, while the remainder of the program is accessed
relatively less. This phenomenon is referred to as locality of reference.
Now, if it can be arranged to have the active segments of a program in a fast memory, then the
tolal execution time can be significantly reduced. It is the fact that CPU is a faster device and
memory is a relatively slower device. Memory access is the main bottleneck for the performance
efficiency. If a faster memory device can be inserted between main memory and CPU, the
efficiency can be increased. The faster memory that is inserted between CPU and Main Memory
is termed as Cache memory.
Mapping Functions
The mapping functions are used to map a particular block of main memory to a particular block of
cache. This mapping function is used to transfer the block from main memory to cache memory.
Three different mapping functions are available:
Direct mapping:
A particular block of main memory can be brought to a particular block of cache memory. So, it is
not flexible.
Associative mapping:
In this mapping function, any block of Main memory can potentially reside in any cache block
position. This is much more flexible mapping method.
Block-set-associative mapping:
In this method, blocks of cache are grouped into sets, and the mapping allows a block of main
memory to reside in any block of a specific set. From the flexibility point of view, it is in between
to the other two methods.
When a process starts to execute, it is placed in the process queue and it is in the new state. As
resources become available, then the process is placed in the ready queue.At any given time a
process may be in one of the following five states.
1.New

: A program is admitted to execute, but not yet ready to execute. The operating
system will initialize the process by moving it to the ready state.

2.Ready

: The process is ready to execute and is waiting access to the processor.

3.Runnin : The process is being executed by the processor. At any given time, only one
g
process is in running state.
4.Waiting : The process is suspended from execution, waiting for some system resource,

such as I/O.
5.Exit

: The process has terminated and will be destroyed by the operating system.

A process being executed may be suspended for a variety of reasons. If it is suspended because
the process requests I/O, then it is places in the appropriate I/O queue. If it is suspended
because of a timeout or because the operating system must attend to processing some of it's
task, then it is placed in ready state.
What is swapping :

1. The process waiting for some I/O to complete, must stored back in disk.
2. New ready process is swapped in to main memory as space becomes
available.
3. As process completes, it is moved out of main memory.
4. If none of the processes in memory are ready,

Swapped out a block process to intermediate queue of blocked

process.

Swapped in a ready process from the ready queue.

Partitioning
Splitting of memory into sections to allocate processes including operating system. There are two
scheme for partitioning :
o

Fixed size partitions

Variable size partitions

The unused portion of memory in each partition is termed as hole.

There are two simple ways to slightly remove the problem of memory wastage:
Coalesce

: Join the adjacent holes into one large hole , so that some process can be
accomodated into the hole.

Compaction : From time to time go through memory and move all hole into one free block of
memory.
There is another scheme for use of memory which is known as paging.
In this scheme,
The memory is partitioned into equal fixed size chunks that are relatively small. This chunk of
memory is known as frames or page frames.
Each process is also divided into small fixed chunks of same size. The chunks of a program is
known as pages.

page

of

program

could

be

assigned

to

available

page

frame.

In this scheme, the wastage space in memory for a process is a fraction of a page frame which
corresponds to the last page of the program.
Addressing Modes:
The most common addressing techniques are:
o

Immediate

Direct

Indirect

Register

Register

Displacement

Stack

Indirect

Introduction to CPU
The operation or task that must perform by CPU are:

Fetch Instruction: The CPU reads an instruction from memory.

Interpret Instruction: The instruction is decoded to determine what action is

required.

Fetch Data: The execution of an instruction may require reading data from
memory or I/O module.

Process data: The execution of an instruction may require performing some

arithmatic or logical operation on data.

Write data: The result of an execution may require writing data to

memory or an I/O module.

The major components of the CPU are an arithmatic and logic unit (ALU) and a control unit (CU).
The ALU does the actual computation or processing of data. The CU controls the movement of
data and instruction into and out of the CPU and controls the operation of the ALU.
The CPU is connected to the rest of the system through system bus. Through system bus, data
or information gets transferred between the CPU and the other component of the system. The
system bus may have three components:
Data
Data bus is used to transfer the data between main memory and CPU.

Bus:

Address
Bus:
Address bus is used to access a particular memory location by putting the address of the
memory location.
Control
Bus:
Control bus is used to provide the different control signal generated by CPU to different part of
the system. As for example, memory read is a signal generated by CPU to indicate that a
memory read operation has to be performed. Through control bus this signal is transferred to
memory module to indicate the required operation.
The major functions of an I/O module are categorized as follows

Control

and

timing

Processor

Communication

Device

Communication

Data

Error Detection

Buffering

Buses
The processor, main memory, and I/O devices can be interconnected through common data
communication
lines
which
are
termed
as common
bus.
The primary function of a common bus is to provide a communication path between the devices
for the transfer of data. The bus includes the control lines needed to support interrupts and
arbitration.
The bus lines used for transferring data may be grouped into three categories:

data,

address

control lines.

There are several schemes exist for handling the timing of data transfer over a bus. These can
be broadly classified as
o

Synchronous bus

Asynchronous bus

Synchronous Bus :

In a synchronous bus, all the devices are synchronised by a common clock, so all devices derive
timing information from a common clock line of the bus. A clock pulse on this common clock line
defines equal time intervals.
In the simplest form of a synchronous bus, each of these clock pulse constitutes a bus cycle
during which one data transfer can take place.
Asynchronous Bus
In asynchronous mode of transfer, a handshake signal is used between master and slave.
In asynchronous bus, there is no common clock, and the common clock
signal is replaced by two timing control signals: master-ready and slaveready.
Master-ready signal is assured by the master to indicate that it is ready
for a transaction, and slave-ready signal is a response from the slave.
The devices need to store information permanently are either magnetic or optical devices.
Magnetic Devices:
Magnetic disk ( Hard disk )
Floopy disk

Optical Devices:
CD- ROM
CD-Recordable( CD R)

Magnetic tape

CD-R/W

DVD

To reduce the gap between HLL and the instruction set of computer architecture, the system
becomes more and more complex and the resulted system is termed as Complex Instruction
Set Computer (CISC).
Characteristics of Reduced Instruction Set Architecture :

Although a variety of different approaches to reduce Instruction set architecture have been taken,
certain characteristics are common to all of them:
1. One instruction per cycle.
2. Registertoregister operations.
3. Simple addressing modes.
4. Simple instruction formats
Pipelining is a particularly effective way of organizing parallel activity in a computer system. The
basic idea is very simple. It is frequently encountered in manufacturing plants, where pipelining is
commonly known as an assembly line operation.
To apply the concept of instruction execution in pipeline, it is required to break the instruction in
different task. Each task will be executed in different processing elements of the CPU.

A database is an organized collection of data. The data are typically organized to model relevant
aspects of reality in a way that supports processes requiring this information. For example,
modeling the availability of rooms in hotels in a way that supports finding a hotel with vacancies.