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    Fpga Implementation of Binary Search 1

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    Araneesh Rajan
    This paper reports an FPGA implementation of binary search. Existing hardware implementation, CAM uses parallel search which results in high speed but there are disadvantages like high power consumption and area. The proposed hardware architecture achieves the balance between power consumption and hardware complexity and to increase the speed.

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    Fpga Implementation of Binary Search 1

    Uploaded by

    Araneesh Rajan
    469 views5 pages
    This paper reports an FPGA implementation of binary search. Existing hardware implementation, CAM uses parallel search which results in high speed but there are disadvantages like high power consumption and area. The proposed hardware architecture achieves the balance between power consumption and hardware complexity and to increase the speed.

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    FPGA IMPLEMENTATION OF BINARY SEARCH 1.docx

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    This paper reports an FPGA implementation of binary search. Existing hardware implementation, CAM uses parallel search which results in high speed but there are disadvantages like high power consumption and area. The proposed hardware architecture achieves the balance between power consumption and hardware complexity and to increase the speed.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    469 views5 pages

    Fpga Implementation of Binary Search 1

    Uploaded by

    Araneesh Rajan
    This paper reports an FPGA implementation of binary search. Existing hardware implementation, CAM uses parallel search which results in high speed but there are disadvantages like high power consumption and area. The proposed hardware architecture achieves the balance between power consumption and hardware complexity and to increase the speed.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
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    The paper proposes implementing binary search in FPGA hardware to reduce power consumption and complexity compared to existing CAM implementations by only activating the memory row containing the searched data.

    The proposed system aims to implement binary search in FPGA hardware to reduce power consumption and complexity compared to existing CAM implementations which have high power usage and complexity.

    Binary search works by repeatedly dividing the search interval in half, starting with the entire array/list. It compares the search key to the middle element and eliminates half of the array, focusing the search on the other half until the target is found or the interval is empty.

    FPGA Implementation Of Binary Search

    Y. Nesika1, T.Asha2, P. Jasmine 3 - 4th year Students,

    Department of ECE, Mar Ephraem College of Engineering

    Email id: [email protected] , [email protected] ,[email protected].


    Under the guidance of: Mrs. C. Jasmine, M. Tech, (Ph .D),
    Abstract- This paper reports an FPGA implementation of binary search. Searching is an important function
    in memory architectures. Normally, binary search using software implementation is a slow process. Existing
    hardware implementation, CAM uses parallel search which results in high speed but there are disadvantages
    like high power consumption and area. The proposed hardware architecture achieves the balance between
    power consumption and hardware complexity.
    INTRODUCTION:
    This is based on designing the binary
    search in hardware based on FPGA. This is aimed to
    reduce the power consumption and hardware
    complexity and to increase the speed. In the existing
    CAM (Content Addressable Memory) based binary
    search, the power consumption is very high. In order
    to reduce the power consumption we are going to
    design the binary search in hardware. Binary search
    is a key task in network application such as network
    security. Signature matching in IDS (Intrusion
    detection system) requires searching, in which binary
    search can be applied. In this paper, we present
    FPGA based architecture of binary search targeting
    decrease power consumption with less hardware
    components. The existing hardware implementation
    CAM requires high power with high hardware
    complexity.
    EXISTING SYSTEM:
    Unlike standard computer memory (random
    access memory or RAM) in which the user supplies a
    memory address and the RAM returns the data word
    stored at that address, a CAM is designed such that
    the user supplies a data word and the CAM searches
    its entire memory to see if that data word is stored
    anywhere in it. If the data word is found, the CAM
    returns a list of one or more storage addresses where
    the word was found (and in some architecture, it also
    returns the data word, or other associated pieces of
    data). Thus, a CAM is the hardware embodiment of
    what in software terms would be called an associative
    array. Because a CAM is designed to search its entire
    memory in a single operation, it is much faster than
    RAM in virtually all search applications. There are
    cost disadvantages to CAM however. Unlike a RAM
    chip, which has simple storage cells, each individual

    memory bit in a fully parallel CAM must have its


    own associate comparison circuit to detect a match
    between the stored bit and the input bit.
    Additionally, match outputs from each cell in the data
    word must be combined to yield a complete data
    word match signal. The additional circuitry increases
    the physical size of the CAM chip which increases
    manufacturing cost. The extra circuitry also increases
    power dissipation since every comparison circuit is
    active on every clock cycle. So power consumption is
    high in CAM.

    PROPOSED SYSTEM:
    A binary search locates an item in a sorted
    array by repeatedly dividing the search interval in
    half. The initial interval includes the entire array. If
    the value of the search key is less than the item in the
    middle of the interval, then the next interval will be
    the lower half of the current interval. If the value of
    the search key is greater than the middle item, then
    the next interval will be the upper half. The search
    process repeats until the item is found or the search
    interval is empty. Binary Search is an O (log
    n) algorithm, which is more efficient than a linear
    search for large arrays.
    It is an efficient algorithm for finding a sorted
    array. Suppose a search is begun by comparing the
    key with the value in the middle location of a sorted
    array. If the middle value is too large then all values
    in the last half are too large; hence, the search can be
    limited to the first half. Similarly if the middle value
    is too small, then the search can be limited to the

    second half. This approach can be continued, each


    time narrowing the search to an interval half the size
    of previous interval.

    BLOCK

    DIAGRAM:

    FLOWCHART FOR BINARY SEARCH:

    MAGNITUDE COMPARATOR:
    It is a combinational circuit. Here we are
    using a 4 bit magnitude comparator. The two inputs
    to the magnitude comparator are the starting and the
    ending address of the memory where we are going to
    search the targeted data. The starting address and the
    ending address of the memory are given to the
    comparator. It compares the two addresses and gives
    an output. If the output is less than or equal, it is
    given to the adder or else it decides that the target to
    be searched is not in the memory.
    ADDER:
    Here we are using a 4 bit adder. The adder now
    adds both the starting and ending addresses and
    produces an output. This output is given to the
    divider.
    DIVIDER:
    Here the output of the adder is divided by
    2.The output of the divider is the middle value
    that is the middle address of the memory where the
    searching is done. Using this middle value we can
    divide the memory into two halves.

    MEMORY:
    A 16 bit RAM memory is used. The two inputs
    to the memory are address and the clock input and
    the output is the data output. The middle value is
    considered as the address of our targeted data and it
    is given as the input to the memory. The second input
    to the memory is the CLOCK input which is used for
    synchronization. The output of the memory is the
    data which is stored in the middle address.
    MASK REGISTER:
    It is nothing but a register which is used to
    store the targeted data which we are searching in
    the memory.
    MAGNITUDE COMPARATOR:
    The two inputs to this magnitude
    comparator are the data output from the memory and
    targeted data from the mask register. If the two inputs
    are equal, it indicates that the target data was found
    in the memory and it is the required output. If the
    targeted data is greater than the data output from
    memory ,then it will be given to an adder and here
    again a starting address is calculated using [Starting
    address=middle value+1].Then this result is given to
    the first magnitude comparator and if the targeted
    data is lesser than the data output, then it is given
    to the subtraction and again an ending address is
    calculated using [Ending address=middle value-1],
    then this will given to the first magnitude comparator.
    And this procedure will be repeated until our targeted
    data is found in memory.
    SOFTWARE TECHNIQUES:
    The software used here is Xilinx XSE
    9.2i. After design entry and optional simulation, you
    run synthesis. The ISE software includes Xilinx
    Synthesis Technology (XST), which synthesizes
    VHDL, Verilog, or mixed language designs to create
    Xilinx-specific net list files known as NGC files.
    Unlike output from other vendors, which consists of
    an EDIF file with an associated NCF file, NGC files
    contain both logical design data and constraints. XST
    places the NGC file in your project directory and the
    file is accepted as input to the Translate (NGDBuild)
    step of the Implement Design process.
    HARDWARE TECHNIQUES:
    FPGAs are programmable semiconductor devices
    that are based around a matrix of Configurable Logic
    Blocks (CLBs) connected through programmable
    interconnects. As opposed to Application Specific

    Integrated Circuits (ASICs), where the device is


    custom built for the particular design, FPGAs can be
    programmed to the desired application or
    functionality requirements. Although One-Time
    Programmable (OTP) FPGAs are available, the
    dominant type are SRAM-based which can be
    reprogrammed as the design evolves.
    FPGAs allow designers to change their designs very
    late in the design cycle even after the end product
    has been manufactured and deployed in the field. In
    addition, Xilinx FPGAs allow for field upgrades to be
    completed remotely, eliminating the costs associated
    with re-designing or manually updating electronic
    systems.

    RESULTS AND DISCUSSION:


    Using the proposed method, the power
    consumption of the system can be reduced, since only
    the row in the memory where the targeted data
    present will be active( switch is ON).So the power is
    supplied only to that particular row in memory
    thereby reducing the power consumption of the
    system. For low - cost applications, we can use the
    proposed system instead of using CAM(Content
    Addressable Memory),which is very expensive since
    binary search is a single small module used only for
    searching of data in several applications like
    signature matching in network security.
    CONCLUSION:
    In the proposed system, we are
    implementing the binary search in FPGA, which is
    re-configurable. So the design can be changed based
    on our applications. The FPGA implementation is
    less expensive than the existing CAM, so for lowcost applications we can use the proposed system.

    ACKNOWLEDGEMENT:
    We would like to thank Prof V.
    Suresh, HOD and
    Prof C. Jasmine Project guide for their valuable
    guidance and support throughout this project.

    REFERENCES:
    Anargyros Krikelis, Charles C. Weems (editors)
    (1997). Associative Processing and Processors, IEEE
    Computer Science Press. ISBN 0-8186-7661-2

    Hannum et al.. (2004). System and method for


    resetting and initializing a fully associative array to
    a known state at power on or through machine
    specific state. U.S. Patent 6,823,434. Available by
    searching
    at
    http://patft.uspto.gov/netahtml/PTO/search-bool.html
    Pagiamtis, K. & Sheikholeslami, A. (2006, March).
    Content-Addressable Memory (CAM) Circuits and
    Architectures: A Tutorial and Survey. IEEE J. of
    Solid-State Circuits, 41(3), 712727.

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