CXD2463R

Timing Controller for CCD Camera

Description
The CXD2463R generates the sync signals for 48 pin LQFP (Plastic)
timing control and back end signal processing in a
CCD camera system using a 510H or 760H black-
and-white CCD image sensor.

Features
• Built-in sync signal generation function
• Built-in electronic iris (electronic shutter) function
• Supports low-speed limiter for electronic iris
Absolute Maximum Ratings
• Supports external synchronization
• Supply voltage VDD, AVDD
(Line-Lock, VReset + HPLL)
VSS – 0.5 to VSS + 7.0 V
• Supports automatic external sync discrimination
• Supply voltage VSS VL – 0.5 to VL + 26.0 V
• Window pulse output for backlight compensation
• Supply voltage VH VL – 0.5 to VL + 26.0 V
• Built-in V driver
• Supply voltage VM VL – 0.5 to VL + 26.0 V
• Input voltage VI VSS – 0.5 to VDD + 0.5 V
Applications
• Output voltage VO VSS – 0.5 to VDD + 0.5 V
• Surveillance camera
• Operating temperature
• Door phone camera
Topr –20 to +75 °C
• Storage temperature
Structure
Tstg –55 to +150 °C
Silicon gate CMOS IC

Recommended Operating Conditions

Applicable CCD Image Sensors
• Supply voltage 1 VDD, AVDD
• Type 1/2, 760H black-and-white CCD (EIA/CCIR)
4.75 to 5.25 V
• Type 1/3, 510/760H black-and-white CCD (EIA/CCIR)
• Supply voltage 3 VH 14.55 to 15.45 V
• Type 1/4, 510/760H black-and-white CCD (EIA/CCIR)
• Supply voltage 4 VL –9.0 to –8.0 V
• Supply voltage 5 VM 0 V
• Operating temperature
Topr –20 to +75 °C

Base oscillation
• 1212fH (EIA: 19.0699MHz)
(CCIR: 18.9375MHz)
• 1820fH (EIA: 28.6364MHz)
• 1816fH (CCIR: 28.375MHz)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E98930E59
 Block Diagram

COMP
EVD
EHD/SYNC
EXT
HVDET
VD
HD
EIA
VDD1
VDD2
VSS1
VSS2
TEST
39 37 38 34 33 35 36 27 19 43 16 32 22
NO SIGNAL SYNC
DETECTION DISCRIMINATION
CIRCUIT CIRCUIT
LCIN 40
VD DETECTION TEST CIRCUIT
CIRCUIT SYNC
SEP
LCOUT 41 29 RST
VD HD
HV-PLL SELECTOR RESET
GEN
HV-PLL SELECTOR
CKI 42

1/2 1/606 GATE

IRIS/SHUTTER
1/525
CCD 28 1/910 CK GEN
1/625
1/908 IHD
AVSS 47 21 ESHUT1

H1 45 IVD
EIA COUNTER
H2 46 20 ESHUT2
DECODER

AVDD 44

–2–
GATE TG/SSG
RG 48

SHP 31 SELECTOR

SHD 30

V1 6

V2 3
UP/DOWN ADDER DECODE
V3 4

V4 2

V DRIVER
VL 8

VM 1

SUB 7

5 25 26 23 24 15 17 18 14 12 13 11 10 9

VH
BLC
Vreg

CVSS
CVDD

CLP1
CLP2

CBLK
SYNC
BLCW1
BLCW2
IRIN/ED1
CXD2463R

SPUPV/ED0

SPDNV/ED2
 CXD2463R

Pin Configuration (Top View)

HVDET

SYNC
CBLK
VSS2

CCD
SHD
SHP

RST
EXT

EIA
HD

VD
36 35 34 33 32 31 30 29 28 27 26 25

EVD 37 24 CLP2

EHD/SYNC 38 23 CLP1

COMP 39 22 TEST

LCIN 40 21 ESHUT1

LCOUT 41 20 ESHUT2

CKI 42 19 VDD1

VDD2 43 18 BLCW2

AVDD 44 17 BLCW1

H1 45 16 VSS1

H2 46 15 BLC

AVSS 47 14 CVSS

RG 48 13 IRIN/ED1

1 2 3 4 5 6 7 8 9 10 11 12
VM

V4

V2

V3

VH

V1

SUB

VL

CVDD

Vreg

SPUPV/ED0

SPDNV/ED2

Pin Description

Pin
Symbol I/O Description
No.
1 VM — Power supply (GND for V driver)
2 V4 O Pulse output for CCD vertical register drive
3 V2 O Pulse output for CCD vertical register drive
4 V3 O Pulse output for CCD vertical register drive
5 VH — Power supply (positive power supply for V driver)
6 V1 O Pulse output for CCD vertical register drive
7 SUB O CCD discharge pulse output
8 VL — Power supply (negative power supply for V driver)
9 CVDD — Power supply (for comparator)
10 Vreg — Bias current supply for comparator
11 SPUPV/ED0 I Shutter speed up reference voltage/shutter speed setting
12 SPDNV/ED2 I Shutter speed down reference voltage/shutter speed setting
13 IRIN/ED1 I Iris signal input/shutter speed setting
14 CVSS — GND (for comparator)
–3–
 CXD2463R

Pin
Symbol I/O Description
No.
15 BLC O Window pulse output for backlight compensation
16 VSS1 — GND
17 BLCW1 I Window select 1 for backlight compensation (with pull-down resistor)
18 BLCW2 I Window select 2 for backlight compensation (with pull-down resistor)
19 VDD1 — Power supply
20 ESHUT2 I Sub pulse control (with pull-down resistor)
21 ESHUT1 I Sub pulse control (with pull-down resistor)
22 TEST I Fixed low (with pull-down resistor)
23 CLP1 O Clamp pulse output
24 CLP2 O Clamp pulse output
25 SYNC O Composite sync output
26 CBLK O Composite blanking output
27 EIA I Low: EIA, High: CCIR (with pull-down resistor)
28 CCD I Low: 510H, High: 760H (with pull-down resistor)
29 RST I Reset (low reset). Always input reset pulse after power-on.
30 SHD O Data sample-and-hold pulse
31 SHP O Precharge level sample-and-hold pulse
32 VSS2 — GND
Horizontal PLL/Vertical PLL discrimination signal
33 HVDET O
High: Vertical PLL, Low: Horizontal PLL
External sync/internal sync discrimination signal
34 EXT O
High: External sync, Low: Internal sync
35 VD O Vertical drive output
36 HD O Horizontal drive output
37 EVD I Vertical drive signal input (with pull-up resistor)
38 EHD/SYNC I Horizontal drive signal input/Composite sync input (with pull-up resistor)
39 COMP O Comparator output
40 LCIN I Inverter input for oscillation
41 LCOUT O Inverter output for oscillation
42 CKI I 2MCK input
43 VDD2 — Power supply
44 AVDD — Power supply (for H1, H2, and RG)
45 H1 O H1 clock output for CCD horizontal register drive
46 H2 O H2 clock output for CCD horizontal register drive
47 AVSS — GND (for H1, H2, and RG)
48 RG O Reset gate pulse output

–4–
 CXD2463R

Electrical Characteristics

1) DC Characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C)

Item Symbol Conditions Min. Typ. Max. Unit

Supply voltage VDD 4.75 5.0 5.25 V

Input voltage 1 VIH1 0.7VDD V

(For input pins not listed below) VIL1 0.3VDD V

Input voltage 2 VIH2 0.8VDD V

(Pin 29) VIL2 0.2VDD V
Input voltage 3
(Pins 11 and 12 in electronic iris VIN3 2.0 VDD V
mode)

Input voltage 4
VIN4 VSS VDD V
(Pin 13 in electronic iris mode)

Output voltage 1 VOH1 IOH = –4.0mA VDD – 0.8 V

(Pins 15, 23, 24, 25, 26, 33, 34, 35 and 36) VOL1 IOL = 8.0mA 0.4 V

Output voltage 2 VOH2 IOH = –6.9mA VDD – 0.8 V

(Pins 30, 31 and 48) VOL2 IOL = 3.0mA 0.4 V

Output voltage 3 VOH3 IOH = –17.4mA VDD – 0.8 V

(Pins 45 and 46) VOL3 IOL = 12.0mA 0.4 V

Output voltage 4 VOH4 IOH = –6.0mA VDD – 0.8 V

(Pin 39) VOL4 IOL = 4.0mA 0.4 V

Output voltage 5 VOH5 IOH = –5.0mA VM – 0.25 V

(Pins 2, 3, 4 and 6) VOL5 IOL = 10.0mA VL + 0.25 V

Output voltage 6 VOH6 IOH = –7.2mA VH – 0.25 V

(Pins 4 and 6 (SG)) VOL6 IOL = 5.0mA VM + 0.25 V

Output voltage 7 VOH7 IOH = –4.0mA VH – 0.25 V

(Pin 7) VOL7 IOL = 5.4mA VL + 0.25 V
Feedback resistor 1
RFE1 VIN = VDD or VSS 250k 1M 2.5M Ω
(Pin 42)
Feedback resistor 2
RFE2 VIN = VDD or VSS 250k 1M 2.5M Ω
(Resistor between Pins 40 and 41)
Pull-up resistor RPU VIL = 0V 20k 50k 125k Ω
Pull-down resistor RRD VIH = VDD 20k 50k 125k Ω
AVDD = 5V
CVDD = 5V
IVM 24 mA
VDD1 = 5V
Current consumption VDD2 = 5V
IVL VL = –8.5V 1.9 mA
IVH VH = 15V 0.8 mA
∗ The typical power consumption is 148mW with the ICX054BL load (in the normal operating state).
–5–
 CXD2463R

2) Input/Output Capacitance (VDD = VI = 0V, fM = 1MHz)

Item Symbol Min. Typ. Max. Unit

Input pin capacitance CIN 9 pF
Output pin capacitance COUT 11 pF
I/O pin capacitance CI/O 11 pF

3) Comparator Characteristics (VDD = 5V ± 0.25V, Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit

Indefinite region Vf ±70 mV

Note 1) Input offset voltage and indefinite region

The input offset voltage and indefinite region (region in which the comparator output is not set to high
or low) shown in the figure below exist in the built-in comparator in this IC, so be careful when
designing the external circuit.
Note 2) Pins 11 and 12 in electronic iris mode
Make sure of Pin 11 (SPUPV) < Pin 12 (SPDNV).

5.0V

70mV
Pins 11 and 12
(SPUPV, SPDNV)
70mV

Indefinite region
GND

4) Power-on Reset Condition

4.75V

VDD

RST
0.2VDD

tWRST

(Within the recommended operating condition)

Item Symbol Min. Typ. Max. Unit

Power-on reset period tWRST 35 ns
–6–
 CXD2463R

1. Electronic Iris/Electronic Shutter Function

The electronic iris or electronic shutter can be selected by setting the following pins to different combinations of
high and low.

ESHUT1 ESHUT2
Operating Mode
Pin 21 Pin 20
L L Electronic iris without limiter
H L Electronic iris with limiter EIA: 1/100 (s), CCIR: 1/120 (s)
L H Electronic shutter mode
H H Sub pulse stopped

1) Electronic Iris Mode

Symbol Pin No. Function

IRIN/ED1 13 Iris signal input
SPDNV/ED2 12 Shutter speed down reference voltage
SPUPV/ED0 11 Shutter speed up reference voltage

2) Electronic Shutter Mode

Symbol Pin No. Mode

SPUPV/ED0 11 H L H L H L H L
IRIN/ED1 13 H H L L H H L L
SPDNV/ED2 12 H H H H L L L L
EIA:
1/100
Shutter speed 1/250 1/500 1/1000 1/2000 1/5000 1/10000 1/100000
CCIR:
1/120

–7–
 CXD2463R

2. Backlighting Correction Function

The CXD2463R has a function to output the window pulse for backlight compensation.
The backlight compensation pulse is output from BLC (Pin 15) in the following range according to the high/low
combination of BLCW1 (Pin 17) and BLCW2 (Pin 18).

Window Type for Different Pin Combinations

Window type BLCW1 (Pin 17) BLCW2 (Pin 18)

Full-screen photometry L L
Bottom emphasis photometry H L
Center emphasis photometry L H
Bottom + center emphasis photometry H H

Example of Basic Circuit Configuration

+5V

39k 10k
Iris comparator Iris 10µ
window switch 27 IRIS
13
IRIN/ED1 3.9k
10k 10k 100k 10µ

19 OP+

13 DETOUT
BLC 15
AGC
window switch
10k 1k

100k
CXD2463R CXA1310AQ

Full-screen photometry Bottom emphasis photometry

Center emphasis photometry Bottom + center emphasis photometry

–8–
 CXD2463R

1) Window Pulse Timing Charts

• EIA Mode/Vertical Direction Timing

(1) Full-screen photometry

VD

HD

0.5HD
BLC 20HD 20.5HD

(2) Center emphasis photometry

VD

HD

101HD 101.5HD
BLC 181HD 181.5HD

(3) Bottom emphasis photometry

VD

HD

0.5HD
BLC 181HD 181.5HD

–9–
 CXD2463R

• EIA Mode/Horizontal Direction Timing

(1) Bottom emphasis photometry and full-screen photometry

HD

MCK

X1 X2
BLC

510H 104MCK
X1
760H 154MCK
510H 3MCK
X2
760H 22MCK

(2) Center emphasis photometry

HD

MCK

X1 X2
BLC

510H 272MCK
X1
760H 407MCK
510H 167MCK
X2
760H 252MCK

– 10 –
 CXD2463R

• CCIR Mode/Vertical Direction Timing

(1) Full-screen photometry

VD

HD

0.5HD
BLC 25HD 25.5HD

(2) Center emphasis photometry

VD

HD

121HD 121.5HD
BLC 216HD 216.5HD

(3) Bottom emphasis photometry

VD

HD

0.5HD
BLC 216HD 216.5HD

– 11 –
 CXD2463R

• CCIR Mode/Horizontal Direction Timing

(1) Bottom emphasis photometry and full-screen photometry

HD

MCK

X1 X2
BLC

510H 114MCK
X1
760H 169MCK
510H 3MCK
X2
760H 22MCK

(2) Center emphasis photometry

HD

MCK

X1 X2
BLC

510H 279MCK
X1
760H 416MCK
510H 164MCK
X2
760H 246MCK

– 12 –
 CXD2463R

3. External Sync Function

The CXD2463R supports the three modes of Line-Lock, VReset + HPLL (VD and HD inputs), and VReset +
HPLL (Sync input) as the external sync functions. Each mode is automatically switched according to the
combination of signals input to EHD/SYNC (Pin 38) and EVD (Pin 37).

1) Automatic External Sync Discrimination

Pin EHD/SYNC and EVD pins signal input state

I/O Symbol
No. and HVDET and EXT pins discrimination results
I EHD/SYNC 38 HD No signal HD SYNC No signal
HD after SYNC
I EVD 37 No signal VD VD No signal
separation
O HVDET 33 L H L L L
O EXT 34 L H H H L
VReset VReset
Mode INT LL INT
+ HPLL + HPLL
• If unspecified signals are input for the external signals given above, there may be recognition errors.

2) LL (Line-Lock) Mode

When the V sync clock is externally input to EVD (Pin 37), the result of comparing the falling edge of the clock
and the falling edge of the internal VD is output from COMP (Pin 39). The output polarity is compatible with the
active filter.

EXT-VD
(Pin 37)

INT-VD
(Pin 35)

COMP
(Pin 39)

High impedance state

– 13 –
 CXD2463R

3) VReset + HPLL (VD and HD Inputs) Mode

When the HD cycle clock is externally input to EHD/SYNC (Pin 38) and the V cycle clock is externally input to
the EVD (Pin 37), the CXD2463R sync signal is output as shown below based on the phase difference
between these signals.
Similar to Line-Lock mode, the result of comparing the phase of the falling edges of the HD cycle clock input to
Pin 38 and the CXD2463R internal HD is output from COMP (Pin 39). The PLL is applied using this signal.
Similar to Line-Lock mode, the polarity of the COMP (Pin 39) output is compatible with the active filter. The
phase of the HD falling edge can be shifted up to ±1/4H with respect to the falling edge of the master VD (EXT-
VD).

• EIA/ODD

(1) EXT-VD and EXT-HD have the same phase.

1/4H 1/4H

EXT-VD
(Pin 37 input)

EXT-HD
(Pin 38 input)

VD
(Pin 35 output)

HD
(Pin 36 output)

SYNC
(Pin 25 output)

(2) EXT-VD and EXT-HD have the same phase to +1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

(3) EXT-VD and EXT-HD have the –1/4H to the same phase.

EXT-VD

EXT-HD

VD

HD

SYNC

– 14 –
 CXD2463R

• EIA/EVEN

(1) EXT-VD and EXT-HD have the same phase.

1/4H 1/4H

EXT-VD
(Pin 37 input)

EXT-HD
(Pin 38 input)

VD
(Pin 35 output)

HD
(Pin 36 output)

SYNC
(Pin 25 output)

(2) EXT-VD and EXT-HD have the same phase to +1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

(3) EXT-VD and EXT-HD have the same phase to –1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

– 15 –
 CXD2463R

• CCIR/ODD

(1) EXT-VD and EXT-HD have the same phase.

1/4H 1/4H

EXT-VD
(Pin 37 input)

EXT-HD
(Pin 38 input)

VD
(Pin 35 output)

HD
(Pin 36 output)

SYNC
(Pin 25 output)

(2) EXT-VD and EXT-HD have the same phase to +1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

(3) EXT-VD and EXT-HD have the same phase to –1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

– 16 –
 CXD2463R

• CCIR/EVEN

(1) EXT-VD and EXT-HD have the same phase.

1/4H 1/4H

EXT-VD
(Pin 37 input)

EXT-HD
(Pin 38 input)

VD
(Pin 35 output)

HD
(Pin 36 output)

SYNC
(Pin 25 output)

(2) EXT-VD and EXT-HD have the same phase to +1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

(3) EXT-VD and EXT-HD have the same phase to –1/4H.

EXT-VD

EXT-HD

VD

HD

SYNC

– 17 –
 CXD2463R

4) VReset + HPLL (SYNC Input) Mode

When the specified sync signal is externally input to EHD/SYNC (Pin 38), the EXT-HD separated from this
sync signal is output from HD (Pin 36). This signal is input through the shifter to EVD (Pin 37). At this time, the
CXD2463R sync signal is output as shown below based on the amount by which EXT-HD is shifted. (The
phase can be shifted up to ±1/2H with respect to the falling edge of EXT-HD.)
COMP (Pin 39) outputs the result of comparing the phase of the falling edge of the shifted EXT-HD (signal
input to Pin 37) and the falling edge of the CXD2463R internal HD. The polarity is compatible with the active
filter.

• EIA/ODD
1/2H 1/2H

EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)

(1) Same phase

SFT-HD (1)
(Pin 37 input)

VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)

(2) Delayed phase

SFT-HD (2)

VD

HD

SYNC

(3) Advanced phase

SFT-HD (3)

VD

HD

SYNC

∗ SFT-HD (1) to (3) are the signals after shifting EXT-HD.

– 18 –
 CXD2463R

• EIA/EVEN

1/2H 1/2H

EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)

(1) Same phase

SFT-HD (1)
(Pin 37 input)

VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)

(2) Delayed phase

SFT-HD (2)

VD

HD

SYNC

(3) Advanced phase

SFT-HD (3)

VD

HD

SYNC

– 19 –
 CXD2463R

• CCIR/ODD

1/2H 1/2H

EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)

(1) Same phase

SFT-HD (1)
(Pin 37 input)

VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)

(2) Delayed phase

SFT-HD (2)

VD

HD

SYNC

(3) Advanced phase

SFT-HD (3)

VD

HD

SYNC

– 20 –
 CXD2463R

• CCIR/EVEN

1/2H 1/2H

EXT-SYNC
(Pin 38 input)
EXT-VD
(Generated inside
the CXD2463R)
EXT-HD
(Pin 36 output)

(1) Same phase

SFT-HD (1)
(Pin 37 input)

VD
(Pin 35 output)
HD
(Generated inside
the CXD2463R)
SYNC
(Pin 25 output)

(2) Delayed phase

SFT-HD (2)

VD

HD

SYNC

(3) Advanced phase

SFT-HD (3)

VD

HD

SYNC

– 21 –
 Timing Generator + Sync Generator Block Timing Chart
Vertical Direction EIA (during 510H/760H CCD drive)
FIELD.E FIELD.O

HD
9H
VD
SYNC
20H
BLK

V1

V2

V3

V4
491 2
510H 493
CCD OUT 1 3
492
493 2
760H
CCD OUT
494 1 3
CLP1
CLP2

– 22 –
FIELD.O FIELD.E

HD
9H
VD
SYNC
20H
BLK

V1

V2

V3

V4
492 1 3
510H
CCD OUT 493 2 4
492 494 1 3
760H
CCD OUT 2
493 4
CLP1
CXD2463R

CLP2
 Timing Generator + Sync Generator Block Timing Chart
Vertical Direction CCIR (during 510H CCD drive)

FIELD.E FIELD.O

HD
7.5H
VD
SYNC
25H
BLK

V1

V2

V3

V4
581 2
510H 583
CCD OUT 1 3
582

CLP1
CLP2

– 23 –
FIELD.O FIELD.E

HD
7.5H
VD
SYNC
25H
BLK

V1

V2

V3

V4
582 1 3
510H
CCD OUT 583 2 4

CLP1
CLP2
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Vertical Direction CCIR (during 760H CCD drive)

FIELD.E FIELD.O

HD
7.5H
VD
SYNC
25H
BLK

V1

V2

V3

V4
581 583 2
760H
CCD OUT 1 3
582

CLP1
CLP2

– 24 –
FIELD.O FIELD.E

HD
7.5H
VD
SYNC
25H
BLK

V1

V2

V3

V4
582 1
760H
CCD OUT 583 2

CLP1
CLP2
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction EIA (during 510H CCD drive)
MCK = 104.88ns

0 10 20 30 40 50 60 70 80 90 100 110

HD/BLK 59 104

MCK
(Internal clock)
H1 26 79

H2

RG

SHP

SHD

CLP1 7 23

CLP2 80 94

– 25 –
V1 32 50

44 62
V2

V3 26 56

V4 38 68

SUB 55 72

HSYNC 14 59

EQ 14 36

VSYNC 14

VD
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction CCIR (during 510H CCD drive)
MCK = 105.61ns

0 10 20 30 40 50 60 70 80 90 100 110

HD/BLK 59 114

MCK
(Internal clock)
H1 31 84

H2

RG

SHP

SHD

CLP1 7 23

CLP2 85 99

– 26 –
V1 37 55

49 67
V2

V3 31 61

V4 43 73

SUB 60 77

HSYNC 14 59

EQ 14 36

VSYNC 14

VD
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction EIA (during 760H CCD drive)
MCK = 69.84ns

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170

HD/BLK 90 154

MCK
(Internal clock)
40 118
H1

H2

RG

SHP

SHD

CLP1 12 36

CLP2 119 140

– 27 –
V1 49 76

V2 67 94

V3 40 85

V4 58 103

SUB 85 108

HSYNC 22 90

EQ 22 56

VSYNC 22

VD
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Horizontal Direction CCIR (during 760H CCD drive)
MCK = 70.48ns

0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170

HD/BLK 90 169

MCK
(Internal clock)
40 132
H1

H2

RG

SHP

SHD

CLP1 12 36

– 28 –
CLP2 133 154

V1 51 84

V2 73 106

V3 40 95

V4 62 117

SUB 95 122

HSYNC 22 90

EQ 22 56

VSYNC 22

VD
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Charge Readout Timing
Field Accumulation (during 510H CCD drive)
E: EIA 1CK = 104.88ns
E: 2.51µs C: CCIR 1CK = 105.61ns
(24CK)
C: 2.53µs

HD
(12CK)
E: 1.26µs E: 1.57µs
E: 38.38µs C: 1.27µs (15CK)
(366CK) C: 1.58µs
C: 38.65µs

ODD

V1

V2

V3

– 29 –
V4

(3CK)
E: 0.32µs E: 1.99µs
(19CK)
C: 0.32µs C: 2.00µs
EVEN

V1

V2

V3

V4
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Charge Readout Timing
Field Accumulation (during 760H CCD drive)
E: EIA 1CK = 69.84ns
E: 2.51µs C: CCIR 1CK = 70.48ns
(36CK)
C: 2.54µs

HD
(23CK)
E: 1.61µs E: 2.51µs
E: 40.56µs C: 1.62µs (36CK)
(581CK) C: 2.54µs
C: 40.95µs

ODD

V1

V2

V3

– 30 –
V4

(3CK)
E: 0.21µs E: 2.51µs
(36CK)
C: 0.21µs C: 2.54µs
EVEN

V1

V2

V3

V4
CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 510H CCD drive)

EIA
1/2H
31.78µs (303CK)
1CK = 104.88ns
1.47µs (14CK)

6.19µs (59CK)
HD

10.90µs (104CK)
BLK (HD)

BLK (ODD)

BLK (EVEN)

– 31 –
VD (ODD)

VD (EVEN)

1.47µs (14CK)

4.72µs (45CK)
HSYNC

EQ 2.30µs (22CK) 2.30µs (22CK)

VSYNC 4.72µs (45CK) 4.72µs (45CK)

CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 510H CCD drive)

CCIR
1/2H
32.00µs (303CK)
1CK = 105.61ns
1.48µs (14CK)

6.23µs (59CK)
HD

12.04µs (114CK)
BLK (HD)

BLK (ODD)

BLK (EVEN)

– 32 –
VD (ODD)

VD (EVEN)

1.48µs (14CK)

4.75µs (45CK)
HSYNC

EQ 2.30µs (22CK) 2.30µs (22CK)

VSYNC 4.75µs (45CK) 4.75µs (45CK)

CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 760H CCD drive)

EIA
1/2H
31.78µs (455CK)
1CK = 69.84ns
1.54µs (22CK)

6.29µs (90CK)
HD

10.76µs (154CK)
BLK (HD)

BLK (ODD)

BLK (EVEN)

– 33 –
VD (ODD)

VD (EVEN)

1.54µs (22CK)

4.75µs (68CK)
HSYNC

EQ 2.37µs (34CK) 2.37µs (34CK)

VSYNC 4.75µs (68CK) 4.75µs (68CK)

CXD2463R
 Timing Generator + Sync Generator Block Timing Chart
Effective Horizontal Period (during 760H CCD drive)

CCIR
1/2H
32.00µs (454CK)
1CK = 70.48ns
1.55µs (22CK)

6.34µs (90CK)
HD

11.91µs (169CK)
BLK (HD)

BLK (ODD)

BLK (EVEN)

– 34 –
VD (ODD)

VD (EVEN)

1.55µs (22CK)

4.79µs (68CK)
HSYNC

EQ 2.40µs (34CK) 2.40µs (34CK)

VSYNC 4.79µs (68CK) 4.79µs (68CK)

CXD2463R
 CXD2463R

High-Speed Phase Timing Chart for the Timing Generator Block

MCK
(Internal clock)

H1

H2

RG

CCD OUT

SHP

SHD

– 35 –
 Application Circuit
+5V

• SYNC input external synchronization Reset circuit

• Electronic iris mode H shifter

SYNC IN

0.01µ 10k
36 35 34 33 32 31 30 29 28 27 26 25 4 29 21 20 24
0.1µ 1M 100
37 24 25
100k 10k 10k
38 23 30
1000p 10p 100 CXA1310AQ
39 22 27
40 21
1M
41 20
1p 42 19
CXD2463R
1000p 43 18
39k
44 17
10k
45 16
10µ
46 15

– 36 –
47 14
3.9k VIDEO OUT
48 13

1 2 3 4 5 6 7 8 9 10 11 12 10µ
10k 10k 100k

–9.0 to –8.0V
RG ADJ 36k 50k 50k
+14.55 to +15.45V

VSUB ADJ

CCD OUT
510H/760H black-and-white CCD

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CXD2463R
 CXD2463R

Package Outline Unit: mm

SDT Ass'y

48PIN LQFP (PLASTIC)

9.0 ± 0.2

∗ 7.0 ± 0.1

36 25 S

37 24

(8.0)

0.5 ± 0.2
A B

48 13
(0.22)

1 12
+ 0.05
0.5
0.127 – 0.02
+ 0.08 + 0.2
0.18 – 0.03 1.5 – 0.1
0.13 M

0.1 S

0.1 ± 0.1

+ 0.08
0.127 – 0.02
+ 0.05
0.18 – 0.03
(0.18)
(0.127)
0.5 ± 0.2

0˚ to 10˚
DETAIL B: SOLDER

DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.

PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-48P-L01 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-LQFP48-7x7-0.5 LEAD MATERIAL 42/COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.2g

LEAD SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL COPPER ALLOY
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18µm

– 37 –
 CXD2463R

Package Outline Unit: mm

Amkor Ass'y
48PIN LQFP (PLASTIC)

9.0 ± 0.2 1.7MAX

7.0 ± 0.1 1.4 ± 0.05

36 25

37 24 B

( 8.0 )
A

48 13

1 12
0.5 b
0.07 M S 0.08 S

0.25
0.1 ± 0.05
b=0.21 ± 0.05
0.6 ± 0.15

0.127 – 0.02
+ 0.05
(0.2) (0.125)

DETAIL B
0˚ to 7˚

DETAIL A PACKAGE STRUCTURE

PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-48P-L282 LEAD TREATMENT SOLDER PLATING

EIAJ CODE P-LQFP48-7X7-0.5 LEAD MATERIAL COPPER ALLOY

JEDEC CODE PACKAGE MASS 0.2g

LEAD SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL COPPER ALLOY
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18µm

– 38 – Sony Corporation