I.

INTRODUCTION
A switched-capacitor dc-dc converter is a circuit

Steady-State Analysis and

which employs primarily semiconductor switches and

capacitors to convert or invert dc voltages. Examples

Design of a Switched-Capacitor
DC-DC Converter

of commercially available switched-capacitor dc-de

converters are the

ICL7660

voltage inverter [1] and

the LTl054 voltage regulator [2]. Because they do

not require magnetic component, switched-capacitor
dc-dc converters are small and amenable to monolithic
integration. They are also more efficient than linear

K. D.

regulators and easier to control t han magnetic-based

switched-mode regulators [5]. They are particularly

T. NGO, Member, I E E E

University o f Florida

attractive for low-power, un-card conversion from a

R. WEBSTER

semi-regulated input voltage.

Motorola, Inc.

In spite of the popularity of switched-capacitor

dc-dc converters, the amount of literature devoted
to their understanding and analysis is surprisingly

A representative switched-capacitor dc-de converter topology

is presented, circuit operation is explained, and control strategies

small. Thus, the ubjective of this work is to present

a modeling technique believed to be applicable to

practical switched-capacitor de-dc converter top ologies.

are identified Slate-space averaging is used to analyze steady-state

The technique leads naturally to a quantitative

performance and to develop control criteria and design equations.

description of converter performance and to useful

The analytical results are verified by SPICE simulation.

dcsign criteria.
A representative switched-capacitur dc-dc
converter topology is used tu demonstrate the
modeling principles and to bring forth the issues
and character istics unique to this type of converters.
The topulogy and its operation are described in
the upcoming section. Section

III

then presents the

modeling methodology and derives design-oriented

perfor mance equations. The performance equations
are verified by computer simulation in Section
Section

II.

V concludes

IV.

the paper.

SWITCHED-CAPACITOR DC-DC CONVERTER

TOPOLOGY
An n-stage switched-capacitor dc-dc convertcr

topology is shown in Fig. 1. The topology comprises

a control clement

Me

and n "stages," where

can

be easily recognized as the number of capacitors

in the circuit, and is s hown later tu be the ratio of
the input voltage to the maximum output voltage.
The first stage consists of capacitor

el ,

which acts as

an output filter for the load resistance RL. Each of

Manuscript received April 2, 1992; revised

1 992.
IEEE Log No.

September

II and 29,

T-AES(30/1/13036.

This research was supported in part by the National Science

Foundation under Grant E SC-8957926, and by the University o[

the other stages consists of one capacitor and three

semiconductor devices. Each switching period

consists of a charging interval
interval

d'r"

where

.....

nN

Ts

and a discharge

is the duty ratio. During the

Me and M2,3, are turned on and

and Mf3, nP are turned off to generate

charging interval,

Mh

dTs
... n
,

....

F lorida's Integrated Electronics Center.

the switched topology shown in Fig. 2(a). During the

Authors' addresses: K.

discharge interval,

D.

T.

Ngo, Dept. of Electrical Engineering.

Larsen Hall, Room 334B, University of Florida, Gainesville, FL,

on and

Me

and

Mh,
M2,3

.. ",n

..

,nN

and

Mh

...

,nP

are turned

arc turned uff to generate the

32611; R. Webster, Paging Division, Motorola, Inc.

switched topology shown in Fig. 2(b).

0018- 92.W94i$4.00 1994 IEEE

as the primary control element, and the other

To simplify analysis and design,

92

IEEE TR ANSACTIONS ON AEJ{OSPACE AND ELECTRONIC SYSTEMS

VOL.

30,

Me

is operated

NO. 1

JANUARY 1994

drivc, but is slower and requires more silicon area than

an n-channel MOSFET. The semiconductor devices
besidcs Me can be implemented by n-channel or
p-channel MOSFETs. N -channel devices are probably
easier to drive sincc thcir sources are connected
to the relatively "stable" voltagcs established by
the capacitors. If a p-channel MOSFET is used for
Mf3. . nN' a negative gate drivc is nceded since the
source of the device is already at ground potentiaL
Instead of active devices, Schottky or pn-junction
diodes can be used in place of M2,3,
and Mf1, .nN'
This would grcatly simplify the drives for thc active
devices and lower the converter cost.
A illustrated in Fig. 2, the fundamental principle
of operation of the converter is the switching of a
number of capacitors between a series and a parallel
configuration. The capacitors are connected in series
across the input during the charging phase, and in
parallel across the output during the discharge phase.
Since the voltages across the capacitors do not change
when the topology changes, a simple form of voltage
step-down is realized, the step-down ratio being the
number of capacitors n.
Depending on how Me is controlled, three types of
control are possible: currcnt, resistance, and duty-ratio
controls. The control element Me acl as a current
source in current control, and as a resistor in resistance
controL As is shown later, current control is simpler
to implemcnt bccause the output is a linear function
of Ion in Fig. 2(a). Rcsistance control is better from
the thermal standpoint since the power losses in
the circuit are distributed relatively cvcnly to all
semiconductor dcviccs and capacitor ESRs, instead
of being concentrated in the control clement Me as
in current controL Duty-ratio control is implemented
by modulating thc duration of thc charging phase,
the switching period bcing kcpt constant. When the
duration of the charging phasc is dccreased, the
average output voltage typically decrcascs bccausc less
time becomes available to supply charge. D uty-ratio
control can be combined with current control or
resistance controL A simple implementation of
resistance/duty-ratio control involves modulating
the duration of the charging phase while driving the
field-effect transistor (I<'ETs) to achieve minimum FET
resistances in their respective phases.
Fig. 3 shows the typical waveforms when Me acts
as a current source and the duty ratio is about 0.75.
During the charging interval, C2,3,
is charged by
the constant Jon produced by life, and the voltage
across C2.3,
rises linearly. The current through Cl
is negative because the current required by the load is
larger than Jon, and the voltage across Cl falls linearly.
(It is shown later, howcvcr, that this currcnt may bc
zero or positivc undcr other operating conditions.)
During the discharge interval, the current through
__

___ ,rI

Fig.

An n -stag e switched-capacitor dc-de converter topology.

1.

repeated stage

(a)
Fig.

charging

2.

Me

(b)

is replaced by Ion, and M2.3.___.n by

interval (a);

Ron

during

are replaced by RonP

and Mf.3.
M2.J,, __.nN
___.nP
during discharge interval (b): Capacitor is replaced by its

capacitance and equivalent series resistance in both

intervals.

___

___ .n

semiconductor dcviccs as on/off switches.

Device Me can be implemented by an n-channel
metal-oxide-semiconductor field-effect-transistor
(MOSFET) or a p-channel MOSFET. (MOSFET is
used herein for convenience; other activc dcvicc typcs
can also be used.) A p-channel MOSFET is easier to
NGO & WEBSTER: STE ADY -STATE

ANALYS1S AND

DES1GN

__ _ ,n

OF A SW1TCHED-CAPAClTOR DC-DC CONVERTER

93

discharge

40.Om
2O.Dm

8.

..

I-

. . ...

..

.
. .

charging

-I-

.
fifoL
,f' ......
L:J)' ..
..

Ie

..
.

C= 1o.)

n
j
;
O.Om,t---i=====-I======i--.

...

The assumption of linear capacitor voltage ripple is

met in practice by designing the time constants of the
switched topologies to be sufficiently longer than the
switching period. Under this assumption, state-space
averaging [4] can be used to model the low-frequency
behavior of the converter as follows.

20.1lm
10.4

A.

10.2

9.6Oms

9.65ms

9.7Oms

9.75ms

9.8Oms

9.85ms

T1ffie

Fig.

9.9Oms

9.9Sms

Derivation of Averaged State-Space Equations

In state-space averaging, the weighted average of

the state-space descriptions of the switched topologies
shown in Fig. 2 is taken to be the overall state-space
description of the converter over each switching
period. For the switched topology shown in Fig, 2(a),
the state-space equations take the general form

3. C urrents through CI (dashed trace, top plot) and CZ,J,. ..,n

(solid trace, top plot), voltage ripple across C2,3, . ,n (center plot),
voltage ripples across CI (dashed trace, bottom plot) and output
(solid trace, bottom plot).

(1)

..

C2,:>, . is negative as C2,3, . . discharges into C1 and the

load; the voltage across C2,3,...,n falls relatively linearly,
The current through C] is positive as C1 is charged,
and the voltage across Cl rises relatively linearly.
Note that the average (signified by ) voltage across
C1 is lower than that across C2,3, .. so that C1 can
be charged by C2,3,...,n' Also note that the output
voltage has discontinuities (labeled V}, V;, etc,)
due to the parasitic resistances in Fig. 2. These
discontinuities are expected to complicate the ripple
calculation,
The analysis of current and duty-ratio controls are
presented in the following section. A comprehensive
treatment of resistance control can be found in [3].
.. ,n

. ,n

. ,n

(2)
where X, a, and yare the state, source, and output
vectors, respectively; and 1\,), Bd, Cd, and Dd are
state-space matrices of appropriate dimensions. With
the components modeled as shown in Fig. 2, the
converter is second-order although more than two
capacitors are present. The vectors x, a, and y can be
chosen as

[Ion],

(3)

It is noted that Ion replaces V; as the input in (3).

For the switched topology shown in Fig. 2(b), the
state-space equations are
(4)

III.

ANALYSIS

(5)

In this scction, the average state-space equations

are first derived and solved for the steady-state
capacitor voltages. These voltages are then used in
conjunction with insight on circuit operation provided
by SPICE simulation to determine design-oriented
performance parameters, such as efficiency, input
voltage requirements, and output voltage ripple. The
following assumptions are made in the analysis.
1) The switching time is negligible comparcd with
the charging and discharge intervals.
2) The components in Fig, 1 are modeled as shown
in Fig. 2. The constant on-voltagcs of bipolar junction
transistors and diodes can be accounted for by lumping
them into the input voltage or the output voltage,
effectively lowering Vi or Vo, respectively.
3) The capacitor voltage ripple is linear as
exemplified in Fig. 3.
94

The average state-space equations are then

Ax

+B a
(6)

Ci +Dil
( dCd +d'Cd,)i + (dDd + d'Dd' )il.

(7)

The matrices in (4)-(7) can be shown to be

IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS

(8)

VOL. 30, NO.1

JANUARY 1994

where

'.0

al = -

d
C1(RL + RESR1)

d'
CI(R' II RL + RESRI)

--:::--:-:::-:-;-;----=---

d'
RL
a2 = --:::--:-=:---=----c:---=-- ---=--CI(R' +RFARl II RL) RL + RESRI

'.0

d'
RL
a3 = --=---=----:-:--=-- - -C'(R ' II RL+ RESRJ) RL + R'

(9)

d'
a4 = - -::;-;--;-;::::-:--=----,,----:-=C'(R' + RESRI II RL)

bl =
CI =

dRL

C l(RL + RESRI) ,

2.0

!!.C

d RL
d'(R' II RL)
+
R' II RL + RESR1
RL + RESR1

(10)

d'(RFSRI II RL)
-C2 = -=---'-----;-:--=-'-'---__=__
RESRI II RL+ R'

RF.R
= CI k RESR2,3,.,n
= =
=
;
C2,3,., n
C
RESRI
RESR1
R'

0.'

I'ig,

where C1, its equivalent-series resistance RESR1,

C2,3" ..,n, and its equivalent-series resistance RESR2,3,. . .
are related hy

and

.---__-_------_-__,

RESR +RonP
'
n -1

C'=(n-l)C.

,n

(11)

(12)

In (9)-(10), the terms containing the duty ratio 1

originate from the elements of the matrices in (1)-(2),
and those containing d' (= 1 - d) originate from the
elements of the matrices in (4)-(5). Thc sccond-order
state-space equations (6)-(12) can now be solved to
determine the dc capacitor voltages.

4.

Ve,_J,

Rf,sJ{

,n ;Vo

0.7

0.'
Duty Ratio d

versus duty ratio for n = 3, Va =

= 1000, k = 3,

100, Roo = 500, RonP

10 V,

Thus, the output voltage is directly dependent on R ,>;

this is typical of current-fed topology. It is independent
of the parasitic resistors, for (13) results strictly from
charge conservation for thc capacitors. Equation (13)
suggests that after n has been selected to step Ion
up n times (or step the Vi down n times), 1 or Ion
may be used for fine control of Vo. It is seen later,
however, that the output voltagc ripple is sensitive to
1; therefore, control via Ion is preferred.
In the limit of zero ESR and on-resistance,
(14) suggests that the voltages across all capacitors
become equal. When the ESRs and on-resistances
are non-zero, VC"",n can become increasingly larger
than Vo as d increases and RL decreases. This effect
is demonstrated in Fig. 4, which plots VC,,3, /V o
as a function of d and RL using typical operating
parameters. The reason for this behavior is that as d
increases or RL decreases, more current is demanded
from C2,3,... ,n during the discharge interval. For fixed
Va' RonP, and RESR, VC2.J"n has to increase to supply
more current. Since, VC2,3"n could he several times
largcr than Va' thc operation of Me could be critically
affected if the input voltage is not sufficicntly high.
Thanks to the normalized form in (14), Fig. 4 can
be used to predict Me3"n for other values of circuit
parameters, Since RESR = 100, k = 3, RonP = 1000,
and n = 3, RESRI 100/3 according to (11) and R' =
55n according to (12). Therefore, the curve labeled
RL = 100\1 is also valid for other values of RESR, k,
R onP, and RL as long as RESRJ/RL (10\1/3)/100\1 =
1/30 and R'/RL = 550/1000 = 0.55.
If RESRI is negligible compared with RL, (14) is
simplified to
,n

B.

Steady-State Capacitor Voltages

Under steady-state condition, the derivative of the

state vector in (6) is zero. By equating (6) to zero, the
following steady-state solution is obtained

Vo
M el,..

,n

= VCl = dnIonRL

(13)

Ve
Vo

1+

,(,
,yESRI

IL

(1 4a)

whcrc a tilde C) signifies a steady-state value; Mx

denotes the normalized voltagc of Vx, the base for
voltage normalization being Vo; 1)/ = Rx/Rh is the
normalized resistance of Rx, the base for resistance
normalization being

(14b)

..

Me"

"

- 1

::::1:; + -nd'

l,6ESRI +1/J'

!f',.

NGG & WEBSTER STEADYSTATE ANALYSIS AND DESIGN OF A SWITCHEDCAPACITOR DCDC CONVERTER

(15)
95

The above equation is consistent with Fig. 4, i.e., it

suggests that large parasitic resistances, small load
resistance, and large duty ratio increase the ratio
Ve2" "JVo; a small number of stages also increases
this ratio. Neither switching frcquency nor capacitance
value enters (14) and (15) because these equations
describe average (dc) phenomena.

the constant Ion required by (13). As VG is reduced,

sevcral scenarios from which Voo can be determined
may occur. T he simplest one is as VG reaches zero, the
lowest potential assumed in Fig. 2, (17) is still satisfied
and Me is still in pinch-off mode. According to (17),
this scenario requires

C.

Since VT is usually less than 5 V for commercial

MOSFETs and Vo is the sum of the voltages across
the capacitors and parasitic resistors (Fig. 2(a,
probably (19) is not frequently encountered in practice.
Nevertheless, if it were, Voo could be determined by
first solving for Ion from (13), and then solving for VSG,
which is VDO, from (18).
A more likely scenario is that before VG reaches
zero, (17) is violated, i.e.,

..

Efficiency

The efficiency of conversion can be derived by

applying (13 ):
",

Pout
Pin

-_-

-dV;Ion
V}/RL

Vo
n-.
Vi

(16)

Thus, in the ideal case where Vi is exactly nVo , the

efficiency is 100% since all voltage reduction is done
via the n capacitors which are lossless. Because Ve2,J"n
is larger than Vo as explained in the previous section,
and because voltage drops are incurred across the
semiconductor devices and ESRs, Vi needs to be
larger than nV", reducing the efficiency below 100%.
Therefore, to maximize the efficiency for a given
output, the converter should be designed to make Vi
as close to nVo as possible. The expression rclating thc
lowest Vi to the output voltage and design variables
(e.g., n, d, and semiconductor device parameters) is
derived below.

(19)

(20)
and Me enters the ohmic (linear) mode. The current
through Me is then given by

Ion

Vso

(3 VSG - VT - 2 VSD

(21)

where VSD is the source-to-drain voltage of Me. Since

the voltage at the drain of M e is given by
Vo Vo + (n - I)[Ion(Ron + RESR)+ Ve2,J".] (22)
Vso Vi - Vo is reduced as Vi is reduced. To maintain
the Ion dictated by (B), VG should be decreased such
that VSG is increased to compensate for the reduction
in VSJ). Thus, it can be expected that cvcntually VSG
VSGmax (imposed by gate breakdown, for instance)
if VSGmax < Vi, or V SG Vi if Vi < VSGmax (VSG Vi
when VG has reached zero volt). The procedure to
determine Voo as a function of Vo, n, d, RL, switching
frcqucncy tsw, circuit parameters (e.g., C and REsR),
and device parameters (e.g., VT and (3) is discussed
first for VSG Vi.
Since Vo and Ve2,J.,n contain ripples, Vo is not
constant during the charging interval. To make the
analysis more tractable, it is assumed that the peak
value of VD (at the end of the charging interval)
determines Ion over the entire charging interval.
This assumption provides conservativc results for
the dropout voltage. If the output voltage ripple is
assumed to be negligible, the normalized peak value
MDpk ( VDpk/Vo) of VD is
=

D.

Input Voltage Requirements

If the voltage at the lower end of Me in Fig. 2(a)

is VD, Vi should always be greater than VD so that
the voltage across Me is positive, permitting Ion to
f low from Vi into the capacitor string in Fig. 2(a). T he
minim Vi required by the converter to produce a
given Vo is referred to herein as the drop-out voltage,
VDO. Since the procedure to compute VDO is similar
for n- and p-channel MOSFET's and since a p-channel
Me is easier to drive (because the source of Me is
then tied to the relatively stable Vi), only p-channel
Me is considered below. A detailed analysis of VDo for
an n-channel Me can be found in [3].
To behave as a current source, Me should stay in
the pinch-off (saturation) mode [6], i.e.,

(17)
where VDG is the drain-to-gate voltage, and VT > 0 is
the threshold voltage of Me. The current through the
device is then

Ion

(VSG - VT)2

(18)

where VSG is the source-to-gate voltage, and (3 is

the conductivity parameter of Me. It is seen from
(18) and Fig. 2(a) that as Vi is decreased toward
VDO, the gate voltage VG Vi - VSG should also bc
decreased so that VSG is constant in order to maintain
=

96

MDpk 1 + (n

- 1) [1/Jon +

1/JESR + Me2,J"n + ! Me2,J,

.,,]

(23)

where, assuming Ion is constant during the charging

interval:
dT
IondT
(24)
6. Me
-!C
2,J .,"
VO

..

where T is thc switching period. From (14), (24), and

(23), it can be seen that MDpk increases as fsw, C,

I EEE TRANSACTIONS ON AEROSPACE AND ELEC1RONIC SYSTEMS

VOL.

30,

NO.1 JANUARY 1994

and RL decreases; MOpk incrcases drastically as d

approaches one. Since V; needs to bc grcater than
VOpb the factors which cause MOpk to increase also
cause Voo to increase.
A quadratic equation in Voo can now bc dcrived
from (21) by cquating VSG to Voo, eliminating Iun
from (21) via (13), and replacing Vso by ( Voo
MOpkVo). Solution of this equation yields the following
normalized result:

These discontinuities need to he determined hefore the

output voltage ripple can be found. As seen in Fig. 2,
the output voltage can be expressed as
V"

VC1 + RESRlIcI

(29)

or, in normalized form:

(30)
where Jx 1,/ Ion is the normalized current of In the
base for current normalization being I on; and recall
that the bases for voltage and resistance normalizations
are Vo and R b I1dRL, respectively. Therefore, from
Fig. 3:
=

M2Opk

'JMTMDpk + Mr2 +

--.

--

!JRbVo

(25)
Thus, as Vo or VOpk increases, so does Voo. From
the device standpoint, a larger VT or smaller ;3
(smaller device) corresponds to a larger VDO; this is
consistent with (21), which suggests that V:,O needs to
be increased as VT increases or ,6 decreases to keep Ion
constant.
If Voo is replaced by Vi and Vo by Vo.max in the
quadratic equation that leads to (25), the maximum
output voltage Vo.max attainable with a given Vi can he
found:

(31)
3
M0

"

",BO
11'lC
1

MDO

MDpk

M4
o

Be + 1pESRI Ille
MC1
("1
.

(32)
where Be signifies the beginning of the charging
intcrval, and BD the bcginning of thc dischargc
interval; and the variables on the right-hand sides are
derived as follows.
From (13) and Fig. 2(a), iC1 during the charging
interval is

JC1,d
Thus, the output voltage is maximized by reducing
MOpk and VT or hy increasing (3 or device size.
If VSG is clamped at VSGmax, e.g., to protect the gate
oxide, (21) can be solved with VSG replaced by V:<;Gmax
to give

JIlD.

'

1pESRI C1 '

Ion

Ion

Vo

RL

1 - I1d.

(33)

The peak-to-peak voltage ripple across CI is

"'-lvlc,

IlC
Ill)
Mel
-1\1CI

fc1"dT
CjRb

- --

(1 - I1d)dT
=

RbCI

-.- ...- .-.

(3 4)
It is thus possible to compute

MSGmax - Afy

B
1\1c1

2 6.Mc1 '

(35)

(27)

From Fig. 2(b), iC1 during the discharge interval is

le,

Me')
1pL
V" + V'ESRI II'LIESRI + 1fJL
.

M CI

.n

Y)ESRI + 1b' II1/JL

(36)

where an overstrike is used to indicate the discharge

phase. Since VC,J" , and VCl vary relatively linearly
Finally, if VSG takes on an arbitrary value (Vi - V.::.), during the discharge interval, so does Ic1, as is evident
from Fig. 3. The values of Ic1 at the beginning of
(25) and (26) are still applicable provided that Vcr is
the discharge interval and at the beginning of the
replaced by (VT + V.::. ) .
charging interval can be found by employing the values
of 1'v1.c'.J. , and MC1 at those instants in the above
equation:
E. Output Voltage Ri pple
(28)

"

"

Because of the parasitic resistances, Vo contains

discontinuities vj, V}, vl, and Vo4 as shown in Fig. 3.

BC

iel

BC
Be
fc1(MCl ,Mc2,), J

NGO & WEBSTER: STEADY STATE ANALYSIS AND DESIGN OF A SWITG1FDCA.PACITOR DC-DC CONVERTER

(3 7)
97

where, from Fig. 3

BC
MC2,3,

BD
MC2,3,
..

!l.MCZ,3.....n
- --=-==

=M.
c2,3,..""

.,

. n

2
!l.Mc 3 . n
2, . ..
Mc 2,3... +
2

(38)

10.1
"

where, from Fig. 2(a)

.ll

_ BC
!l.Mc2,3,..,," =MCBD
MCZ,3,.
2,3...
.

. 'I

londT
=

VoC

8:
iii

10.0

_,n

dT

(39)

Rb C'

Instead of (37)-(39), J!!"D and JcBe can also be found

by notmg
that from charge conservation for C1 and the
assumption that lc, is linear (Fig. 3):
Bc

I + JC,
dJ.C,.d "" -d' c,
2

(40)

0.3

5.

Fig.

fsw = 5

Vol, V;. V;, Vo4 versus duty ratio

kHz, RL

1 kn, RESR
e

Therefore,

-dJC"d !l.Jc,
BD _ JC,
- d-' + -2(41)

!l.J.C,

!l.Mc2,3. .,.
..

j.tF,

for n = 3,
=

Vo

50n, RonP

10 V,

lOOn,

3.

2.0

15

,ilL
'r

!l.MCl

(42)

LO

where !l.Mc, is given by (34) and !l.MC2,3. . by (39).

The peak-to-peak voltage ripple across the output is
defined as

0.5

lOn, Ron

0.'

'I{l' + 'I{lESRl II 'I{lL 'I{lESRl + 'I{lL

'I{lESRl + 'I{l' II 'I{lL

!l.Mo

0.7

2.5 r------------.....,..,._7T'T1

where the peak-to-peak ripple on Jc, is computed from

(36):
--

0
Duty Ratio d

max(M;,M;,M;,M:)- min(M;,M;,M;,M;).
(43)

In general, it is difficult to associate the maximum or

the minimum value of Vo with any single discontinuity.
Fig. 5 illustrates this difficulty by showing the variation
of V], V;, V:, and Vo4 as the duty ratio varies for n
3. For d < 0.31, !l.Vo =V; - V:; for 0.31 < d < 0.35,
!l.Vo vg - V:; for 0.35 < d < 0.39, !l.Vo V: - V;;
and for d > 0.39, !l.Vo
Vo4 - V}. Therefore, it is
difficult to derive a simple analytical expression for
!l.Vo for all operating conditions. Nevertheless, i t
may b e postulated from Fig. 5 that for each n , there
is a duty ratio at which !l.Vo is minimum, and far
away from which !l.Vo lVo2 - Vo41. An approximate
equation for !l.Vo can then be derived from (31)-(34)
and (41) be neglecting !l.Jc,:

0.3

0.1

Fig. 6.

I""
e

=
=

j.tF,

kn, RESR

0.'

0.7

Output VOltage ripp le versus duty ratio for

5000 Hz, RL

0
Duty Ratiod

Va

lOn, Ron = son, RonP

10 V,
=

lOon,

3. Solid lines are from exact (43); dashed lines are

from approximate (44); square boxes are data points from SP ICE
simulation.

98

where fsw liT is the switching frequency. The above

equation suggests means to reduce !l.Mo: increasing
fsw and Ct, reducing RESRl, and keeping d away
from zero or one. Both (43) and (44) are plotted
in Fig. 6 so that they may be compared. The figure
shows that the ripple is minimum in the vicinity of
d lin, and increases as d approaches zero or one.
The approximate (44) tends to be conservative for
d> lin, but optimistic for d < lin. It also deviates
noticeably from (43) for large n and for d> lin.
It es timates reasonably well the range of duty ratio
within which the minimum ripple is found, but predicts
=

IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS

VOL. 30, NO.1

JANUARY

1 994

incorrectly that the minimum ripple is zero! This is

because the minimum ripple is tJ. Va V' V;, not
IV; - Va41, according to Fig. 5.
According to Fig. 5, V; Vo4 where the ripple is
minimum. Thus, the corresponding duty ratio can be
found by equating M} from (31) to M; from (3 2) and
solving the resulting equation. The minimum ripple
can then be found by evaluating M] - M; at this duty
ratio. Although the ripple at d lin is not minimum,
it is a reasonable estimate of the minimum ripple.
From (33) and (34), JC"d and tJ.Mc, are both 0 when
d lin. This results in Jp'D > 0 > Jc from (41) and
M; > M; M; > M; from (31) and (32), as is also
seen in Fig. 5. Therefore, the output voltage ripple at
d lin is determined by M] and M; in (32):
=

VgMc

ResTl
Resr2
ReST3

D3
04
0,

M3p

where tJ.JC1 is determined by (42) with tJ.Mc;

F.

..

n'

1) Select n to be M;,min Vi,min/Vn rounded down

to the nearest integer, where Vi,min is the lowest Vi. A
the iteration proceeds, n may have to be decreased if
MDO is found to be larger than Mi,min'
2) Let d lin for minimum output voltage ripple.
3) Determine lon,m ax, the maximum Ion, to supply
RL,min, the minimum load resistance, from (13).
4) Select Mc from its rms or average current,
which can be computcd from Ion,max and d, and
blocking voltage, which is essentially Vi,max. Device
parameters for Mc, such as VT and f3, are thus known.
5) Select other semiconductor components from
their rms or average currents and blocking voltagcs.
The current through M2,3,
is Ion during the charging
interval; the current through Mh
(both Nand P
devices) is the same as the current through C2,3
during the discharge interval, which can be found
from chargc-balance considcration, c.g., (40) for C1.
The blocking voltages across these devices can be
conservatively taken to be Vi,max. After these devices
have been selected, their on-resistances Ron and RonP
arc known.
6) Estimate Mez""n from (15) in the first iteration,
or compute Mcv from (14) in the subsequent
iterations; the estimated value is optimistic since V'ESR
is not induded in (15).
=

XFETP

lOu

Fig.

1(X)m

7.

L=lu

W=200u L=lu

PMOS(Kp=IO.OOu Vlo=2)

D(Is;:..{) tp Rs=16

RELTOL:::{105

probe

W=200u

NMOS(Kp=20.00u Vto=2)

XFETN

tran

Design Considerations

The input to a design problem are usually a range

of input voltage Vi, a range of load resistance RI.,
output voltage VOl output voltage ripple tJ.Vo, and
switching frequency [<;'N' The following procedure
may be iterated to seled the number of stages n,
duty ratio d, control current I on, the semiconductor
devices, capacitance C and its RESR, and the ratio
k
CI/C2,3, .

XFETP

.model XL)

O.

IC=1O.0

10

.model XFE1P

(45)

IC=IO.O

5u

10

M2p

option

IC=IO.O

5u

XD
XD
XD
XD

02

V'ESRltifc,

W=200u L=lu

3.33333
10
10
Ik

RI

model

XFETP

15u

C3

Id=l/n

II

C2

M; - M;

40 0 III .lu 150u 200u)

pulse (40 35.8915 0, lu.5u l.5Ou 200u)

Me

pulse (0

II

CI

tJ.M o

40

10

VgP

tJ.M o,min

Practical file for Fig. 3 (Scott Hams, 08/06/92)

Vi

Ibv=D Ip)

lTL4=50 ITL5=()
UI C

Typical

SPICE

input file.

7) Determine MDpk from (25) or (27) by letting

M DO

Mi.min.

8) One equation relating C and RESR is thus

established by (23) and (24); another equation can
be found from the data on C and RESR published
by capacitor manufacturers. A common form for the
second equation is RESR coef CCXP, where eoef and
exp arc constants related to fabrication technology,
device geometry, dimensions, etc. [8]. From these
two equations, C and the corresponding RESR can be
determined.
9) Select k in (11) from (45) or the exact (43) to
satisfy the requirement on output voltage ripple.
10) Now that all component values are available,
MDO can be recomputed from (23)-(24), (14), and (25)
or (27). If 11,1Do > Mi,min, C may be increased to reduce
MDO toward Mi,mlD' If C becomes unacceptably large,
the number of stages n needs to be reduced, sacrificing
efficiency. The design cycle then repeats, starting from
Step 2.
=

IV.

VERIFICATION BY SIMULATION

.... n

...

Extensive simulation by PSPICE [7] has been

performed to verify the analysis over a wide range
of load resistance, duty ratio, number of stages,
capacitance, and other parameters [3]. A typical
SPICE input file is shown in Fig. 7. The control
element Mc is a p-channel MOSFET driven by the
pulse generator V g Me. The other switches which are
on during the charging interval are implemented by
diodes D2 and D3. The switches which are on during
the discharge interval are implemented by diodes D4,
D5, and p-channel MOSFET's M2p and M3p driven
hy the pulse generator Vgp.

,n

.... ,n

n
.

NGO & WEBSTER: STEADY-STATE ANALYSIS Al'D DESIGN

OF

A SWITCIIED-C APACITOR DC-DC CONVERTER

99

4.0

c
D

----.cr-....

RL=1 kQ, W!L=IOO

RL=lOkU WIL=I
__

______-

c
o

----- - -8 . _ . . ..___H.....
R.::.L_=lO_ --:kU,,:W: _'_L=_I_O__-:'
___
';------;c:-:- ----:::
o .:.
R
Duty atio

3.0

Normalized dropout voltage for n = 3, Vo = 10 V,

5000 Hz, RESR = 50, Ron = 160, C = 5 J-lF, k = 3,
{.In = 20 (J1I/L)J-lNV2, {Jp = 20 (J1I/L)IJNV2, VTn = 2 V,

Fig. 8.
fsw

VTp

2 V. Square boxes are data points from SPICE simulation.

Fig. 6 compares the solid curves generated by (43)

with the square boxes representing simulation data for
the output voltage ripple; the two sets of data match
closely in general. Fig. 8 compares the prediction
generated by (25) with the simulation data for the
drop-out voltage. Prediction results are larger (more
conservative) than simulation results by less than 5%
in most cases. Agreement better than 1% between
simulation and state-space-averaging results was also
observed for Vo in (13) and MC3" n in (14) for a wide
range of circuit parameters.
V.

RE FER EN CES
[I]

(1988)

ln tersil Appli ca tion s Han dbook.

and Applications of the ICL7660 CMOS

P rinciples

Voltage

Converter, 1988,632-<>40.

[2]

(1989)
Application notes for the LT1054 switchcd capacitor
voltage converter with regulator.

I jn ea r Technology Corporation, 1989.

[3 ]

Webster, J. R. (1991)

[4]

Middlebrook, R. D, and Cuk, S. (1976)

CONCLUSION

Power int egrat ed switched-<:apacitor volt ag e re g u la tor.

Master's Thesis, University of F l orida, Gainesville, 1991.

A switched-capacitor dc-dc converter topology

which consists of n stages of semiconductor switches
and capacitors has been described. The switches
connect the capacitors across the input source during
the charging phase and then across the load during the
discharge phase to step down the input voltage by a
nominal ratio n. Further control of the output voltage
is possible via current, resistive, or duty-ratio control.
Based on the observation that the ripple on the
capacitor voltages are generally linear in practicc,
state-space avcraging has been used to derive the
average state-space equations for a generalized n-stage
switched-capacitor converter circuit. If the components
of the stages match, the n-capacitor topOlogy can bc
modeled by simple second-ordcr dynamic equations.
The modeling equations have been solved to determine
the average capacitor voltages, control-to-output
transfer characteristic, efficiency, drop-out voltage,
and output voltage ripple. It has bccn found that

100

in the presence of parasitic resistances, the voltage

across the switched capacitors can be several times
the voltage across the output capacitor, especially for
a small number of stages, duty ratio approaching unity,
or hcavy loading. The efficiency can be improved by
increasing the number of stages, but this raises the
drop-out voltage. The drop-out voltage can be lowered
by increasing the switching frequency and capacitance,
and by kccping the duty ratio away from zero or one.
If low output voltage ripple is desired, the duty ratio
should be the inverse of the number of stages. Other
means for lowering the output ripple are raising the
switching frcqucncy and capacitance and minimizing
parasitic resistances.
Both exact and approximate equations which are
useful for design have been derived for the practical
performance parameters. A design procedure based
on these equations was then described. Finally, the
analytical results have been verified by extensive
simulation by PSPICE.

IEEE

A gene ral

unified approach to modelling

switchingconverter power stages.

IEEE Power Electronics Specialists Conference

(1976), 18-34.
[5]

R ecord,

Middlebrook. R. D. (1988)

Transformerless converters with la rge conversion ratios.

JF;F:F: Transactions on Power Electronics, 3, 4 (Oct.1988),

84-488
4
.

[6]

Sedra, A. S., and Smith,

K.

C. (1991)

Microelectronic Circuits, (3rd Ed.)

Englewood Cliffs, NJ: Saunders College Publishing, 1991.

[7]

Tu in en g a ,

P.

W.

(1988)

(SPICEA guide to circuit simulation and a n alysi s

PSPICE).

[8]

us ing

Englewood Cliffs, NJ: PrenticeHall, In c ., 1988.

Prymak, J. (1989)

Software for
capacitors.

calcu lating

power capability for MLC ceramic

In Proceedings of the High Frequency Power C onversion

Conference, 1989, 167-174.

TR<\NSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS

VOL.

30,

NO.1

JANUARY 1994

Khai D. T. Ngo (S'82-M'84) received a B.S. degree in electrical and electronics

engineering from California State Polytechnic University, Pomona, in 1979, and
an M.S. and Ph.D. degree in the same discipline from California Institute of
Technology, Pasadena, in 1980 and 1 984, respectively.
He was a member of 1echnical Staff at General Electric Corporate Research
and Development Center in Schenectady, NY from 1984 to 1988. He is currently
an Asociate Professor in the Department of Electrical Engineering at the
University of Florida, Gainesville. His research interests are low-profile magnetics,
power integrated circuits, power semiconductor devices, power quality and
high-frequency converters for utility systems.

James Rodney Webster

received the B.S.E.E. and the M.E. degrees in electrical

engineering from the University of Florida, Gainesville, in 1989 and 1991,
respectively.
Since graduating he has worked tor the Paging Division of Motorola, Inc.
on the design of full-custom, mixed-signal CMOS VLSI for low-power paging
applications.

NGO & WEBSTER: STEADYSTATE ANALYSIS AND DESIGN OF A SWITCHED-CAPACITOR DC-DC CONVERTER

101