Arithmetic-logic units

The four-bit adder

An arithmetic-logic unit, or ALU, performs many different arithmetic

and logic operations. The ALU is the heart of a processoryou could
say that everything else in the CPU is there to support the ALU.
Heres the plan:
Well show an arithmetic unit first, by building off ideas from the
adder-subtractor circuit.
Then well talk about logic operations a bit, and build a logic unit.
Finally, we put these pieces together using multiplexers.
We show the same examples as from the book (pp. 360-365), but things
are re-labeled to be clearer in LogicWorks. Cin and S0 are also treated a
little differently.

The basic four-bit adder always computes S = A + B + CI.

But by changing what goes into the adder inputs A, B and CI, we can
change the adder output S.
This is also what we did to build the combined adder-subtractor circuit.

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Arithmetic-logic units

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Its the adder-subtractor again!

Arithmetic-logic units

So we have one adder performing two separate functions.

Sub acts like a function select input which determines whether the
circuit performs addition or subtraction.
Circuit-wise, all Sub does is modify the adders inputs A and CI.

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Modifying the adder inputs

The multi-talented adder

Here the signal Sub and some XOR gates alter the adder inputs.
When Sub = 0, the adder inputs A, B, CI are Y, X, 0, so the adder
produces G = X + Y + 0, or just X + Y.
When Sub = 1, the adder inputs are Y, X and 1, so the adder output
is G = X + Y + 1, or the twos complement operation X - Y.

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Arithmetic-logic units

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Some more possible functions

By following the same approach, we can use an adder to compute other

functions as well.
We just have to figure out which functions we want, and then put the
right circuitry into the Input Logic box .

We already saw how to set adder inputs A, B and CI to compute ei ther

X + Y or X - Y.
How can we produce the increment function G = X + 1?
One way: Set A = 0000, B = X, and CI = 1

How about decrement: G = X - 1?

How about transfer: G = X?

(This can be useful.)

A = 1111 (-1), B = X, CI = 0

A = 0000, B = X, CI = 0
This is almost the same as the
increment function!

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The role of CI

Table of arithmetic functions

The transfer and increment operations have the same A and B inpu ts,
and differ only in the CI input.
In general we can get additional functions (not all of them usef ul) by
using both CI = 0 and CI = 1.
Another example:
Twos-complement subtraction is obtained by setting A = Y, B = X,
and CI = 1, so G = X + Y + 1.
If we keep A = Y and B = X, but set CI to 0, we get G = X + Y. This
turns out to be a ones complement subtraction operation.

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Arithmetic-logic units

Here are some of the different possible arithmetic operations.

Well need some way to specify which function were interested i n, so
weve randomly assigned a selection code to each operation.

S2

S1

S0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

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0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Desired arithmetic operation

G (A + B + CI)
X
X+1
X+Y
X+Y+1
X + Y
X + Y + 1
X1
X

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(transfer)
(increment)
(add)
(1C subtraction)
(2C subtraction)
(decrement)
(transfer)

X
X
X
X
X
X
X
X

0
1
0
1
0
1
0
1

Arithmetic-logic units

S2

S1 A

0
0
1
1

0
1
0
1

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S2

S1

0
0
1
1

0
1
0
1

0000
Y
Y
1111

S1

Yi

Ai

0
0

0
0

0
1

0
0

0
0

1
1

0
1

0
1

1
1

0
0

0
1

1
0

1
1

1
1

0
1

1
1

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10

Primitive gate implementation

We could build this circuit using primitive gates.

If we want to use K-maps for simplification, then we should first
expand out the abbreviated truth table.
The Y that appears in the output column (A) is actually an input .
We make that explicit in the table on the right.
Remember A and Y are each 4 bits long!
S2

0000
Y
Y
1111

We want to pick one of these four possible values for A, dependi ng on

S2 and S1.

Primitive gate-based input logic

All we need to do is compute the adder input A, given the arithmetic

unit input Y and the function select code S (actually just S 2 and S1).
Here is an abbreviated truth table:

Required adder inputs

A
B
CI
0000
0000
Y
Y
Y
Y
1111
1111

(1C subtraction)
(2C subtraction)
(decrement)
(transfer)

Building the input logic

This second table shows what the adders inputs should be for each of
our eight desired arithmetic operations.
Adder input CI is always the same as selection code bit S 0.
B is always set to X.
A depends only on S2 and S1.
These equations depend on both the desired operations and the
assignment of selection codes.
Selection code
S2
S1
S0

(transfer)
(increment)
(add)

Arithmetic-logic units

Mapping the table to an adder

Arithmetic operation
X
X+1
X+Y
X+Y+1
X + Y
X + Y + 1
X1
X

From the truth table, we can find

an MSP:

S2

0
1

0
0
Yi

S1
1
0
1
1

Ai = S 2Yi + S 1Yi

11

Again, we have to repeat this

once for each bit Y3-Y0,
connecting to the adder inputs
A3-A0.

This completes our arithmetic

unit.

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Bitwise operations

1 0 1 1
AND 1 1 1 0
1 0 1 0

Bitwise operations in programming

Most computers also support logical operations like AND, OR and NOT,
but extended to multi-bit words instead of just single bits.
To apply a logical operation to two words X and Y, apply the operation
on each pair of bits Xi and Y i:
OR

1 0 1 1
1 1 1 0
1 1 1 1

1 0 1 1
XOR 1 1 1 0
01 01

Languages like C, C++ and Java provide bitwise logical operations:

These operations treat each integer as a bunch of individual bits:

They are not the same as the operators &&, || and !, which treat each
integer as a single logical value (0 is false, everything else is true):

Bitwise operators are often used in programs to set a bunch of B oolean

options, or flags, with one argument.
Easy to represent sets of fixed universe size with bits:
1: is member, 0 not a member. Unions: OR, Intersections: AND

& (AND)

13 & 25 = 9

Weve already seen this informally in twos-complement arithmetic,

when we talked about complementing all the bits in a number.

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You can use bitwise-OR to generate a broadcast address, for sending

data to all machines on the local network.
192.168. 10. 43 = 11000000.10101000.00001010.00101011

0. 0. 0. 31 = 00000000.00000000.00000000.00011111
192.168. 10. 63 = 11000000.10101000.00001010.00111111

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S1

S0

Output

0
0
1
1

0
1
0
1

Gi = X iYi
Gi = X i + Y i
G i = X i Yi
Gi = X i

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Combining the arithmetic and logic units

Inputs:
X (4 bits)
Y (4 bits)
S (2 bits)
Outputs:
G (4 bits)

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true && true = true

Well just use multiplexers and some

primitive gates to implement this.
Again, we need one multiplexer for each
bit of X and Y.

Our simple logic unit

01101 & 11001 = 01001

A logic unit supports different logical

functions on two multi-bit inputs X and Y,
producing an output G.
This abbreviated table shows four
possible functions and assigns a selection
code S to each.

192.168. 10. 32 = 11000000.10101000.00001010.00100000

~ (NOT)

Defining a logic unit

IP addresses are actually 32-bit binary numbers, and bitwise operations

can be used to find network information.
For example, you can bitwise-AND an address 192.168.10.43 with a
subnet mask to find the network address, or which network th e
machine is connected to.
192.168. 10. 43 = 11000000.10101000.00001010.00101011
& 255.255.255.224 = 11111111.11111111.11111111.11100000

because

^ (XOR)

Arithmetic-logic units

Bitwise operations in networking

because

13 && 25 = 1

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| (OR)

17

Now we have two pieces of the puzzle:

An arithmetic unit that can compute eight functions on 4 -bit inputs.
A logic unit that can perform four functions on 4-bit inputs.

We can combine these together into a single circuit, an arithmet ic-logic

unit (ALU).

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Our ALU function table

This table shows a sample

function table for an ALU.
All of the arithmetic operations
have S3=0, and all of the logical
operations have S 3=1.
These are the same functions we
saw when we built our arithmetic
and logic units a few minutes ago.
Since our ALU only has 4 logical
operations, we dont need S 2. The
operation done by the logic unit
depends only on S1 and S0.

A complete ALU circuit

The / and 4 on a line indicate that its actually four lines.

S3

S2

S1

S0

Operation

0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

G=X
G=X+1
G=X+Y
G=X+Y+1
G = X + Y
G = X + Y + 1
G=X1
G=X

1
1
1
1

x
x
x
x

0
0
1
1

0
1
0
1

G = X and Y
G = X or Y
G=XY
G = X

Cout should be ignored

when logic operations are
performed (when S3=1).

4
4

G is the final ALU output.

When S3 = 0, the final
output comes from the
arithmetic unit.
When S3 = 1, the
output comes from the
logic unit.
The arithmetic and logic units share the select inputs S1
and S0, but only the arithmetic unit uses S2.

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Comments on the multiplexer

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20

The completed ALU

Both the arithmetic unit and the logic unit are active and produce
outputs.
The mux determines whether the final result comes from the
arithmetic or logic unit.
The output of the other one is effectively ignored.
Our hardware scheme may seem like wasted effort, but its not really.
Deactivating one or the other wouldnt save that much time.
We have to build hardware for both units anyway, so we might as
well run them together.
This is a very common use of multiplexers in logic design.

This ALU is a good example of hierarchical design.

With the 12 inputs, the truth table would have had 2 12 = 4096 lines.
Thats an awful lot of paper.
Instead, we were able to use components that weve seen before to
construct the entire circuit from a couple of easy -to-understand
components.
As always, we encapsulate the complete circuit in a black box so we
can reuse it in fancier circuits.
4
4
4

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Arithmetic summary

In the last few lectures we looked at:

Building adders hierarchically, starting with one-bit full adders.
Representations of negative numbers to simplify subtraction.
Using adders to implement a variety of arithmetic functions.
Logic functions applied to multi-bit quantities.
Combining all of these operations into one unit, the ALU.
Where are we now?
We started at the very bottom, with primitive gates, and now we
can understand a small but critical part of a CPU.
This all built upon our knowledge of Boolean algebra, Karnaugh m aps,
multiplexers, circuit analysis and design, and data representations.

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