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Tutorial1 Creating Simple Xilinx ISE Project

1. The document describes the steps to create a simple project in Xilinx ISE 9.2 including creating a new project, adding a VHDL source file, writing a sample VHDL program, creating a constraint file, generating a configuration file, and loading the configuration file onto an FPGA device. 2. It provides instructions for each step with descriptions of windows and options in the Xilinx ISE software. 3. The sample VHDL program uses a counter that counts up and down based on the state of an input switch and outputs the count on LEDs.

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113 views

Tutorial1 Creating Simple Xilinx ISE Project

1. The document describes the steps to create a simple project in Xilinx ISE 9.2 including creating a new project, adding a VHDL source file, writing a sample VHDL program, creating a constraint file, generating a configuration file, and loading the configuration file onto an FPGA device. 2. It provides instructions for each step with descriptions of windows and options in the Xilinx ISE software. 3. The sample VHDL program uses a counter that counts up and down based on the state of an input switch and outputs the count on LEDs.

Uploaded by

hohhooh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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COE758 XilinxISE9.

2Tutorial1
CreatingSimpleProject
g
p
j

StartXilinxISEsoftware,andpressOKonTipoftheDaytogettoascreen
as shown above
asshownabove
2

CreatenewprojectbyselectingFile>NewProject
New window will open
Newwindowwillopen.
3

Projectlocation selectthedirectoryfortheprojects
Project Name selectprojectname.Noticehowdirectorywithsame
ProjectName
select project name Notice how directory with same
projectnameisaddedintheProjectLocationtextfield.
PressNext>

IntheDevicePropertiesselectionofthedeviceandpackageisdone.
In
the Device Properties selection of the device and package is done.
Family:Spartan3E
Device:XC3S500E
Package:FG320
S d 5
Speed:5
PreferredLanguage:VHDL
KeeptherestofthesettingsandpressNext>

Inthiswindowyoucaneitheraddnewsource,orleaveitforlaterasitis
done in this tutorial
doneinthistutorial.
Press Next>severaltimesuntilfinishandpressFinish onthelastwindow.
6

Whennewprojectiscreatedsourcefilescanbeadded.Rightclickonthe
device and select New Source
deviceandselectNewSource.
NewWizardwindowisopened
7

SelectVHDLModuleandenterthenameofthevhdl sourcefile.
Press Next>
PressNext>
8

Inthiswindowinputandoutputsignalsarespecified.
Notice that for led and switch signals Bus checkbox is selected and size of
NoticethatforledandswitchsignalsBuscheckboxisselectedandsizeof
thebusisspecified.
PressNext>

Lastwindowinthewizardshowssummaryofthesourceincludinginputs
and outputs for that module
andoutputsforthatmodule.
PressFinish toaddsourcefiletoproject.
10

WhensourcefileisaddedISEtoolwindowshouldlookasabove
Next step is to add actual processing source code
Nextstepistoaddactualprocessingsourcecode.
11

SampleVHDLprogram
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;

Librarydefinitions

entitytutorialis
Port(clk :inSTD_LOGIC;
led:outSTD_LOGIC_VECTOR(7downto 0);
switch:inSTD_LOGIC_VECTOR(3downto 0));
endtutorial;

Input/Output definitions

architectureBehavioraloftutorialis
signalcounter:std_logic_vector(29downto 0);

counterdefinition

begin
process(clk)
begin
if(clk'Event andclk='1')then
if(switch(0)='1')then
counter<=counter+'1';
else
counter<=counter'1';
endif;
endif;
endprocess;
led(7downto 0)<=counter(29downto 22);

Counter counting up if switch is on, and counting


down if switch is off. Every addition occurs on every
positive clock edge.
edge
OutputofthetopbitsofcounteronLEDs

end Behavioral;
endBehavioral;

12

WhenprogramiswrittenitssyntaxcanbecheckedbyexpandingSynthesize
and double clicking on Check Syntax If errors are found double click on
anddoubleclickingonCheckSyntax.Iferrorsarefound,doubleclickon
errorandcorrectthemistake.
13

WhenalloftheerrorswerecorrectedandSynthesishasbeencompleted
successfullyanassignmentofinputsandoutputshastobedone.Since
y
g
p
p
FPGAisalreadymountedonthedevelopmentplatforminputsandoutputs
arerestrictedandhavetobespecified.
Onlyonesthatareusedhavetobespecifiedintheconstraintfile.
Add new source same way as before but this time select Implementation
Addnewsourcesamewayasbefore,butthistimeselect
Implementation
ConstraintFile,andspecifynamefortheconstraintfile.
Press Next>

14

UCFconstraintfileisaddedtotheVHDLfile.
Select constraint file and double click on Edit Constraints (Text)
SelectconstraintfileanddoubleclickonEditConstraints(Text)
15

EnterconstraintsfortheLEDsandSwitchesthatarelocatedinthelower
right corner
rightcorner.
ClocksignalforallofthedesignsisconnectedtopinC9onFPGA
16

Whencodeisdebuggedandconstraintfileiscorrectlyenteredwecan
generate a configuration file Right click on Generate Programming File and
generateaconfigurationfile.RightclickonGenerateProgrammingFileand
selectRun.
Similarlyasbefore,iferrorsoccur,doubleclickontheerrorandcorrectit.

17

Ifconfigurationfileisgeneratedsuccessfullywecanloaditontothe
platform.
platform
18

ExpandGenerateProgrammingFile,rightclickonConfigureDevice
(iMPACT) and select Run iMPACT wizardwindowwillopen.
(iMPACT)andselectRun.iMPACT
wizard window will open
19

SelecttopoptionofconfiguringusingJTAGandpressFINISH.

20

OntheinitialiMPACT loadwizardwillprompttoselectconfigurationfiles
for all of the devices present on the JTAG chain Press Esc keyforallofthe
forallofthedevicespresentontheJTAGchain.PressEsc
key for all of the
windows.RightclickontheleftdevicewhichrepresentsSpartan3EFPGA
andselectAssignNewConfigurationFile

21

ToloadprogramontheFPGAdevice,rightclickontheFPGAiconandselect
Program Programming properties window will be shown
Program.Programmingpropertieswindowwillbeshown.
22

OntheProgrammingPropertiesmakesureverifyisUNCHECKED.
Press OK atwhichpointconfigurationfilewillbeuploadedtoFPGA.
PressOK
at which point configuration file will be uploaded to FPGA
23

Conclusion
Thiscompletesfirstsimpletutorialwhichincluded:
Creatingnewproject
Adding
AddingVHDLsourcefile
VHDL source file
Writingsimpleprograminvolvinginputsandoutputswithsimpleinternal
counter
Creatingconstraintfile
Generatingconfigurationfile
G
i
fi
i fil
UploadingconfigurationtoFPGAdevice
SecondtutorialcoversuseofinternalBlockRAM
f
andaChipscope
p p Proembedded
logicanalyzerwhichisrequiredforcompletionofallthelabsinthecourse.

24

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