Latches
Positive Latch
Library IEEE;
Use ieee.std_logic_1164.all;
Entity platch is
Port (E, D: in std_logic;
Q: out std_logic);
End platch;
Architecture behavioral of platch is
Begin
Process (E, D)
Begin
If (E ='1') then
Q <= D;
End if;
End process;
End behavioral;
Positive-Edge triggered Clock Flip Flop
Library IEEE;
Use ieee.std_logic_1164.all;
Entity FF is
Port (clk, D: in std_logic;
Q: out std_logic);
End FF;
Architecture behavioral of FF is
Begin
Process (clk)
Begin
If (clk'event and clk='1') then
Q <= D;
End if;
End process;
End behavioral;
Flip-Flop with Negative-Edge Clock and Asynchronous Clear
Library IEEE;
Use ieee.std_logic_1164.all;
Entity FF is
Port (Clk, D, CLR: in std_logic;
Q: out std_logic);
End FF;
Architecture behavioral of FF is
Begin
Process (Clk, CLR)
Begin
If (CLR = 1) then
Q <= '0';
Elsif (Clk'event and Clk=0) then
Q <= D;
End if;
End process;
End behavioral;
Flip-Flop with Positive-Edge Clock and Synchronous Set
Library IEEE;
Use ieee.std_logic_1164.all;
Entity FF is
Port (Clk, D, S: in std_logic;
Q: out std_logic);
End FF;
Architecture behavioral of FF is
Begin
Process (Clk)
Begin
If (Clk'event and Clk='1') then
If (S='1') then
Q <= '1';
Else
Q <= D;
End if;
End if;
End process;
End behavioral;
4-bit Register with Positive-Edge Clock, Asynchronous reset
and Clock Enable
Library IEEE;
Use ieee.std_logic_1164.all;
Entity reg_4 is
Port (Clk, CE, RST: in std_logic;
D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0));
End reg_4;
Architecture behavioral of reg_4 is
Begin
Process (Clk, RST)
Begin
If (RST='1') then
Q <= "0000";
Elsif (Clk'event and Clk=1) then
If (CE='1') then
Q <= D;
End if;
End if;
End process;
End behavioral;
Counters
4-bit Unsigned Up Counter with Asynchronous Clear
Library IEEE;
Use ieee.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity counter is
Port (Clk, CLR: in std_logic;
Q : out std_logic_vector (3 downto 0));
End counter;
Architecture reg_4 behavioral of counter is
Signal tmp: std_logic_vector (3 downto 0): ="0000";
Begin
Process (Clk, CLR)
Begin
If (CLR='1') then
Tmp <= "0000";
Elsif (Clk'event and Clk='1') then
Tmp <= tmp + 1;
End if;
End process;
Q <= tmp;
End behavioral;
4-bit Unsigned Down Counter with Synchronous Set
Library IEEE;
Use IEEE. std_logic _1164.all;
Use IEEE.std_logic_unsigned.all;
Entity counter is
Port (Clk, S: in std_logic;
Q: out std_logic_vector (3 downto 0));
End counter;
Architecture behavioral of counter is
Signal tmp: std_logic_vector (3 downto 0):="0000";
Begin
Process (Clk)
Begin
If (Clk'event and Clk='1') then
If (S='1') then
Tmp <= "1111";
Else
Tmp <= tmp - 1;
End if;
End if;
End process;
Q <= tmp;
End behavioral;
4-bit Unsigned Up Counter with Asynchronous Load from Input
Library IEEE;
Use IEEE.STD_LOGIC_1164.ALL;
Use IEEE.STD_LOGIC_ARITH.ALL;
Use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity counter is
Port (Clk, ALOAD: in std_logic;
D: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (3 downto 0));
End counter;
Architecture behavioral of counter is
Signal tmp: std_logic_vector (3 downto 0):="0000";
Begin
Process (C, LOAD, D)
Begin
If (ALOAD='1') then
Tmp <= D;
Elsif (C'event and C='1') then
Tmp <= tmp + 1;
End if;
End process;
Q <= tmp;
End behavioral;
4-bit Unsigned Up/Down counter with Asynchronous Clear
Library IEEE;
Use ieee.std_logic_1164.all;
Use IEEE.std_logic_unsigned.all;
Entity counter is
Port (Clk, CLR, UP_DOWN: in std_logic;
Q: out std_logic_vector (3 downto 0));
End counter;
Architecture behavioral of counter is
Signal tmp: std_logic_vector (3 downto 0): ="0000";
Begin
Process (Clk, CLR)
Begin
If (CLR='1') then
Tmp <= "0000";
Elsif (Clk'event and Clk='1') then
If (UP_DOWN='1') then
Tmp <= tmp + 1;
Else
Tmp <= tmp - 1;
End if;
End if;
End process;
Q <= tmp;
End behavioral;
8-bit Shift-Left Register with Positive-Edge Clock,
Asynchronous Clear, Serial In, and Serial Out
Library IEEE;
Use ieee.std_logic_1164.all;
Entity shift is
Port (CLK, SI, CLR: in std_logic;
SO: out std_logic);
End shift;
Architecture behavioral of shift is
Signal tmp: std_logic_vector (7 downto 0):="00000000";
Begin
Process (CLK, CLR)
Begin
If (CLR='1') then
Tmp <= (others => '0');
Elsif (CLK'event and CLK='1') then
Tmp <= tmp (6 downto 0) & SI;
End if;
End process;
SO <= tmp (7);
End behavioral;
8-bit Shift-Left Register with Positive-Edge Clock, Serial In, and
Parallel Out
Library IEEE;
Use ieee.std_logic_1164.all;
Entity shift is
Port (Clk, SI : in std_logic;
PO : out std_logic_vector(7 downto 0));
End shift;
Architecture behavioral of shift is
Signal tmp: std_logic_vector (7 downto 0):="00000000";
Begin
Process (Clk)
Begin
If (Clk'event and Clk='1') then
Tmp <= tmp (6 downto 0) & SI;
End if;
End process;
PO <= tmp;
End behavioral;
8-bit Shift-Left Register with Positive-Edge Clock,
Asynchronous Parallel Load, Serial In, and Serial Out
Library ieee;
Use ieee.std_logic_1164.all;
Entity shift is
Port (Clk, SI, ALOAD: in std_logic;
D: in std_logic_vector (7 downto 0);
SO: out std_logic);
End shift;
Architecture behavioral of shift is
Signal tmp: std_logic_vector (7 downto 0):="00000000";
Begin
Process (Clk, ALOAD, D)
Begin
If (ALOAD='1') then
Tmp <= D;
Elsif (Clk'event and Clk='1') then
Tmp <= tmp (6 downto 0) & SI;
End if;
End process;
SO <= tmp (7);
End behavioral;
8-bit Shift-Left Register with Positive-Edge Clock, Synchronous
Parallel Load, Serial In, and Serial Out
Library IEEE;
Use ieee.std_logic_1164.all;
Entity shift is
Port (Clk, SI, SLOAD: in std_logic;
D: in std_logic_vector (7 downto 0);
SO: out std_logic);
End shift;
Architecture behavioral of shift is
Signal tmp: std_logic_vector (7 downto 0): ="00000000";
Begin
Process (Clk)
Begin
If (Clk'event and Clk='1') then
If (SLOAD='1') then
Tmp <= D;
Else
Tmp <= tmp (6 downto 0) & SI;
End if;
End if;
End process;
SO <= tmp (7);
End behavioral;
8-bit Shift-Left/Shift-Right Register with Positive- Edge Clock,
Serial In, and Parallel Out
Library IEEE;
Use ieee.std_logic_1164.all;
Entity shift is
Port (Clk, SI, LEFT_RIGHT: in std_logic;
PO: out std_logic_vector (7 downto 0));
End shift;
Architecture behavioral of shift is
Signal tmp: std_logic_vector (7 downto 0): ="00000000";
Begin
Process (Clk)
Begin
If (Clk'event and Clk='1') then
If (LEFT_RIGHT='0') then
Tmp <= tmp (6 downto 0) & SI;
Else
Tmp <= SI & tmp (7 downto 1);
End if;
End if;
End process;
PO <= tmp;
End behavioral;
