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Ece4750 Cheat Sheet

this is a great guide for writing good verilog code. read this, be a pro, and make big bucks working as chip designer

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278 views2 pages

Ece4750 Cheat Sheet

this is a great guide for writing good verilog code. read this, be a pro, and make big bucks working as chip designer

Uploaded by

WangAlex
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 4750 Linux, Git, Verilog Cheat Sheet

SSH Access to ECE Computing Resources


ssh -X [email protected]

Linux Commands
man command
pwd
echo ${ENVVAR}
echo "string"

display help for given command


display current working dir
display given environment variable
display given string

mkdir A
make dir A to B
mkdir -p A/B
make all dirs in path A/B
ls
list contents of current working dir
ls -la
list contents of current working dir (verbose)
ls A
list contents of dir A
ls *.txt list files with .txt suffix in current working dir
tree
recusrively list contents of current working dir
cd A
change current working dir to A
cd ..
change current working dir to parent dir
cd ~
change current working dir to home dir
cp a b
cp -r A B
mv a b
mv A B
rm a
rm -r A
rmdir A

copy file a to b
copy dir A to B
move file a to b
move dir A to B
remove file a
remove dir A
remove dir A

cat a
display file a
less a
display file a with paging and search
grep "string" a
search file a for given string
grep -r "string" A
recursively search files in dir A
tar -czvf a.tgz A
create archive a.tgz of dir A
tar -xzvf a.tgz
extract archive a.tgz
cmd >
cmd
cmd_a
cmd_a

a
redirect output of cmd to newly created file a
a
redirect output of cmd to append to file a
&& cmd_b
execute cmd_a and then execute cmd_b
| cmd_b
send output from cmd_a to cmd_b

source setup-ece4750.sh source setup script for course


quota
check disk usage
trash
move file to ${HOME}/tmp/trash
cd ${HOME}/.snapshot
change dir to snapshots

Git Commands
help cmd
display help on git command cmd
init
initialize current working dir as a git repo
add a
add file a to staging area
add A
add directory A to staging area
commit
commit staged files
commit -m "msg"
commit staged files w/ commit msg
commit -a -m "msg" commit tracked files w/ commit msg
log
show history log of previous commits
status
show status of local repo
checkout a
revert file a to last commit
checkout A
revert dir A to last commit
clone url
clone repo at given URL
pull
pull remote commits to local repository
push
push local commits to remote repository
remote -v
list remote repositories
whatchanged show incremental changes for each commit
xstatus
xlog
xadd

compact status display


compact log display
add all tracked, modified files to staging area

Setting up GitHub
git remote set-url origin \
[email protected]:<id>/<repo>.git
git push --set-upstream origin master

ECE 4750 Lab Management Script


help
display help
start lab
start lab and become owner
list
list all labs
update lab
update lab with changes from course staff
backup lab
backup lab for safe-keeping
finish lab
create tarball of lab for CMS submission
trash lab
trash local/shared repository for lab
add-partner netid
add lab partner
remove-partner netid
remove lab partner
list-partner
list lab partners
join-owner netid
join lab already started by owner
enable-github gid
enable GitHub as the remote repo
disable-github
disable GitHub as the remote repo

Common Makefile Targets


all
check
clean
sproj-all
sproj-check
sproj-clean
sproj-eval

make all simulators for eval


make, run, summarize all tests
remove all generated files
make simulators for subproject
make, run, summarize tests for subproject
remove all generated files for subproject
make, run, summarize simulators for eval

Example Verilog Development Session


% source setup-ece4750.sh
% ece4750-lab-admin start ece4750-tut3-verilog
%
%
%
%
%

cd ${HOME}/ece4750/ece4750-tut3-verilog
mkdir build
cd build
../configure
make

%
%
%
%
%
%
%
%

make ex-gcd-GcdUnit-test
./ex-gcd-GcdUnit-test
./ex-gcd-GcdUnit-test +verbose=1
./ex-gcd-GcdUnit-test +test-case=1 +trace=1
./ex-gcd-GcdUnit-test +test-case=1 +dump-vcd
gtkwave ex_gcd_GcdUnit-test.vcd &
make ex-gcd-check
make check

%
%
%
%

make ex-gcd-sim
./ex-gcd-sim +input=random-a +stats
./ex-gcd-sim +input=random-b +stats
make ex-gcd-eval

ECE 4750 Linux, Git, Verilog Cheat Sheet


Synthesizable Verilog Keywords
logic
logic [N-1:0]
& | ^ ^~ ~ (bitwise)
&& || !
& ~& | ~| ^ ^~ (reduction)
+ - >> << >>> == != > <= < <=
{}
{N{}} (repeat)
?:
if else
case, endcase
begin, end
module, endmodule
input, output
assign
parameter
localparam
genvar
generate, endgenerate
generate for
generate if else
generate case
$clog2()
$bits()
named port connections
named parameter passing

Synthesizable Verilog Keywords


with Limitations
always
enum
struct
casez, endcase
task, endtask
function, endfunction
= (blocking assignment)
<= (non-blocking assignment)
typedef
packed
$signed()

Verilog Coding Conventions


Use subproject prefix for file, module,
macro names
Try to keep lines less than 7480 chars
Include header comment at top of each file
Include comments to explain code
Explicitly include file dependencies
Use include guards
Use only spaces, no tabs
Use two-space indentation
Use CamelCase for module names
Use under_scores for variable, port,
instance names
Use ALL_CAPS for macro names
Use p_ prefix for parameters
Use c_ prefix for constants
Use clk and reset for clock and reset
Use informative variable names
Use localparams for local constants
Always declare type of all ports
Align port declarations, one per line
Align port connections, one per line
Align parameter config, one per line
Avoid positional port connections
Avoid positional parameter config
Prefer ternary operator over if
Prefer case over casez
Clearly separate sequential logic from
combinational logic
FSMs have three blocks: state,
state transitions, state outputs
Use tasks for compact state output table
Datapaths should use structural
composition of child modules

ex-regincr-RegIncr.v

ex-regincr-RegIncr.t.v

// = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
// Registered Incrementer
// = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

// = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
// ex - regincr - RegIncr Unit Tests
// = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

ifndef E X _ R E G I N C R _ R E G _ I N C R _ V
define E X _ R E G I N C R _ R E G _ I N C R _ V

include " ex - regincr - RegIncr . v "


include " vc - test . v "

module e x _ r e g i n c r _ R e g I n c r
(
input logic
clk ,
input logic [7:0] in ,
output logic [7:0] out
);

module top ;
VC_TEST_SUITE_BEGIN (
" ex - regincr - RegIncr " )

// Sequential logic
logic [7:0] temp_reg ;
always @ ( posedge clk )
temp_reg <= in ;
// Combinational logic
logic [7:0] temp_wire ;
always @ (*)
temp_wire = temp_reg + 1;
// Combinational logic
assign out = temp_wire + 1;
endmodule
endif /* E X _ R E G I N C R _ R E G _ I N C R _ V */

Example Line Trace for GCD

1:
2:
3:
9:
10:
11:
12:

src
0f05
#
#
#
#
#
#

>
>
>
>
>
>
>

in
A
0f:05(xx
#
(0f
#
(0a
#
(05
#
(00
#
(05
#
(05

B
xx
05
05
05
05
00
00

ST out sink
I )
>
C-)
>
C-)
>
C-)
>
Cs)
>
C )
>
D )05 > 05

Legend for val/rdy interfaces in line traces


spaces !valid && ready
valid && !ready
#
.
!valid && !ready
msg
valid && ready

// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - // Test e x _ r e g i n c r _ R e g I n c r
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - logic [7:0] t1_in ;
logic [7:0] t1_out ;
e x _ r e g i n c r _ R e g I n c r t1_reg_incr
(
. clk ( clk ) ,
. in
( t1_in ) ,
. out ( t1_out )
);
// Helper task
task t1
(
input logic [7:0] in ,
input logic [7:0] out
);
begin
t1_in = in ;
#1;
V C _ T E S T _ N O T E _ I N P U T S _ 1 ( in );
VC_TEST_NET ( t1_out , out );
#9;
end
endtask
// Test case
V C _ T E S T _ C A S E _ B E G I N ( 1 , " basic " )
begin
#1;
t1 ( 8 ' h00 , 8 ' h ?? );
t1 ( 8 ' h13 , 8 ' h02 );
t1 ( 8 ' h27 , 8 ' h15 );
t1 ( 8 ' hxx , 8 ' h29 );
end
VC_TEST_CASE_END
VC_TEST_SUITE_END
endmodule

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