2, 4 and 8 Mutiplex LCD Driver: em Microelectronic
2, 4 and 8 Mutiplex LCD Driver: em Microelectronic
2, 4 and 8 Mutiplex LCD Driver: em Microelectronic
EM MICROELECTRONIC - MARIN SA
V6118
2, 4 and 8 Mutiplex LCD Driver
Description
Features
Applications
Pad Assignment
Fig. 2
Fig. 1
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V6118
Handling Procedures
This device has built-in protection against high static
voltages or electric fields; however, anti-static
precautions must be taken as for any other CMOS
component. Unless otherwise specified, proper operation
can only occur when all terminal voltages are kept within
the voltage range. Unused inputs must always be tied to
a defined logic voltage level.
Operating Conditions
Parameter
Symbol Min
Operating
TA
-40
Temperature
Logic supply voltage
VDD
2
LCD supply voltage
VLCD
2
Typ
5
5
Max Unit
+85 C
6
8
V
V
Table 2
Table 1
Electrical Characteristics
VDD = 5V 10%, VLCD = 2 to 7V and TA = -40 to +85C, unless otherwise specified
Parameter
Symbol
Test Conditions
Min.
Dynamic supply current
ILCD
See note 1
Dynamic supply current
IDD
See note 1 at TA = 25C
Dynamic supply current
IDD
See note 1
Dynamic supply current
IDD
See note 2
Standby supply current
ISS
See note 3 at TA = 25C
Control Signals DI, CLK, STR, FR
and COL
Input leakage
IIN
0 < VIN < VDD
Input capacitance
CIN
at TA = 25C
Low level input voltage
VIL
0
High level input voltage for DI, STR, VIH
2.0
FR and COL
High level input voltage for CLK
VIH
3.0
Data Output DO
High level output voltage
VOH
IH = 4 mA
2.4
Low level output voltage
VOL
IL = 4 mA
Driver Outputs S1 S40
Driver impedance (note 4)
ROUT
IOUT = 10A, VLCD = 7V
Driver impedance (note 4)
ROUT
IOUT = 10A, VLCD = 3V
Driver impedance (note 4)
ROUT
IOUT = 10A, VLCD = 2V
Bias impedance V1, V2, V3 (note 5) RBIAS
IOUT = 10A, VLCD = 7V
Bias impedance V1, V2, V3 (note 5) RBIAS
IOUT = 10A, VLCD = 3V
Bias impedance V1, V2, V3 (note 5) RBIAS
IOUT = 10A, VLCD = 2V
DC output component
VDC
see Tables 4a & 4b,
VLCD = 5V
Typ.
100
0.1
3
200
0.1
Max.
150
1
12
250
1
Units
1
8
100
0.8
VDD
nA
pF
V
V
VDD
0.4
V
V
0.5
1.2
9
16
18
30
1.5
2.5
30
50
20
25
A
A
A
A
A
k
k
k
k
k
k
mV
Table 3
All outputs open, STR at VSS, FR = 400 Hz, all other inputs at VDD.
All outputs open, STR at VSS, FR = 400 Hz, fCLK = 1 MHz, all other inputs at VDD.
All outputs open, all other inputs at VDD.
This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S40
when a given voltage bias level is driving the outputs (S1 to S40)
Note 5: This is the impedance seen at the segment pin. Outputs measured one at a time.
Note 1:
Note 2:
Note 3:
Note 4:
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V6118
Column Drivers
Outputs
FR Polarity
S1 to S40
logic 1
S1 to S40
logic 0
S1 to S40
S1 to S40
logic 1
logic 0
COL
logic 0
logic 0
Column Data
logic 1
logic 1
Measured*
Sx* - VSS
VLCD - Sx*
logic 0
logic 0
logic 0
logic 0
VLCD - Sx*
Sx* - VSS
Guaranteed
FR Polarity
logic 1
logic 0
COL
logic 1
logic 1
Column Data
logic 1
logic 1
Measured*
VLCD - Sx
Sx - VSS
S1 to Sn*
S1 to Sn*
logic 1
logic 0
logic 1
logic 1
logic 0
logic 0
Sx - VSS
VLCD - Sx
Guaranteed
VLCD - Sx = Sx - VSS 25 mV
VLCD - Sx = Sx - VSS 25 mV
Table 4b
Min.
120
120
Typ.
Max.
200
200
20 (note 1)
30 (note 1)
100
100
10
200
128/256/512
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
Table 5a
Note 1: tDS + tDH minimum must be 100 ns. If tDS = 20 ns then tDH 80ns.
Note 2: V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number.
VDD = 2 to 6V, VLCD = 2 to 8V and TA = -40 to +85C
Parameter
Symbol
Test Conditions
Clock high pulse width
tCH
Clock low pulse width
tCL
Clock and FR rise time
tCR
Clock and RF fall time
tCF
Data input setup time
tDS
Data input hold time
tDH
Data output propagation
tPD
CLOAD = 50pF
STR pulse width
tSTR
CLK falling to STR rising
tP
STR falling to CLK falling
tD
FR frequency (Vers. 2/4/8)
FFR (note 2)
Min.
500
500
Typ.
Max.
200
200
100 (note 1)
150 (note 1)
400
500
10
1
128/256/512
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Hz
Table 5b
Note 1: tDS + tDH minimum must be 500 ns. If tDS = 100 ns then tDH 400ns.
Note 2: V6118 n, FR = n times the desired LCD refresh rate where n is the V6118 version number.
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V6118
Timing Waveforms
Fig. 3
Address Bits
Addr. 1 to Addr. n*
Display RAM
LCD Row
(Note1)
10
1000
10000000
10000000
Row 1
01
0100
01000000
01000000
Row 2
0010
00100000
00100000
Row 3
0001
00010000
00010000
Row 4
00001000
00001000
Row 5
00000100
00000100
Row 6
00000010
00000010
Row 7
00000001
00000001
Row 8
Note1: A set address bit corresponds to a write enabled RAM
address, the same data can be written to more than one RAM
address by setting the required address bits .
V6118 2
V6118 4
V6118 8
Address
Fig. 4
Display RAM
LCD Row
(Note1)
10000000
100000000
10000000
10000000
Row 1
01000000
01000000
01000000
01000000
Row 2
00100000
00100000
00100000
Row 3
00010000
00010000
00010000
Row 4
00001000
00001000
Row 5
00000100
00000100
Row 6
00000010
00000010
Row 7
00000001
00000001
Row 8
Note1: A set address bit corresponds to a write enabled RAM
address, the same data can be written to more than one RAM
address by setting the required address bits .
V6118 2
V6118 4
V6118 8
Address
Fig. 5
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V6118
Block Diagram
Note 1: When logic 1 the STR input forces the display RAM address 10000000 (which corresponds to row 1)
has to be selected by the 8 bit sequences. Cascaded V6118s are synchronized in this way. The LCD
picture is rebuilt starting from row 1 each time data is written to the display RAM.
Fig. 6
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V6118
Pin Assignment
Name
S1..S40
V3
V2
V1
VLCD
FR
DI
DO
CLK
STR
VDD
COL
VSS
Function
LCD outputs, see Table 7
LCD voltage bias level 3 (note 1, 2)
LCD voltage bias level 2 (note 1)
LCD voltage bias level 1 (note 1)
Power supply for the LCD
AC input signal for LCD driver output
Serial data input
Serial data output
Data clock input
Data strobe, blank, synchronize input
Power supply for logic
Column only driver mode
Supply GND
Name
S1
S2
S3
S4
S5
S6
S7
S8
S9S40
COL inactive
V6118 (2)
Row1
Row2
Col1
Col2
Col3
Col4
Col5
Col6
Col738
COL
active
V6118 (4)
Row1
Row2
Row3
Row4
Col1
Col2
Col3
Col4
Col536
V6118 (8)
Row1
Row2
Row3
Row4
Row5
Row6
Row7
Row8
Col132
Col1
Col2
Col3
Col4
Col5
Col6
Col7
Col8
Col940
Table 7
Table 9
LCD Bias
Type
Configuration
V6118 (2)
n=2
1:2 MUX
Alt + Pleshko
V6118 (4)
n=4
1:4 MUX
1/3 Bias
V6118 (8)
n=8
1:8 MUX
5 levels
VOP
(note 1)
VOFF (rms)
2n
1
n
= 3.69
3
4 Levels
1/4 Bias
5 Levels
1+
3
n
= 3.4
VON (rms)
VOFF (rms)
n +1
= 2.41
n 1
1+
8
= 1.73
n
n + 15
= 1.446
n+3
Table 8
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V6118
Row and Column Multiplexing Waveform V6118 (2)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 7
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V6118
Row and Column Multiplexing Waveform V6118 (4)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 8
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V6118
Row and Column Multiplexing Waveform V6118 (8)
VOP = VLCD - VSS, VSTATE = VCOL - VROW
Fig. 9
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V6118
Functional Description
Supply Voltage VLCD, VDD, VSS
The voltage between VDD and VSS is the supply voltage for
the logic and the interface. The voltage between VLCD and
VSS is the supply voltage for the LCD and is used for the
generation of the internal LCD bias levels. The internal
LCD bias levels have a maximum impedance of 25 k for
a VLCD voltage from 3 to 8V. Without external connections
to the V1, V2, V3 bias level inputs, the V6118 can drive
most medium sized LCD (pixel area up to 4'000 mm2).
For displays with a wide variation in pixel sizes, the
configuration shown in Fig. 13 can give enhanced contrast
by giving faster pixel switching times. On changing the
row polarity (see Fig. 7, 8 and 9) the parallel capacitors
lower the impedance of the bias level generation to the
peak current, giving faster pixel charge times and thus a
higher RMS "on" value. A higher RMS "on" value can
give better contrast. IF for a given LCD size and
operating voltage, the "off" pixels appear "on", or there is
poor contrast, then an external bias level generation
circuit can be used with the V6118. An external bias
generation circuit can lower the bias level impedance and
hence improve the LCD contrast (see Fig. 12). The
optimum values of R, Rx and C, vary according to the
LCD size used and VLCD. They are best determined
through actual experimentation with the LCD.
For LCD with very large average pixel area (eg. up to
10'000 mm2), the bias level configuration shown in Fig. 14
should be used.
When V6118s are cascaded, connect the V1, V2 and V3
bias inputs as shown in Fig. 10. The pixel load is
averaged across all the cascaded drivers. This will give
enhanced display contrast as the effective bias level
source impedance is the parallel combination of the total
number of drivers. For example, if two V6118 are
cascaded as shown in Fig. 10, then the maximum bias
level impedance becomes 12.5 k for a VLCD voltage from
3 to 8V.
Table 8 shows the relationship between V1, V2 and V3 for
the multiplex rates 2, 4 and 8. Note that VLCD > V1 > V2 >
V3 for the V6118 2 and V6118 8, and for the V6118 4,
VLCD > V1 > V2.
Data Input /Output
The data input pin, DI, is used to load serial data into the
V6118. The serial data word length is 40 bits when COL
is inactive, and 48 bits when it is active. Data is loaded in
inverse numerical order, the data for bit 40 (bit 48 when
COL is active) loaded first with the data for bit 1 last. The
column data bits are loaded first and then the address bits
(see Fig. 4 & 5).
The data output pin, DO, is used in cascaded applications
(see Fig. 10). DO transfers the data to the next cascaded
chip. The data at DO is equal to the data at DI delayed by
40 clock periods, when COL is inactive and 48 clock
10
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V6118
It is recommended that data transfer to the V6118 should
be synchronized to the FR signal to avoid a falling or
rising edge on the FR signal while writing data to the
V6118. The LCD pixels change polarity with the FR
signal. On the edges of the FR signal current spikes will
appear on the VSS and VLCD supply lines. If the supply
lines have high impedance then voltage spikes will
appear. These voltage spikes could interfere with data
loading on the DI and CLK pins.
Driver Outputs S1 to S40
There are 40 LCD driver outputs on the V6118. When
COL is inactive, the outputs S1 to Sn function as row
drivers and the outputs S(n+1) to S40 function as column
drivers, where n is the V6118 version no. (2, 4 or 8).
When COL is active, all 40 outputs function as column
drivers (see Table 6). There is a one to one relationship
between the display selected RAM and the LCD driver
outputs. Each pixel (segment) driven by the V6118 on the
LCD has a display RAM bit which corresponds to it.
Setting the bit turns the segment "on" and clearing it turns
it "off".
COL Input
The V6118 functions as a row and column driver while the
COL input is inactive. When active, the COL input
configures the V6118 to function as a column driver only.
The former row outputs function as column outputs. In
cascaded applications, one V6118 should be used in the
row and column configuration ( COL inactive) and the rest
Applications
Two V6118 8s Cascaded
By connecting the V1, V2 and V3 bias outputs as shown, the pixel load is averaged across all the drivers. The
effective bias level source impedance is the parallel combination of the total number of drivers. For example, if
two V6118 are cascaded as above, then the maximum bias level impedance becomes 12.5 k.
Fig. 10
11
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V6118
Microprocessor Interface and LCD Blanking
1) When the microprocessor is reset, the port pin will be configured as an input and so the STR line would float.
The pull-up resistor will ensure that the LCD is blank while the system reset line is active and after until the
port pin is set up by software.
Writing Data to the Display RAM while keeping the LCD Blank
Fig. 11
12
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V6118
Enhanced Switching from V6118
C = 1F
Rx is given by the formula
Rx = 4(24 k) ((VDISP/VLCD) -1)
Fig.13
Fig.14
All dimensions in mm
Fig.15
13
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V6118
Dimensions of QFP Package
All dimensions in mm
Fig.16
14
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V6118
Package and Ordering Information
Dimensions of Chip Form
Ordering Information
The V6118 is available in the following packages:
V6118 2 52F
V6118 4 52F
V6118 8 52F
Chip form
V6118 2 Chip*
V6118 4 Chip*
V6118 8 Chip*
V6118 2 TAB
V6118 4 TAB
V6118 8 TAB
*on request
When ordering, please specify the complete part
number and package
EM Microelectronic-Marin SA cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an EM
Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice
at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
EM Microelectronic-Marin SA, 09/04, Rev. L
15
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