16th IEEE Asian Test Symposium

Enhanced Broadside Testing for Improved Transition Fault Coverage

Irith Pomeranz1
School of Electrical & Computer Eng.
Purdue University
W. Lafayette, IN 47907, U.S.A.
[email protected]

and

Abstract

during test application, and the change can be made at a

slow speed.
Both skewed-load and broadside tests have the
disadvantage that they may leave some faults undetected,
even though the faults can be detected under enhanced
scan. Although the detection of some of these faults can
be considered overtesting [4]-[5], there are cases where it
is important to be able to detect the presence of delay
defects even if they cannot be detected under functional
operation conditions. For example, when attempting to
improve the yield for a new design or a new process, or
when a product needs to be highly reliable. Several
design-for-testability (DFT ) approaches have been proposed for improving the fault coverage achievable by
scan-based tests [6]-[11]. The method of [6] requires
reordering of the flip-flops in a scan chain, while the
method of [7] requires the insertion of dummy scan flipflops. In [8], [9] and [11], the basic scan flip-flops are
enhanced with additional logic and control inputs to
improve the fault coverage of broadside tests [9] and eliminate the need for a fast changing scan enable signal [11].
The method of [10] selects a subset of the flip-flops to
operate in skewed-load mode while the remaining flipflops operate in broadside mode during test application.
The skewed-load flip-flops still require a fast changing
scan enable signal, but the reduction in the number of
skewed-load flip-flops makes the design of the scan
enable logic easier.
In [12] it was shown that the use of multiple scan
chains helps improve the transition fault coverage
achieved by skewed-load tests. Multiple scan chains are
typically used for reducing the test application time by
reducing the number of clock cycles required for a scan
operation. As a by-product, the fault coverage of transition faults under skewed-load tests is improved as well.
This can be seen as follows. For a circuit with n scan
chains, there are n flip-flops whose data inputs are driven
from external scan chain inputs. The values of these flipflops can be determined arbitrarily under the second pattern of a two-pattern skewed-load test. The higher the
value of n , the more flexibility exists in determining the

The use of multiple scan chains was shown to

improve the coverage of transition faults achieved by
skewed-load tests. For broadside tests, the number of scan
chains does not affect the transition fault coverage. We
describe an enhanced broadside configuration under
which increasing the number of scan chains helps
increase the fault coverage. In the enhanced
configuration, the first flip-flop of a scan chain operates in
skewed-load mode while the other flip-flops operate in
broadside mode. This provides flexibility in determining
the value of the first flip-flop of every scan chain under the
second pattern of a broadside test, thus increasing the
transition fault coverage. We also describe a procedure
that makes small modifications to a given scan chain
configuration in order to improve the transition fault coverage.

1. Introduction
Three types of tests for transition faults in scanbased circuits exist. Under enhanced scan tests [1] every
two-pattern test can be applied to the circuit. Under
skewed-load tests [2] the first pattern of a test is scanned
in. The second pattern is obtained by an additional shift of
the scan chains. Under broadside tests [3] the first pattern
of a test is scanned in. The second pattern is obtained by
latching the next state of the first pattern, and using it as
the present state for the second pattern. Enhanced scan
requires special scan flip-flops that are capable of holding
two values. Skewed-load tests in standard scan circuits
require a scan enable signal that changes at the circuit
speed in order to switch from scan mode, required for the
generation of the first and second patterns during test
application, to functional mode, required for latching the
circuit response to the test. Broadside tests do not have
this requirement since the scan enable changes from scan
mode to functional mode after the first pattern is generated
1. Research supported in part by SRC Grant No. 2004-TJ-1244.
2. Research supported in part by SRC Grant No. 2004-TJ-1243.

1081-7735/07 $25.00 2007 IEEE

DOI 10.1109/ATS.2007.16

Sudhakar M. Reddy2
Electrical & Computer Eng. Dept.
University of Iowa
Iowa City, IA 52242, U.S.A.
[email protected]

479
473

second pattern of the test. This flexibility can be used for

improving the fault coverage.
In this work we study the improvement in fault coverage of transition faults due to the use of multiple scan
chains under broadside tests. Without any modification,
broadside tests cannot benefit from the use of multiple
scan chains. Considering the first pattern of the test, any
pattern can be shifted in regardless of the number of scan
chains. Considering the second pattern of the test, in
broadside tests the state part of the pattern is obtained by
latching the next state obtained under the first pattern.
Since scan is not used for the second pattern, broadside
tests are not affected by the use of multiple scan chains.
We describe an enhancement of broadside tests that
allows us to take advantage of the existence of multiple
scan chains in Section 2. Under the proposed enhancement, the first flip-flop of every scan chain receives its
value from the corresponding scan chain input under the
first and second patterns of an otherwise broadside test.
The resulting configuration can be viewed as a hybrid
skewed-load and broadside configuration similar to [10].
However, the skewed-load flip-flops under the proposed
enhancement are always the first flip-flops of the scan
chains. This allows us to take advantage of the existence
of multiple scan chains. The issue of multiple scan chains
and its effect on fault coverage was not considered in earlier works on DFT for transition faults, including [10].
We refer to the resulting configuration as an input-shift
broadside configuration.
In Section 3 we describe an experiment to study the
effects of multiple scan chains on the fault coverage of
transition faults with the input-shift broadside
configuration. Noting that the number of scan chains may
be limited by ATE constraints or a decompressor size, we
consider several different numbers of scan chains for
every circuit.
In Section 4 we describe a procedure that selects a
scan configuration so as to improve the fault coverage
achieved under the input-shift broadside configuration.
The procedure makes small modifications to the ordering
of the flip-flops in the scan chains in order to use more
effective flip-flops as first flip-flops of the scan chains, and
thus improve the fault coverage. It is important to note
that only the first flip-flops of the scan chains affect the
transition fault coverage obtained by input-shift broadside
tests, while the order of the other flip-flops in the scan
chains can be determined based on layout considerations
and does not affect the fault coverage. Therefore, the
effect of reordering on routing overhead, if any, is

expected to be negligible.

2. The input-shift broadside configuration

Under skewed-load tests, the first flip-flop of a scan
chain receives its value from the corresponding scan chain
input during the first as well as the second pattern of a
two-pattern test. Consequently, the first flip-flop of a scan
chain can be assigned an arbitrary value under both patterns. This observation was used in [12] to demonstrate
that the fault coverage of skewed-load tests increases with
the number of scan chains.
To obtain an increase in fault coverage with the
number of scan chains for broadside tests, we propose in
this section a scan configuration in which the first flip-flop
of every scan chain operates in skewed-load mode, and all
the other flip-flops operate in broadside mode. We refer to
this configuration as the input-shift broadside
configuration. To describe this configuration in more
detail, we use the following notation.
For a circuit with k flip-flops, we number the flipflops 0,1, . . . ,k 1. The present-state variable of flip-flop
i is denoted by yi , the next-state variable of flip-flop i in
the non-scan circuit is denoted by Yi , and the next-state
variable of flip-flop i in the scan circuit is denoted by Yi .
Yi is an output of the combinational logic of the circuit,
and Yi is connected to the data input of the scan flip-flop.
Between them there is a multiplexer that helps select
between scan mode and functional mode. We express Yi
as a function of Yi after introducing additional notation.
For n scan chains, the scan chain inputs are denoted
by SI 0,SI 1, . . . ,SIn 1. The index of the first flip-flop of
scan chain j is denoted by f irst (j ). We denote the set of
first flip-flops by FIRST . We have
FIRST = {f irst (j ):0j <n }.
In standard scan design, there is a single scan control input, denoted by SC . The next state function of flipflop i , where i
/ FIRST , is
Yi = SC .Yi +SC .yi 1.
The next state function of flip-flop i , where i = f irst (j ), is
Yi = SC .Yi +SC .SI j .
Under the input-shift broadside configuration, we
use two scan control inputs, denoted by SCB and SCI .
SCB is the scan control input for flip-flops that operate in
broadside mode during test application, i.e., the flip-flops
not included in FIRST . SCI is the scan control input for
flip-flops that operate in skewed-load mode during test
application, i.e., the flip-flops included in FIRST . If
i
/ FIRST , the next state function of flip-flop i is
Yi = SCB .Yi +SCB .yi 1.

474
480

If i = f irst (j ), the next state function of flip-flop i is

Yi = SCI .Yi +SCI .SI j .
The use of SCB and SCI allows four modes of
operation shown in Table 1. When SCB = SCI = 0, we
have Yi = Yi for all the flip-flops, and the circuit operates
in functional mode. When SCB = SCI = 1, we have
Yi = SI j for i FIRST and Yi = yi 1 for i
/ FIRST , and
the circuit operates in scan mode. When SCB = 0 and
SCI = 1, we have Yi = SI j for i FIRST and Yi = Yi for
i
/ FIRST . This mode is used for generating the second
pattern of a test during test application. It ensures that the
first flip-flops of the scan chains (the skewed-load flipflops) capture their values from the corresponding scan
chain inputs, while the other flip-flops (the broadside flipflops) capture the circuit state. The mode where SCB = 1
and SCI = 0 is not used in this work.
Table 1: Modes of operation

the same vectors V 1, S 1 and V 2 when they are applied as

input-shift broadside tests. We separate every state Si ,
i = 1,2, into two subvectors corresponding to the two scan
chains. In the case of input-shift broadside tests, the
values of flip-flops 0 and 7 can be determined arbitrarily
under S 2. Thus, they can be different from their values
under S 2 of the broadside test. These values are shown in
bold in Table 2. It can be seen that flip-flop 0 assumes a
different value under S 2 in the first input-shift broadside
test than in the first broadside test; both flip-flop 0 and
flip-flop 7 assume different values under S 2 in the second
input-shift broadside test than in the second broadside test;
and so on.
Table 2: Example input-shift broadside tests



broadside
input-shift broadside


Si
Si
i  Vi
chain 0
chain 1  Vi
chain 0
chain 1
























































1  001
0100110
0111110  001
0100110
0111110
2  111
1100110
0011000  111
0100110 0011000






















































1  011
0101110
1101001  011
0101110
1101001
 011
2





















































1101010
0011010  011
0101010 1011010
1  111
1101101
1100010  111
1101101
1100010
2  000
0000001
1100000  000
1000001 0100000
























































1  101
0101111
1111101  101
0101111
1111101
2  110
0000000
0011000  110
1000000 0011000






















































1  110
0100101
1110100  110
0100101
1110100
2  110
0000000
1100000  110
1000000 1100000






















































1  010
1110110
0100011  010
1110110
0100011
 001
2





















































0001010
0000010  001
0001010 0000010


1  000
0011110
0101000  000
0011110
0101000
2  011
1011110
0011000  011
0011110 1011000






















































1  000
1011101
0110111  000
1011101
0110111
2  101
0111001
0110111  101
0111001 1110111






















































1  011
1011111
0111101  011
1011111
0111101
2  100
0111010
0000010  100
1111010 0000010
























































1  101
0010100
1101010  101
0010100
1101010
2  010
0000000
1101000  010
1000000 1101000

SC
SCI  mode































B

0
0  functional
1
1  scan shift
0
1  input-shift broadside
1
0  unused
A broadside test consists of a primary input vector
V 1 and a present state S 1 that constitute the first pattern of
the test, and a primary input vector V 2 and a present state
S 2 that constitute the second pattern of the test. For a
broadside test, S 2 is the next state obtained under V 1 and
S 1. To apply a two-pattern test <S 1V 1,S 2V 2> under the
input-shift broadside configuration, the state S 1 of the first
pattern is scanned in while setting SCB = SCI = 1. The
first primary input vector V 1 is applied in state S 1 while
setting SCB = 0 and SCI = 1. This causes the broadside
flip-flops to latch their part of S 2, while the skewed-load
flip-flops receive their values from the corresponding scan
chain inputs. The primary input vector V 2 is applied next
while setting SCB = 0 and SCI = 0. This causes all the
flip-flops to latch the final state of the test, which is then
scanned out by setting SCB = SCI = 1. Since the SCI signal drives only the first flip-flops of the scan chains, it can
be more easily designed to be fast changing.
To demonstrate the operation of a circuit under
input-shift broadside tests, we consider ISCAS-89 benchmark circuit s 298 that has three primary inputs, and 14
flip-flops. For this example, the flip-flops are divided into
two scan chains. The first flip-flops of the scan chains are
f irst (0) = 0 and f irst (1) = 7. In Table 2 under column
broadside we show several broadside tests for the circuit.
Under column input-shift broadside we show tests with

The flexibility in determining the value of the first

flip-flop in every scan chain under S 2 is expected to lead
to an improvement in fault coverage as demonstrated in
the following section.

3. Effects of the input-shift broadside

configuration on the transition fault coverage
To measure the effects of using input-shift broadside tests on the transition fault coverage, we perform the
experiment described in this section.
We use a set B of 100,000 random two-pattern
broadside tests. Every test consists of two patterns
<V 1S 1,V 2S 2> as demonstrated in Table 2. For a given
number of scan chains n and a given set FIRST of first
flip-flops of the n scan chains, we find an input-shift
broadside test set BIS as follows. Initially, BIS = B . For

475
481

every test in BIS , we modify randomly the values of the

flip-flops included in FIRST under state S 2. Table 2
demonstrates how the test set B shown on the left in Table
2 may be modified when FIRST = {0,7} into the test set
BIS shown on the right in Table 2.
For a given value of n , we partition the flip-flops of
a circuit into scan chains of approximately equal lengths.
We do not modify the scan chain order relative to the
order of the flip-flops in the given circuit description. For
a circuit with k flip-flops we use n = 0, 1, 2, 4, . . . , 32.
We use n = 0 to indicate that standard broadside tests are
applied. In this case, the number of scan chains does not
affect the fault coverage. For a circuit with k < 32 flipflops, the largest number of scan chains we consider is the
largest power of two that is smaller than 32. In addition
we consider n = k . With n = k scan chains, every twopattern test can be applied to the circuit, similar to
enhanced scan. To ensure that the tests applied with n
scan chains are also applicable with 2n scan chains, for
n 1, we partition every scan chain of length L into two
scan chains of lengths L /2 and L /2 in order to obtain
2n scan chains from n scan chains.
The results of this experiment for benchmark circuits are shown in Table 3. Under column FF we show
the number of flip-flops. Under column fault coverage
subcolumn n =0 we show the transition fault coverage
obtained by broadside tests. Under column fault coverage
subcolumn n =n 0, where n 0 = 1,2,4, . . . ,32, we show the
transition fault coverage obtained by input-shift broadside
tests with n scan chains. If k < 32, the last column where
a fault coverage is entered corresponds to n = k .
From Table 3 it can be seen that the fault coverage
increases with n . The increase is significant for smaller
circuits even with small values of n . For larger circuits,
n = 1 may not increase the fault coverage significantly.
However, as n is increased further, the fault coverage
increases as well. This is expected since a larger value of
n implies more flexibility in determining the present state
under the second pattern of a test. Further improvements
in fault coverage are expected if deterministic test sets are
used.

4. Selecting
configuration

an

input-shift

chains (the flip-flops included in the set FIRST ) so as to

increase the transition fault coverage. The starting point
for the modification process is the equal length scan
chains used in Section 3. The transition fault coverage is
measured by applying the same random test sets B and
BIS used in Section 3. BIS is recomputed for every set of
first flip-flops FIRST as described in Section 3.
A modification made by the proposed procedure
swaps the first flip-flop of a scan chain with a flip-flop
placed later in the same scan chain. Assuming that the
flip-flops are indexed consecutively, if flip-flop i is the
first flip-flop of scan chain j , we attempt to swap flip-flop
i with each one of the flip-flops i +1,i +2, . . . ,i +1, for a
constant . By limiting , we limit the distance, and thus
the overhead, of swapping the flip-flops.
For every flip-flop i +, where 0 < , swapping
of flip-flops i and i + implies that flip-flop i is removed
from the set FIRST , and flip-flop i + is inserted into
FIRST in its place. For every , we compute the fault
coverage obtained by the test set BIS under the set
FIRST {i }+{i +}. We denote the resulting fault coverage by f c (i ,i +). We select the value of for which the
fault coverage is the highest, and we replace flip-flop i
with flip-flop i + as the first flip-flop of the scan chain.
We set FIRST = FIRST {i }+{i +}, and we modify
f irst (j ) = i into f irst (j ) = i +.
We consider every flip-flop i FIRST in the same
manner. For illustration, we consider ISCAS-89 benchmark circuit s 298 with n = 2 scan chains. The circuit has
k = 14 flip-flops, and we initially have FIRST = {0,7}.
With = 4, we consider the swapping of flip-flop i = 0
with every one of the flip-flops 1, 2 and 3. We obtain
f c (0,0) = 87.92% when flip-flop 0 is kept as the first flipflop of scan chain 0, f c (0,1) = 89.93% when flip-flop 0 is
replaced with flip-flop 1 as the first flip-flop of scan chain
0, f c (0,2) = 91.44% when flip-flop 0 is replaced with
flip-flop 2 as the first flip-flop of scan chain 0, and
f c (0,3) = 88.93% when flip-flop 0 is replaced with flipflop 3 as the first flip-flop of scan chain 0. We select to
swap flip-flop 0 with flip-flop 2 to obtain FIRST = {2,7},
and f irst (0) = 2.
Next, we consider the swapping of flip-flop i = 7
with every one of the flip-flops 8, 9 and 10. We obtain
f c (7,7) = 91.44% when flip-flop 7 is kept as the first flipflop of scan chain 1, f c (7,8) = 90.94% when flip-flop 7 is
replaced with flip-flop 8 as the first flip-flop of scan chain
1, f c (7,9) = 90.94% when flip-flop 7 is replaced with
flip-flop 9 as the first flip-flop of scan chain 1, and
f c (7,10) = 91.11% when flip-flop 7 is replaced with flip-

broadside

A scan configuration is typically selected based on

layout considerations. Small changes in the ordering of
the flip-flops in the scan chains can typically be accommodated without significant routing overhead. In this section
we modify the selection of the first flip-flops of the scan

476
482

flop 10 as the first flip-flop of scan chain 1. We select to

keep flip-flop 7 to obtain the final set FIRST = {2,7}.
We applied this process to benchmark circuits using
= min{L ,5}, where L is the highest scan chain length.
The results are shown in Table 4. We report the results
for n = 1, 2 and 4. After the circuit name we show the
number of flip-flops, and the fault coverage obtained with
n = 0. For every value of n 1, we show the fault coverage before modification under column init , and the fault
coverage after modification under column mod .
From Table 4 it can be seen that by swapping the
first flip-flop of a scan chain with a flip-flop that is relatively close to it, it is possible to improve the fault coverage of transition faults noticeably. It is interesting to note
that in some cases, n modified scan chains with first flipflops selected by the proposed procedure result in a higher
fault coverage than 2n scan chains with the first flip-flops
obtained before modification.

References

5. Concluding remarks

[8]

[1]

[2]

[3]

[4]
[5]

[6]

[7]

We described an enhanced configuration for broadside testing referred to as input-shift broadside. Under this
configuration, increasing the number of scan chains helps
increase the transition fault coverage. This property exists
for skewed-load tests, but not for standard broadside tests.
In the input-shift broadside configuration, the first flip-flop
of a scan chain operates in skewed-load mode while the
other flip-flops operate in broadside mode. This provides
flexibility in determining the value of the first flip-flop of
every scan chain under the second pattern of an input-shift
broadside test, thus increasing the transition fault coverage. We also described a procedure that makes small
modifications to a given scan chain configuration in order
to improve the transition fault coverage. The procedure
may replace the first flip-flop of a scan chain with another
flip-flop that follows it at a small distance in the same scan
chain if controlling this flip-flop from the scan chain input
is more important for the detection of transition faults.

[9]

[10]

[11]

[12]

477
483

S. Dasgupta, R. G. Walther, T. W. Williams and E. B.

Eichelberger, "An Enhancement to LSSD and Some
Applications of LSSD in Reliability, Availability and Serviceability", in Proc. 11th Fault-Tolerant Computing
Symp., 1981, pp. 880-885.
J. Savir and S. Patil, "Scan-Based Transition Test", IEEE
Trans. on Computer-Aided Design, Aug. 1993, pp. 12321241.
J. Savir and S. Patil, "Broad-Side Delay Test", IEEE
Trans. on Computer-Aided Design, Aug. 1994, pp. 10571064.
J. Rearick, "Too Much Delay Fault Coverage is a Bad
Thing", in Proc. Intl. Test Conf., Oct. 2001, pp. 624-633.
J. Saxena, K. M. Butler, V. B. Jayaram, S. Kundu, N. V.
Arvind, P. Sreeprakash and M. Hachinger, "A Case Study
of IR-Drop in Structured At-Speed Testing", in Proc. Intl.
Test Conf., 2003, pp. 1098-1104.
W. Mao and M. D. Ciletti, "Arrangement of Latches in
Scan-Path Design to Improve Delay Fault Coverage", in
Proc. 1990 Intl. Test Conf., Sept. 1990, pp. 387-393.
J. Savir and R. Berry, "At-Speed Test is Not Necessarily
an AC Test", in Proc. 1991 Intl. Test Conf., Oct. 1991,
pp. 722-728.
N. A. Touba and E. J. McCluskey, "Applying TwoPattern Tests Using Scan-Mapping", in Proc. VLSI Test
Symp., April 1996, pp. 393-397.
I. Pomeranz and S. M. Reddy, "On Achieving Complete
Coverage of Delay Faults in Full Scan Circuits using
Locally Available Lines", in Proc. 1999 Intl. Test Conf.,
Oct. 1999, pp. 923-931.
S. Wang, X. Liu and S. T. Chakradhar, "Hybrid Delay
Scan: A Low Hardware Overhead Scan Based Delay Test
Technique for High Fault Coverage and Compact Test
Sets", in Proc. Design Autom. and Test in Europe Conf.,
2004, pp. 1296-1301.
N. Devtaprasanna, A. Gunda, P. Krishnamurthy, S. M.
Reddy and I. Pomeranz, "Methods for Improving Transition Delay Fault Test Coverage Using Broadside Tests",
in Proc. Intl. Test Conf., Nov. 2005, pp. 256-265.
I. Pomeranz and S. M. Reddy, "On the Coverage of Delay
Faults in Scan Designs with Multiple Scan Chains", in
Proc. 2002 Intl. Conf. on Computer Design, Sept. 2002,
pp. 206-209.

Table 3: Fault coverage for equal-length scan chains



fault coverage
circuit  FF  n=0
n=1
n=2
n=4
n=8
n=16
n=32







































































s298
14  81.71
87.25
87.92
94.30
99.66
100.00

s344
15  94.48
97.67
97.67
97.97
100.00
100.00


s382
21  78.40
78.53
83.12
85.47
91.79
99.08
100.00

s420
16
73.21
74.29
76.79
80.48
83.81
96.79


s526
21  64.64
69.77
75.29
77.38
90.49
99.43
99.90

s641
19  94.69
94.92
95.23
97.27
97.73
98.20
98.44


s953
29  94.65
96.90
96.90
96.90
97.90
99.63
100.00
s1196 
18  99.54
99.54
99.54
99.58
99.62
100.00
100.00

b03
30  94.01
94.14
94.27
95.05
95.44
97.79
100.00

b09
28  85.71
85.98
85.44
88.27
90.30
92.18
100.00

b10
17  82.74
83.19
84.07
86.17
96.90
100.00
100.00


b11
30
87.33
87.72
88.20
89.13
89.37
94.22
99.17








































































s1423 
74  88.12
88.26
88.51
89.25
90.65
92.23
95.12
s5378  179  90.18
90.18
90.35
91.53
91.77
91.72
92.52
s9234  228  73.51
73.71
73.86
74.01
74.22
74.30
75.74
s13207  669  77.43
77.79
77.79
77.81
77.93
78.14
78.45
s15850  597  67.14
68.24
68.63
68.66
68.89
69.12
74.03
s38417  1636  94.09
94.09
94.08
94.10
94.11
94.07
94.10
s38584  1452  86.06
86.33
86.35
86.36
86.37
86.44
86.47


b04
66  90.62
90.91
91.07
91.48
91.69
93.17
98.11

b14
 247  72.96
72.98
72.95
73.06
73.09
73.30
73.50

Table 4: Fault coverage for scan chains with modified first flip-flops



fault coverage





n=1
n=2
n=4
circuit  FF  n=0  init
mod  init
mod  init
mod




































































s298
14  81.71  87.25
90.94  87.92
91.44  94.30
95.30


s344
15  94.48  97.67
97.97  97.67
98.11  97.97
98.26




s382
21  78.40  78.53
78.53  83.12
83.38  85.47
89.01

s420
16  73.21  74.29
74.88  76.79
77.62  80.48
80.48

s526
21  64.64  69.77
72.43  75.29
77.00  77.38
85.46


s641
19  94.69  94.92
96.56  95.23
97.03  97.27
97.34

s953
29  94.65  96.90
97.17  96.90
97.17  96.90
97.17
s1196 
18  99.54  99.54
99.58  99.54
99.58  99.58
99.92

b03
30  94.01  94.14
95.70  94.27
95.83  95.05
96.22

b09
28  85.71  85.98
86.66  85.44
87.06  88.27
89.22




 86.17
b10
17
82.74
83.19
89.27
84.07
96.46
98.56





b11
30  87.33  87.72
87.72  88.20
91.80  89.13
96.89




































































s1423 
74  88.12  88.26
88.40  88.51
88.76  89.25
89.53
s5378  179  90.18  90.18
90.18  90.35
90.44  91.53
91.75
s9234  228  73.51  73.71
73.90  73.86
74.44  74.01
74.41
s13207  669  77.43  77.79
77.79  77.79
77.79  77.81
77.81
s15850  597  67.14  68.24
71.61  68.63
72.59  68.66
72.68
s38417  1636  94.09  94.09
94.09  94.08
94.12  94.10
94.13


s38584  1452  86.06  86.33
86.33  86.35
86.35  86.36
86.36



b04
66  90.62  90.91
90.95  91.07
98.35  91.48
98.68

b14
 247  72.96  72.98
73.69  72.95
73.73  73.06
73.83

478
484