Files PDF Mock Test 2 - Answers

ARM Accredited Engineer
Mock Test 2 - Answers

www.arm.com/aae
Instructions
This mock test is designed to give prospective test-takers an opportunity to sample questions of a similar
scope and level of difficulty to those included in the live AAE certification test.
The test consists of 10 multiple choice questions and an accompanying document provides answers to
these questions along with a rationale for each question and answer.
We suggest that you allow yourself 10 minutes to complete this test, without the use of any reference
materials or learning materials.
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Question 1
Thumb-2 technology is implemented in which of the following?
A)
B)
C)
D)
All ARM processors

All ARMv7 processors
ARMv7-A processors only
ARMv7-A and ARMv7-R but not ARMv7-M
Answer B is correct. ARM1156T2 was the first processor to be extended with Thumb-2 technology.
It is supported by all ARMv7 processors. AArch32 supports Thumb-2 (T32) as well.
Question 2
Which one of the following is a valid difference between bare metal and OS applications?
A) OS applications never make use of shared resources; bare metal applications always do.
B) OS applications have direct control over their memory configuration; bare metal
applications never do.
C) OS applications are scheduled by the OS; bare metal applications can run without a
scheduler being present.
D) Bare metal applications always have to call device drivers to access low level platform
hardware; OS applications do not.
Answer C is correct. OS manages the hardware resources and schedules the applications to share
these resources. A bare-metal application does not need a scheduler as it is the only application
which occupies all the resources.

Version 1.0
Question 3
Which assembly instruction would you use to load 4 words starting from the memory location
0x80000000 into the registers r0-r3?
(Assume r9 contains the base address 0x80000000)
A)
B)
C)
D)
LDMDB r9, {r0-r3}

LDMIA r9, {r0-r3}
LDMIB r9, {r0-r3}
LDMDA r9, {r0-r3}
Answer B is correct. ARM Architecture Reference Manual A5.4.2 Load and Store Multiple
Increment after, A5.4.6 Load and Store Multiple addressing modes (alternative names):
Increment address After each transfer. Start address = 0x80000000
Decrement address Before each transfer. Start address = 0x7FFFFFF0
h transfer. Start address = 0x80000004
. Start address = 0x7FFFFFF4
Question 4
A cache that supports dirty bits to manage the most recently written value to a given memory
location in the memory hierarchy is referred to as a:
A)
B)
C)
D)
write-back cache.
write-through cache.
set-associative cache.
fully-associative cache.
Answer A is correct. ARM Architecture Reference Manual B6.3.2 Write-through or write-back

caches: In a write-back cache, the cache line is marked as dirty. This means that it contains data
values that are more up-to-date than those in main memory. Whenever a dirty cache line is
selected to be re-allocated to another address, the data currently in the cache line is written back
to main memory.

Version 1.0
Question 5
The ARM processor registers R13, R14, and R15 are architecturally used for special purposes.
Which is the correct respective sequence of special purpose registers?
A)
B)
C)
D)
PC, LR, SP
LR, PC, SP
SP, LR, PC
LR, SP, PC
Answer C is correct. ARM Architecture Reference Manual section A1.1.1 ARM registers.
Question 6
When building code for both ARM and Thumb states, which tool decides for each function call
whether to use a BL or BLX instruction?
A)
B)
C)
D)
The linker
The archiver
The compiler
The assembler
Answer A is correct. When the linker resolves the symbol definitions, it replaces the B or BL
instructions with BX or BLX instructions if there is a need to switch the state between ARM and
Thumb.

Version 1.0
Question 7
Optimizing for space will:
A)
B)
C)
D)
produce an image which is decompressed at run-time.

cause the compiler to unroll loops where possible.
result in more functions being inlined by the compiler.
produce smaller code, even if this results in slower execution.
Answer D is correct. The compiler option -Ospace instructs the compiler to perform optimizations
to reduce image size at the expense of a possible increase in execution time.
-Otime operates in the opposite way. It optimizes for performance, but with a potential increase in
image size.
Question 8
When building code for a processor without floating point hardware, how would the compiler deal
with floating point calculations in the source code?
A) The compiler will produce code that results in calculations with less accuracy
B) The compiler will produce an error and not compile
C) The compiler will use libraries to perform the floating point operations with integer
instructions
D) The compiler will warn the programmer that the code needs to be rewritten using fixedpoint arithmetic
Answer C is correct. ARM Compiler User Guide: Compiler supports floating-point arithmetic both
in hardware and in software. A floating-point library is required to support the software floatingpoint operations using no additional hardware.

Version 1.0
Question 9
What is the MINIMUM number of priority levels that a Generic Interrupt Controller (GIC) supports?
A)
B)
C)
D)
8
16
32
64
Answer B is correct. ARM Generic Interrupt Controller Architecture Specification section 3.3
Interrupt prioritization: A GIC supports a minimum of 16 and a maximum of 256 priority levels.
Question 10
What is the WFI instruction used for?
A)
B)
C)
D)
To power down the interrupt controller when it is not required

To signal an interrupt event to another processor in a multi-core system
To enable interrupts temporarily while in the middle of an exception handler
To place the processor in a low power mode while waiting for an interrupt
Answer D is correct. WFI stands for Wait for Interrupt. It is intended for power saving only. It
suspends execution until one of the following events occurs: an exception, an interrupt becomes
pending, a Debug Entry request.

Version 1.0

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ARM Accredited Engineer

Mock Test 2 - Answers

Non-Confidential Proprietary Notice

ARM Accredited Engineer

Mock Test 2 - Answers

All ARM processors

Copyright 2013 ARM Limited

ARM Accredited Engineer

Mock Test 2 - Answers

LDMDB r9, {r0-r3}

Answer A is correct. ARM Architecture Reference Manual B6.3.2 Write-through or write-back

Copyright 2013 ARM Limited

ARM Accredited Engineer

Mock Test 2 - Answers

Copyright 2013 ARM Limited

ARM Accredited Engineer

Mock Test 2 - Answers

produce an image which is decompressed at run-time.

Copyright 2013 ARM Limited

ARM Accredited Engineer

Mock Test 2 - Answers

To power down the interrupt controller when it is not required

Copyright 2013 ARM Limited

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