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Name-Karanbeer Singh Roll No - B37 Reg No-11210257 Section - E1201

The document describes implementing half adder, full adder, half subtractor, and full subtractor circuits in Verilog. It includes the code for each circuit as well as test benches to simulate and test the circuits. The aim is to learn how to implement various logic operations and wire functions in Verilog.

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Kulbir Godara
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51 views9 pages

Name-Karanbeer Singh Roll No - B37 Reg No-11210257 Section - E1201

The document describes implementing half adder, full adder, half subtractor, and full subtractor circuits in Verilog. It includes the code for each circuit as well as test benches to simulate and test the circuits. The aim is to learn how to implement various logic operations and wire functions in Verilog.

Uploaded by

Kulbir Godara
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Name- Karanbeer Singh

Roll No- B37


Reg No-11210257
Section- E1201

Aim: Implement Half Adder, Full Adder, Half Substractor and Full Subtractor in
Verilog.

Learning Objectives:
Learn to implement various operations.
Learn to implement wire function.

Program codes:
Half Adder
module hhimanshu_A22(s, c, a,
b); output s; output c; input
a;
input b; assign
s=a^b; assign
c=a&b;
endmodule

TEST BENCH
module ch_v;
// Inputs
reg a;
reg b;
// Outputs
wire s;
wire c;
// Instantiate the Unit Under Test (UUT)
hhimanshu_A22 uut (
.s(s),
.c(c),
.a(a),
.b(b)

);
initial begin // Initialize
Inputs a = 0; b =
0;
// Wait 100 ns for global reset to finish
#4; a
= 0; b
= 1;
#4;
a = 1;
b = 0;
#4;
a = 1;
b = 1;
end
endmodule

Full Adder
module FA(s, c, x, y,
z); output s;
output c; input x;
input y; input z;
wire p,q,r; xor(s,x,y,z);
and(p,x,y); and(q,y,z);
and(r,x,z); or(c,p,q,r);

endmodule
TEST BENCH
module v_v;
// Inputs
reg x;
reg y;
reg z;
// Outputs
wire s;
wire c;
// Instantiate the Unit Under Test (UUT)
FA uut (
.s(s),
.c(c),
.x(x),
.y(y),
.z(z)
);
initial begin // Initialize
Inputs x = 0; y =
0; z = 0;
// Wait 100 ns for global reset to finish
#2; x
= 0; y
= 0; z
= 1;
#2;

x = 0; y = 1; z =
0; #2;
x = 0; y = 1; z =
1; #2;
x = 1; y = 0; z =
0; #2;
x = 1; y = 0; z =
1; #2;
x = 1; y = 1; z =
0; #2;
x = 1; y = 1; z =
1; end
endmodule

Half Subtractor

module HS(d, b, x,
y); output d;
output b; input x;
input y; wire p;
xor(d,x,y); not(p,y);
and(b,x,p);

endmodule
TEST BENCH
module k_v;
// Inputs
reg x;
reg y;
// Outputs
wire d;
wire b;
// Instantiate the Unit Under Test (UUT)
HS uut (
.d(d),
.b(b),
.x(x),
.y(y)
);
initial begin // Initialize
Inputs x = 0; y =
0;
// Wait 100 ns for global reset to finish
#3; x
= 0; y
= 1;
#3; x
= 1; y
= 0;
#3; x
= 1; y
= 1;
end
endmodule

Full Subtractor:
module FS(d, b, x, y, z);
output d; output b;
input x; input y; input
z; wire p,q,r,s; assign
d=((x^y)^z); assign s=~x;
assign p=s&y; assign
q=s&z; assign r=y&z;
assign b=((p|q)|r);

endmodule
TEST BENCH
module f_v;
// Inputs
reg x;
reg y;
reg z;

// Outputs
wire d;
wire b;
// Instantiate the Unit Under Test (UUT)
FS uut (
.d(d),
.b(b),
.x(x),
.y(y),
.z(z)
);
initial begin // Initialize
Inputs x = 0; y =
0; z = 0;
// Wait 100 ns for global reset to finish
#2; x
= 0; y
= 0; z
= 1;
#2; x
= 0; y
= 1; z
= 0;
#2; x
= 0; y
= 1; z
= 1;
#2; x
= 1; y
= 0; z
= 0;
#2; x
= 1; y
= 0; z
= 1;
#2; x
= 1; y
= 1; z
= 0;
#2; x
= 1; y
= 1; z
= 1;

end
endmodule

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