1

DIGITAL CIRCUITS LAB

Laboratory Manual

By
Dr. S. lakshminarayana
B.T.P.Madhav

K L UNIVERSITY
VADDESWARAM, GUNTUR DT

ACKNOWLEDGEMENTS

We take this opportunity to thank Our Head of the Department Dr.

Habibulla Khan, for his continuous encouragement and support during
this

manual

preparation.

Dr.S.Lakshminarayana,

We

Professor,

would
E.C.E

like

to

Department

thank
for

his

suggestions towards the adding of practical and application oriented

concepts. I thank Mr. M. Ravi Kumar and all other teaching and nonteaching faculty for their encouragement and help during the
preparation of this laboratory manual.

B.T.P.MADHAV

Preface
Digital circuits lab is an elementary course taught to electronics and
communication students at K L University. Basic concepts of digital logic design,
such as implementation of logic gates, using logic gates and universal gates the
design of different combinational and sequential circuits are taught in this lab. In
practical classes students are given hands on experience on what they have
studied in lecture classes.

Learning objectives for each experiment are given in the beginning of the
experiment in the manual. For each experiment a list of review questions are
included. Answering to these questions ensures learning of the process in terms
of its application. Students are expected to answer all the review questions and
to enter their observations in the manual itself. Students will be working with
each facility on rotation basics weekly twice. At the end of the semester,
students are expected to familiarize completely for using all the facilities in the
digital circuits lab.

Authors

PIN Configurations for Logic Gates

NAND GATE 7408

OR GATE 7432

NOT GATE - 7404

7400

NAND GATE 7400

NOR GATE 7402

EX-OR GATE 7486

Table of contents

Experiment Number
1

Name of the Experiment

REALIZATION
OF
GATES
UNIVERSAL GATES

USING

Page no.
7

COMBINATIONAL CIRCUITS

14

COMPARATOR

20

CODE CONVERTERS

22

MULTIPLEXER AND DEMULTIPLEXER

26

FLIP FLOPS USING GATES

30

RING AND JOHNSON COUNTERS

35

SYNCHRONOUS COUNTER

40

CONVERSION OF ONE FLIP-FLOP TO

ANOTHER TYPE

43

10

BCD-TO-SEVEN SEGMENT DECODER

DRIVER

48

11

CD 4033 DECADE COUNTER/SEVEN

SEGMENT DECODER
SEQUENCE GENERATOR
STUDY OF DECADE COUNTERS USING
7490
MODULO N COUNTERS USING 7490
SHIFT REGISTERS

51

12
13
14
15

53
57
61
65

7
EXPERIMENT NO 1

REALISATION OF LOGIC GATES USING UNIVERSAL GATES

LEARNING OBJECTIVE: Realization of gates using NAND Gate and NOR Gate
A. REALISATION USING NAND GATE:AIM: To realize AND, OR, NOT, NOR and EX-OR GATES using NAND Gate.

APPARATUS: IC 7400, Bread Board, Power supply, connecting wires.

THEORY: NAND, NOR gates are called Universal building blocks. NAND and NOR Gates perform
AND, OR, NOT, EX-OR Gates operations.

1.NOT from NAND: - If the two inputs of NAND Gate are connected together then it acts as NOT
Gate.
2.AND from NAND: - If the output of NAND Gate is given to the input of not gate using NAND gate,
AND Gate is obtained.
3.OR from NAND: - If the two NOT Gates using NAND Gates are given as the inputs to NAND
Gate, OR Gate is obtained.
4.NOR from NAND: - If the o/p of OR Gate using NAND Gate is given as the inputs to NAND Gate,
NOR Gate is obtained.
5.EX-OR from NAND: - If the o/p of one NAND Gate is connected to the one input of another two
NANDS and the outputs are connected to the inputs of fourth NAND gate, So EX-OR is obtained.

PROCEDURE:
1. Connections are made as per circuit diagram.
2. Use logic input switches for inputs A and B.
3. Use logic output indicator LED for monitoring the o/p logic.
4. Compare with standard truth table.
5. The o/p is noted for different inputs.

PRECAUTIONS:
1. Connect and check Vcc and Ground pins properly.
2. Verify the supply voltage properly (dont exceed +5V).
3. Place the connections without loose contacts.
4. Connections must be checked before giving the inputs.

CIRCUIT DIAGRAM:
NOT FROM NAND GATE:

TRUTH TABLE:
INPUT OUTPUT
A
Y= A
0
1
1
0

AND FROM NAND GATE:

TRUTH TABLE:
INPUT
A
B
0
0
0
1
1
0
1
1

OR FROM NAND GATE:

TRUTH TABLE:
INPUT
A
B
0
0
0
1
1
0
1
1

NOR FROM NAND GATE:

OUTPUT
Y=AB
0
0
0
1

OUTPUT
Y=A+B
0
1
1
1

TRUTH TABLE:

INPUT
A
B
0
0
0
1
1
0
1
1

EX-OR FROM NAND GATE:

OUTPUT
Y= A B
1
0
0
0

TRUTH TABLE:
INPUT
A
B
0
0
0
1
1
0
1
1

OUTPUT
Y= AB + A B
0
1
1
0

OBSERVATIONS:
NOT GATE:
INPUT OUTPUT
A
Y= A

AND GATE:
INPUT
A
B

OUTPUT
Y=AB

INPUT
A
B

OUTPUT
Y=A+B

OR GATE:

NOR GATE:

INPUT
A
B

OUTPUT
Y= A B

EX-OR GATE:
INPUT
A
B

OUTPUT
Y= AB + A B

10

B. REALISATION USING NOR GATE:-

AIM: To realize AND, OR, NOT, NOR, NAND Gates using NOR Gate.

APPARATUS: IC 7402, DIGITAL Logic Trainer, Connecting wires.

1.NOT from NOR: - If the two inputs of NOR Gate are connected together then it acts as NOT Gate.

2.OR from NOR: - If the output of NOR Gate is given to the input of NOT gate using NOR gate, OR
Gate is obtained.

3.AND from NAND: - If the two NOT Gates using NOR Gates outputs are given to the NOR Gate as
inputs, AND Gate is obtained.

4.NAND from NOR: - If the output of AND Gate using NOR Gates is given to the inputs to the NOR
Gate, NOR Gate is obtained.

5.EX-OR from NOR: - If the output of one NAND Gate is connected to the one input of another two
NANDS and the outputs are connected to the inputs of fourth NAND gate, So EX-OR is obtained.

PROCEDURE:

1. Connections are made as per circuit diagram.

2. Use logic input switches for inputs A and B.
3. Use logic output indicator LED for monitoring the output logic.
4. Compare with standard truth table.
5. The output is noted for different inputs.

PRECAUTIONS:

1. Connect and check Vcc and Ground pins properly.

2. Verify the supply voltage properly (dont exceed +5V).
3. Place the connections without loose contacts.
4. Connections must be checked before giving the inputs.

11

CIRCUIT DIAGRAMS:
NOT FROM NOR GATE:

TRUTH TABLE:
INPUT OUTPUT
A
Y= A
0
1
1
0

AND FROM NOR GATE:

TRUTH TABLE:
INPUT
A
B
0
0
0
1
1
0
1
1

OR FROM NOR GATE:

TRUTH TABLE:
INPUT
A
B
0
0
0
1
1
0
1
1

NAND FROM NOR GATE:

OUTPUT
Y=AB
0
0
0
1

OUTPUT
Y=A+B
0
1
1
1
TRUTH TABLE:

INPUT
A
B
0
0
0
1
1
0
1
1

EX-OR FROM NOR GATE:

OUTPUT
Y= AB
1
1
1
0

TRUTH TABLE:
INPUT
A
B
0
0
0
1
1
0
1
1

OUTPUT
Y= AB + A B
0
1
1
0

12

OBSERVATIONS:
NOT GATE:
INPUT OUTPUT
A
Y= A

AND GATE:
INPUT
A
B

OUTPUT
Y=AB

INPUT
A
B

OUTPUT
Y=A+B

OR GATE:

NAND GATE:

INPUT
A
B

OUTPUT
Y= AB

EX-OR GATE:
INPUT
A
B

OUTPUT
Y= AB + A B

13

Review Questions
1)
2)
3)
4)
5)

Why NAND and NOR gates are called universal gates?

How many minimum number of NAND gates are required to realize XOR gate?
What is a gate propagation delay?
What is noise margin? Draw a visual representation of noise margin idea.
Implement F=w(x+y+z) using AND OR gates and universal gates.

RESULTS AND DISCUSSION

Signature of student

Signature of Instructor

14
EXPERMENT NO: 2

COMBINATIONAL CIRCUITS
LEARNING OBJECTIVES:
To design the logic circuits which perform binary addition and subtraction
AIM:
To design the following combinational circuits and verify their truth tables
a) Half adder and Half subtractor
b) Full adder and Full subtractor
APPARATUS:
1) Fixed 5v DC power supply
2) Bread board
3) IC7400: quad 2-input NAND gates
4) IC 7486: quad 2 input XOR gates

..1no
. ..1no.
..2no.
..1no.

PROCEDURE:

HALF ADDER

1) Connect the half adder circuit as shown in fig

2) Take 7486 and 7408 ICs
3 ) Remember to connect 5v to Vcc pin and 0v to GND pin.
4) Apply 5v for logic 1 level and 0v for logic 0 level at the input terminals of the gate.
5) The Two Inputs are A and B
6) Apply inputs to the circuits as per truth table
7) Note down the sum values in the table
8) Note down carry values in the table
9) Verify the observation table matches with the truth table.

15

HALF ADDER CIRCUIT

HALF SUBTRACTOR

A
0
0
1
1

B
0
1
0
1

Difference
0
1
1
0

Barrow
0
1
0
0

16

FULL ADDER CIRCUIT

FULL SUBTRACTOR

17

18

19

Review Questions
1)
2)
3)
4)
5)

What is meant by fan out of a logic gate?

What is the difference between carry and borrow?
Design a full adder circuit using two half adders.
Design a full subtractor circuit using two half subtractors.
How is the propagation delay of a combinational circuit determined?

Results and Discussion

Signature of student:

Signature of instructor

20
EXPERMENT NO: 3

COMPARATOR
LEARNING OBJECTIVES:
To design the comparator, which compares the magnitude of the numbers
AIM:
To verify the operation of 2-bit word comparator.
APPARATUS:
1) 5V DC power supply
2) IC 7486: quad 2-input xor gate
3) IC 7404: inverter
4) IC 7408: quad 2-input AND gate
5) IC 7406: Nor Gate
5) Bread board

.. .1no
1no
1no
1no
..1no
1no

PROCEDURE:
1) Connect the word comparator using XOR gates, NOT, AND, X-NOR gates as shown in fig
2) Apply 5v for logic 1 level and 0v for logic 0 level.
3) Apply the inputs for the 2 words as per the truth table, compare the 2 words.
PRECAUTIONS:
1) Correct ICS should be properly placed on IC base using pin diagrams
2) The open circuit voltage of the power supply should be exactly 5v

21

RESULT:
The word comparator for 2 bits is studied
Review questions
1) Design one bit comparator?
2) What is equality gate?
3) What is the IC number for 4-bit comparator?
4) Give applications of comparator.

Results and Discussion

Signature of student:

Signature of instructor

22
EXPERMENT NO:4

CODE CONVERTERS

LEARNING OBJECTIVES:
To design the code converters which convert from one code to other code.
AIM:
Verify the operation of 4-bit binary to gray code and 4-bit gray to binary converter
APPARATUS:
1. 5V DC power supply
2. Bread board
3. IC 7486: Quad 2-input XOR Gates

. 1No
. 1No
. 1No

PROCEDURE:

BINARY TO GRAY CONVERTER

1.
2.
3.
4.

Connect the binary to gray converter circuit as shown in figure using IC 7486
Remember to connect 5V to 14 pin and 0V to 7 pin.
Apply 5V for logic 1 level and 0V for logic 0 level at the binary inputs.
Repeat the steps for all 16 binary input combinations.

GRAY TO BINARY CONVERTER

1.
2.
3.
4.

Connect the gray to binary converter circuit as shown in figure using IC 7486
Remember to connect 5V to VDD pin and 0V to GND pin.
Apply 5V for logic 1 level and 0V for logic 0 level at the binary inputs.
Repeat the steps for all 16 binary input combinations.

23

24

25

PRECAUTIONS
1) Correct IC should be properly placed on the IC base using pin diagram.
2) The open circuit voltage of the power supply must be stable and near 5.0V.
3) In case the logic gate outputs do not make sense, check your circuit thoroughly. If the problem
is still not resolved, get IC tested by the technician.
RESULT
Code converter operation has been verified.

Review Questions

1) What is advantage of gray code?

2) What is meant by distance in cyclic codes?
3) Write Boolean function for binary outputs in terms of gray code inputs in gray to binary
converter.
4) what is meant by Excess-3 code.
5) Write names of any two other types of codes.
Results and Discussion

Signature of student:

Signature of instructor

26
EXPERMENT NO: 5

MULTIPLEXER AND DEMULTIPLEXER

LEARNING OBJECTIVES:
To design the Multiplexer and De-multiplexer.
AIM:
Verify the operation of a 4:1 multiplexer.
Verify the operation of a 1:4 de-multiplexer.
APPARATUS:
1) Fixed 5v DC power supply
2) Bread board
3) IC7411 Tripple 3-input AND gates
4) IC 7432:quad 2 input OR gates
5) IC 7404 Hex inverters

..1no
.1no.
..2no.
..1no.
..1no.

PROCEDURE:
MULTIPLEXER
1) Connect the multiplexer circuit as shown in fig,use IC 7404, 7411, 7432 to connect the circuit
(the IC number is printed on top of each IC in silver color)
2) Remember to connect 5v to vdd pin and 0v to GND pin.
3) Apply 5v for logic 1 level and 0v for logic 0 level at the input terminals of the gate.
4) Apply inputs to the circuits as per truth table
5) Verify the observation table matches with the truth table.

DEMULTIPLEXER
1) Connect the multiplexer circuit as shown in fig, use IC 7404, 7411, 7432 to connect the circuit
(the IC number is printed on top of each IC in silver colour)
2) Remember to connect 5v to vdd pin and 0v to GND pin.
3) Apply 5v for logic 1 level and 0v for logic 0 level at the input terminals of the gate.
4) Apply inputs to the circuits as per truth table
5) Verify the observation table matches with the truth table.

27

28

29

E
1
1
1
1

S0
0
0
1
1

S1
0
1
0
1

Output
D0
D1
D2
D3

Demultiplexer Table
PRECAUTIONS
1) Correct IC should be properly placed on the IC base using pin diagram.
2) The open circuit voltage of the power supply must be stable and near 5.0V.
3) In case the logic gate outputs do not make sense, check your circuit thoroughly. If the
problem is still not resolved, get IC tested by the technician.
RESULT
The operation of 4:1 MUX and 1:4 De-MUX has been verified.

Review Questions
1) How many selection lines are required for a 8:1 multiplexer?
2) What is the difference between decoder & de-multiplexer?
3) Implement all logic gates functioning using multiplexer.
4) Draw a 2:1 MUX diagram using NAND gates?
5) What are the uses of multiplexer?
6) Implement 2:1 DeMUX using AND gates and Tristate buffers.

Results and Discussion

Signature of student:

Signature of instructor

30
Experiment No-6

FLIP-FLOPS USING GATES

LEARNING OBJECTIVE: Functioning of Flip-Flops
AIM: To Construct RS, JK, D flip-flops and to verify their truth tables.
APPARATUS: Bread board, power supply, ICs 7400, 7476, 7402, 7474.
THEORY:
RS flip-flop: A bi-stable multivibrator or flip-flop has two stable states and can remain in either of
these two states unless an external trigger pulse switches it from one state to other. Thus it can stay in
one of the two possible states after an input has applied. The state does not change following the
removal of input. A flip-flop is essentially a one-bit memory or storage device. The basic digital
memory circuits obtained by cross coupling of NAND gates at the output. It is the most basic logic
sequential circuit. it is called the R-S flip-flop because it has two inputs S(sets) R(reset) outputs are
denoted by Q, Q when Q=1,then Q =0,these are the initial signals called present state. This is also
called R-S latch because the 1-bit memory is locked or latched. There are four possible cases
Case (1): when S=0,R=0 the flip-flop remains same and Qn+1=Qn.
Case (2): when S=0,R=1 the flip-flop resets to 0 and Qn+1=0
Case (3): when S=1,R=0 the flip-flop sets to 1 and Qn+1=1
Case (4): when S=1,R=1 and at the same time is forbidden case because the outputs Q & Q both
becomes `0` which is contradictory.
JK FLIP- FLOP: J-K flip-flop is simple an RS flip-flop with two AND gates at the input having
outputs Q, Q connected in cross-coupled fashion. Thus the input to the steering gate A is J, clock and
Q outputs and to the other gate B is K, clock and Q output. Now suppose before clock is applied Q=1,
Q =0,J=1,K=1.when clock pulse arrives, it will make the output to flip-flop as Q=0, Q =1. Thus a
change of state occurs. Thus state will change each time a clock pulse arrives if J=K=1. It means that
flip-flop toggles from one state to other at each clock pulse. Short duration clock pulse is used to
overcome race around problem.

D-FLIP-FLOP: D-flip-flop is JK flip-flop by the addition of not gate at one of the input. Thus K is the
complement of J and only one data input D to the flip-flop necessary. The symbol in figure if
D=0,J=0,K=1 at the negative transition of clock Q=0, Q =1.when D=1,J=1,K=0 at the negative
transition of clock Q=1, Q =0. Thus output after clock is equal to the input at D before clock. The bit
on D-line is transferred to the output at the next clock and this unit functions as one-bit delay device. It
is known as one-bit bistable latch or clocked D-latch.
PROCEDURE:
1. Hook up the circuits as shown in figures
2. Use logic switches for input and indicators for output.
3. Compare both the truth tables to verify their equivalence.
PRECAUTIONS:
1. Connections are made tightly.
2. Connections should be made using patch cards. So that the loose connections that may arise can
be avoided.

31

CIRCUIT DIAGRAM:
RS FLIP-FLOP:
Using NOR Gates:

Using NAND Gates:

TRUTH TABLE:

JK FLIP-FLOP:

Not
allowed
State

Not
allowed
State

Previous Previous
State
State
1
1

32

TRUTH TABLES:
Case-I : Keep Clk=0, Assign Qn= 0, Qn=1 by setting Preset=1, Clear=0 in each case.
CLK

Pr

Cr

Qn

Qn

Q n+1

Comments

Past state

Reset

Set

Toggle

Case-II : Keep Clk=0, Assign Qn= 0, Qn=1 by setting Preset=0, Clear=1 in each case.
CLK

Pr

Cr

Qn

Qn

Q n+1

Comments

Past state

Reset

Past

Toggle

D FLIP-FLOP:

TRUTH TABLE:

Dn

Dn+1

Case-I : Keep Clk=0, Pr=1, Cr=0 , Qn=0 Set in each case.

CLK

Pr

Cr

Dn

Qn

Qn

Q n+1

Case-II : Keep Clk=0, Pr=0, Cr=1 , Qn=1 Set in each case.

CLK

Pr

Cr

Dn

Qn

Qn

Q n+1

33

OBSERVATIONS:
RS FLIP-FLOP:
R

JK FLIP-FLOP:
Case-I :
CLK

Pr

Cr

Qn

Qn

Q n+1

Comments

Pr

Cr

Qn

Qn

Q n+1

Comments

Case-II :
CLK

D FLIP-FLOP:
Case-I : Keep Clk=0, Pr=1, Cr=0 , Qn=0 Set in each case.
CLK

Pr

Cr

Dn

Qn

Qn

Q n+1

Case-II : Keep Clk=0, Pr=0, Cr=1 , Qn=1 Set in each case.

CLK

Pr

Cr

Dn

Qn

Qn

Q n+1

34

RESULT:
R-S, J-K, D-flip-flops are constructed and their truth tables are verified.

Review Questions
1)
2)
3)
4)

What is meant by race around condition?

What are the applications of JK and T Flip Flops?
Define latch?
Draw the graphic symbols for positive-edge-triggered flip-flops and negative-edge-triggered
flip-flops.
5) Draw the graphic symbols for positive latch and negative latch?
6) Draw characteristic table, and excitation table for JK flip-flop.
Result and Discussion

Signature of Student

Signature of Instructor

35
EXPERMENT NO: 7

RING AND JOHNSON COUNTERS

LEARNING OBJECTIVES
To construct and analyze the operation of Ring/Johnson counter made from JK flipflops
AIM:
To study and verify the operation of Ring counter and Johnson counters.
APPARATUS:
1) 5V DC power supply
. 1No
2) Bread board
. 1No
3) IC 7474: dual positive edge triggered flip-flops .2No
PROCEDURE:
RING COUNTER SETUP
1. Identify the pin1 on both IC 7474s. Place the two ICs on bread board mid section.
2. Connect the ring counter circuit as shown in figure.
3. Remember to connect 5V to VDD pin and 0V to GND pin.
4. Apply 5V for logic 1 level and 0V for logic 0 level at the binary inputs.
5. Repeat the steps for all 16 binary input combinations.
CLOCK GENERATION
5) Use a probe to connect the output socket of pulse generator to the circuit.
6) Negative terminal of the probe must be connected to the circuit ground.
7) Set the pulse generator in pulse mode to generate the pulsed through pulse button operation.
8) Remember to set the pulse generator output amplitude to around 5V for proper operation of the
counter.

36

37

38

39

RESULT:
The operation of Ring counter and Johnson counter has been verified.

Review questions
1) What is a sequential circuit?
2) Draw the logic circuit for dividing the clock frequency signal by half using toggle flip-flop.
3) Name other types of counters you are familiar with.
4) What are applications of counters?
5) How many states will be there in an 8-bit ring counter?
6) What are applications of ring counter?
Results and Discussion

Signature of student

Signature of instructor

40
EXPERMENT NO: 8

SYNCHRONOUS COUNTER
LEARNING OBJECTIVES:
To design Arbitrary-sequence synchronous counter
AIM:
To design a synchronous counter for any given count sequence and modulus.
APPARATUS:
1.
2.
3.
4.

5V DC power supply
Bread board
IC 7476:
IC trainer

. 1No
. 1No
. 1No
. 1No

PROCEDURE:
1. Find the number of flip-flops required using equation m2N
2. Write the count sequence in the tabular form
3. Determine the flip-flops inputs, which must be present for the desired next state from the
present state using excitation table.
4. Prepare k-map for each flip-flop input interns of flip-flop output as the input variables.
Simplify the k-map and obtain the minimized expressions.
5. Connect the circuit using flip-flops and other gates corresponding to the minimized
expressions.
DESIGN EXAMPLES
To design a 3-bit synchronous counter excitation table of JK flip-flops

Previous
state
0
0
1
1

Next state

0
1
0
1

0
1
X
X

X
X
1
0

41

42

RESULT:
The synchronous counter for given sequence is designed.

Review questions
1) What is shift register &give different modes of operation
2) Give various types of synchronous counters
3) How shift register acts as ring counter
4) Differentiate synchronous and asynchronous counters

Results and Discussion

Signature of student:

Signature of instructor

43
EXPERMENT NO: 9

CONVERSION OF ONE FLIP-FLOP TO ANOTHER TYPE

Learning objectives:
To understand the design procedure for conversion of flip-flop.
AIM:
To convert D flip-flop to T type , JK flip-flop to D flip-flop, JK flip-flop to T type and D
flip-flop to JK flip=flop.
APPARATUS:
1. 5V DC power supply
2. Bread board
3. IC 7474, 7486, 7408, 7432

. 1No
. 1No
. 1No

PROCEDURE:
Preparation of excitation table (JK flip-flop)
Consider the excitation table of JK flip-flop as shown in figure.
s.no
J
K
Qn

Qn+1

3
4

0
0

1
1

0
1

0
0

44

45

46

47

RESULT:
The conversion of one flip-to another is verified.

Review questions:
1) In converting JK flip flop to T flip-flop,T input interms of J,K and the output is.
2) The output of D flip flop is.when clock is present
3) The number of flip flops for synchronous circuit is determined by.
4) The number of flip flops for mod-n counter are..
5) What are the applications of flip flops?
Results and Discussion

Signature of student:

Signature of instructor

48
EXPERMENT NO: 10

BCD-TO-SEVEN SEGMENT DECODER DRIVER

LEARNING OBJECTIVES:
To understand the design procedure for the BCD-to-seven segment decoder to display decimal
numbers.
Aim:
To design a common Anode type BCD-to- seven segment decoder driver
APPARATUS:
1. IC Trainer
2. Bread board
3. IC 7447
4. FND 500/560

DISPLAY DEVICE:

Pin diagram

.1 no.
1 no.
.1 no.
..1 no

49

There are mainly two types of seven segment displays are there
1) Common cathode (CC)
2) Common anode (CA)
If 7447 is used common anode is used.. Figure below shows the top view of the 7-segment
display. The maximum sink current is 40 mA. 7447 operates upto 15 v, 7446 operates upto 30v

PROCEDURE:
1) Make the truth table for the above decoder circuit.
2) Use k-map to find the expressions for individual output (a, b, g).
3) Make the inter connections using IC 7447 to get the decoder circuit.

Decimal or
Function
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
B1
RB1
LT

LT

RB1

DCBA

B1/REO

a bcdefg

None

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
H
L

H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X

LLLL
LLLH
LLHL
LLHH
LHLL
LHLH
LHHL
LHHH
HLLL
HLLH
HLHL
HLHH
HHLL
HHLH
HHHL
HHHH
XXXX
LLLL
XXXX

H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H

LLLLLLH
HLLHHHH
LLHLLHL
LLLLHHL
HLLHHLL
LHLLHLL
HHLLLLL
LLLHHHH
LLLLLLL
LLLHHLL
HHHLLHL
HHLLHHL
HLHHHLL
LHHLHLL
HHHLLLL
HHHHHHH
HHHHHHH
HHHHHHH
LLLLLLL

A
A

Truth table for 7446 and 7447 BCD to 7-Segment Decoder,

H = Binary 1 L = Binary 0 X = Dont care

B
C
D

50

NOTES
A. BI/RBO represents Blanking Input/Ripple Blanking Out- put. This input must be held at
High or left open for normal operation i.e. for output functions 0 through 15.
B. When a Low is applied to the Blanking Input, all segments go High regardless of any
other input condition.
C. When RBI and inputs A, B, C and D are at Low level. With the Lamp-Test (LT) at High
level, all segments out puts go high and the RBO goes to a Low level.
D. When BI/RBO is high and a Low is applied to the LT input all segment outputs go Low.
E. X indicates don't care i.e. the input may be either High or Low.

RESULT:
The BCD-to-7segment decoder is designed and verified.

Review questions
1) What is the BCD to 7 segment decoder?
2) Differentiate between active low output and active high output
3) Draw the pin diagram for BCD to 7segment decoder
4) How does an encoder differ from decoder?
5) Define decoder?
Results and Discussion

Signature of student:

Signature of instructor

51
Experiment No-11

CD4033 DECADE COUNTER/ SEVEN SEGMENT DECODER

AIM: To study the operation of CD4033 decade counter/ seven segment decoder
MATERIALS NEEDED:
1CD4001 quad 2-input NOR gate
1CD4033 decade counter/decoder
17-segment common-cathode LED display
116 pin dip socket
114 pin dip socket
5SPST switches
1DPDT switch
6100k ohms, Jw resistors
1DC multimeter
19V
CIRCUIT DIAGRAM:

Figure (1). Study of CD4033 Decade Counter/Decoder

Common cathode display is used
No external current limiting resistors are not required
PROCEDURE:
1.
2.
3.
4.
5.

Connect the circuit as shown in Figure (1) Check connections and apply power by Swl.
Close Sw6 and open it. Note the number displayed. Measure the voltages on pins 4 and 5.
Close Sw5. Note the number displayed. Measure the voltages on pins 4 and 5.
Open Sw3 and Sw5. Close Sw4 and note the number displayed.
Apply a clock pulse and note the change in the displayed number and also measure the voltages on
pins 4 and 5 when the clock pulse goes 'high' and when the clock pulse goes 'low'.
6. Repeat step 5 for 20 clock pulses.
7. Open Sw4 and repeat steps 5 and 6.
8. Close Sw3 and repeat step 5 for 4 clock pulses.
9. Close Sw6 and open Sw3.Repeat step 5 for 4 clock pulses.
10. Tabulate your observations as shown in Figure(2). Draw a timing diagram and compare it with
that shown in Fig. 55.

52

Count
0
1
2
3
4
5
6
7
8
9

a
1
0
1
1
0
1
1
1
1
1

b
1
1
1
1
1
0
0
1
1
1

c
1
1
0
1
1
1
1
1
1
1

Decoded Outputs
d
e
1
1
0
0
1
1
1
0
0
0
1
0
1
1
0
0
1
1
1
0

f
1
0
0
0
1
1
1
0
1
1

g
0
0
1
1
1
1
1
0
1
1

cout
1
1
1
1
1
0
0
0
0
0

Table for Experiment of CD4O33

CONCLUSIONS:
1. The CD4 033 is a decade counter and can directly drive a seven-segment common-cathode LED
display.
2. The counter advances one count on the positive going clock transition provided that the lock
Enable and Reset inputs are 'low'.
3. The counting is inhibited if the Clock Enable or the Reset input is 'high'.
4. The counter is reset to zero by a 'high' on the Reset line.
5. The Carry-Out output remains 'high' for counts 0 through 4 and remains 'low' for counts from 5
through 9. The output is therefore, is a symmetrical square wave.
6. AH segment outputs 'a' through 'g' go 'high' and numbei 8 is displayed when the Lamp-Test
input goes 'high'. This input therefore, enables checking of malfunctions in display devices.
7. The figure 0 is bianked out if the Ripple-Blanking-Input (RBI) is 'low'.
8. The Ripple-Blanking-Output (RBO) normally remains 'high' but it goes 'low* during the period
when the number to be displayed is zero, provided that the RBI input is 'low'. The zero remains
blanked out. This output can be used to blank the non-significant zeros in a multi-digit displays.
Review Questions:
1. How will you drive a common-anode seven-segment LED display from the output of a CD4033
2. How will you connect four CD4033 decade counters and four common-cathode displays so that
non-significant zeros on the integer side are not displayed? For example, a number 0070 should
be displayed as 70 only.
3. How will you connect four CD4033 counters and four seven-segment common-cathode displays
to blank out non-significant zeros on the fraction side? For example, the number .0700 should be
displayed as .07 only
RESULTS AND DISCUSSION

Signature of Instructor

Signature of Student

53

EXPERMENT NO: 12

SEQUENCE GENERATOR
LEARNING OBJECTIVES:
To design the sequence generator to generate given binary sequence
Aim:
To design a sequence generator using shift register and multiplexers, to generate the sequence
101..
APPARATUS:
1. IC Trainer
2.Bread board
3.IC 74153,7476,7474

.1 no.
1 no.
.1 no.

PROCEDURE:
1) Determine the number of flip flops required to construct the shift register using the formula 2n L
Where n=number of flip flop.
L= length of sequence.
2) Prepare the table showing the shift register input and corresponding output , assuming sequence is
observed at Qo .
3) From the above table get the expression for shift register input in terms of its outputs
4) Make the connections as per the expression obtained.
5) Set the flip flops to Qo=1,Q1=1 and apply clock pulses to observe the sequence at Qo.
6) For the sequence generator using multiplexer, make the connection as per the given circuit diagram.
DESIGN:
Using shift register
To generate sequence 101.
As L=3, 223, I.e number of flip flops required are 2.
Table:
Do
0
1
1

Qo
1
0
1

Q1
1
1
0

54

55

56

RESULT:
For a given sequence, the sequence generator is designed using shift registers and multiplexers.

Review questions:
1) Define sequence generator?
2) How is average power dissipation in a logic gate calculated?
3) Define noise margin?
4) Draw IEEE rectangular shape symbols for logic gates.
Results and Discussion

Signature of student:

Signature of instructor

57
Experiment No ;13

STUDY OF DECADE COUNTERS USING 7490

AIM: To understand the construction and operation of decade counters using 7490

APPARATUS:
1.Fixed power supply, (5V)
2.Bread board
3.IC 7490
4. Pulse generator

.1 no.
1 no.
.1 no.
.1no.

Description of 7490 decade counter

1) The 7490 integrated circuit counts the number of pulses arriving at its input.
For Mod-10 decimal counter the number of pulses counted (up to 9) appears in binary form on
four pins of the IC. When the tenth pulse arrives at the input, the binary output is reset to zero
(0000) and a single pulse appears at another output pin.
2) Two input NAND gates (2nos) are there to be used for modulo N counter
3) For proper operation of counter, any one terminal of gates (2,3,6 and 7) should be grounded.

PROCEDURE:
1)
2)
3)
4)
5)
6)

Construct the circuit as per the figure given

Apply input to the pin 14
Apply Vcc 5v to the pin 5
Ground the pin 10
Apply switching between R0(1) to R9(1) as per the circuit arrangement.
Collect output at pin 11

PRECAUTIONS:
1. Correct ICs should be placed on IC base using pin diagrams.
2. The open circuit voltage of the power supply should be exactly 5v.
3. Never remove IC or insert IC when the power is on
4. Check +ve and zero terminals for power supply connection.

R0 (1)

R0 (2)

R9 (1)

R9 (2)

58

R0
R9

1) To enable counting one of the input terminals of both gates should be zero
2) If all inputs of single gate R0 (1) and R0 (2) is 1 , the counter resets to 0000.
3) If both inputs of gates R9(1) and R9(2) are 1 , the counter is reset to 1001 (Decimal 9)

59

Asymmetric output

Symmetric output

Review Questions
1) What is the difference between synchronous and asynchronous counters
2) Describe some applications of counters
3) How many states does a mod-n counter have?
4) What do you mean by pre-settable counter
5) What is meant by hybrid counter

RESULTS AND DISCUSSION:

Signature of Student

Signature of Instructor

60
Experiment No: 14

MODULO N COUNTER USING 7490

AIM: To understand the construction and operation of Modulo N counters using 7490

APPARATUS:
1.Fixed power supply, (5V)
2.Bread board
3.IC 7490
4. Pulse generator

.1 no.
1 no.
.1 no.
.1no.

PROCEDURE:
1)
2)
3)
4)
5)
6)
7)
8)

Construct the circuits as per the figurs given

Apply Vcc 5v to the pin 5
Construct divide by 3 counter by connecting 5v to pin 5 and collect o/p from pin 8.
Construct divide by 5 counter by connecting 5v to pin 5 and collect o/p from pin 11.
Construct divide by 6 counter by connecting 5v to pin 5 and collect o/p from pin 12, 9,8,11.
Construct divide by 7 counter by connecting 5v to pin 5 and collect o/p from pin 8.
Construct divide by 8 counter by connecting 5v to pin 5 and collect o/p from pin 12, 9,8,11
Construct divide by 9 counter by connecting 5v to pin 5 and collect o/p from pin 12, 9,8,11

PRECAUTIONS:
1) Correct ICs should be placed on IC base using pin diagrams.
2) The open circuit voltage of the power supply should be exactly 5v.
3) Never remove IC or insert IC when the power is on
4) Check +ve and zero terminals for power supply connection.

61

62

63

Result:
Modulo n counters are studied and the observations as per truth tables are tabulated as shown.

Review questions:
1. Define counter and give differences between different types of counters.
2. What are the basic elements used in counters.
3. Differentiate positive and negative edge triggering of Flip Flops
4. Distinguish between asymmetric and symmetric decade counters.
5. How can you make divide by 1000 counter using three 7490 ICs
Results and Discussion

Signature of student:

Signature of instructor

64
Experiment 15

SHIFT REGISTERS
LEARNING OBJECTIVE: To learn about Right shift and Left shift functions
AIM: To study about Right shift and Left shift operations using IC 7495.
APPARATUS:
1)
2)
3)
4)

IC 7495
Bread Board
Power Supply (+5v)
Connecting wires

. 1no
..1no
..1no

Pin Diagram For 7495

PROCEDURE
1) Mount the 7495 on the bread board and make the connections.
2) Connect logic monitors to pins marked L1, l2, L3, L4
3) Connect pulsar switch A to pin 9 and pulsar switch B to pin 8.
4) Connect the parallel outputs to parallel inputs as shown.
5) Connect switches sw1 to sw4 as shown in figure.
6) Notice that the serial inputs for the left shift will be applied with switch sw4 (pin 5) and serial
inputs for right shift will be entered with switch sw2 (pin 1)
7) Connect pin 14 of the IC to +5v and pin 7 to ground.

65

RIGHT SHIFT FUNCTION

8) Set mode control switch sw3 (pin 6) to low for right shift. Set the serial input sw2 (pin 1) to
low and apply clock pulses with pulsar switch A to clear the register.
9) Enter a 1 at the serial input for right shift with switch sw2 (pin 1) and apply one clock pulse
with pulsar switch A. the register will read now 1000.
10) Enter a 0 at the serial input for right shift with switch sw2 (pin 1) and apply three clock pulses.
The register will now read 0001.
LEFT SHIFT FUNCTION
11) Set mode control switch sw2 (pin 6) to high for left shift and enter a 0 at the serial input for left
shift with switch sw4 (pin 5). Apply one clock pulse with pulsar switch B. the the register will
now read 0010.
12) Enter a 1 at the serial input with sw4 (pin 5) and apply one clock pulse with pulsar switch B.
the register will now read 0101
13) Enter a 0 at the serial input with sw4 (pin 5) and apply clock pulses with pulsar switch B. the
register will now read as follows

After first clock pulse

1010

After second clock pulse 0 1 0 0

After third clock pulse

1000

After fourth clock pulse

0000

66

Result : The Right shift and Left shift operations are observed using IC 7495.

Review Questions
1) What is the purpose of a register?
2) What is meant by SISO, SIPO, PIPO and PIPO?
3) Give applications of registers.
4) What kind of registers is used in RAM?

RESULTS AND DISCUSSION:

Signature of Student

Signature of Instructor