Microcontrolador msp430g2231
Microcontrolador msp430g2231
Microcontrolador msp430g2231
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description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1s.
The MSP430G2x21/31 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer and
ten I/O pins. The MSP430G2x31 family members have a 10-bit A/D converter and built-in communication
capability using synchronous protocols (SPI or I2C). For configuration details, see Table 1.
Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,
and then process the data for display or for transmission to a host system.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
EEM
Flash
(KB)
RAM
(B)
Timer_A
USI
ADC10
Channel
CLOCK
I/O
Package
Type
MSP430G2231IRSA16
MSP430G2231IPW14
MSP430G2231IN14
--
128
1x TA2
10
16-QFN
14-TSSOP
14-PDIP
MSP430G2221IRSA16
MSP430G2221IPW14
MSP430G2221IN14
--
128
1x TA2
--
10
16-QFN
14-TSSOP
14-PDIP
MSP430G2131IRSA16
MSP430G2131IPW14
MSP430G2131IN14
--
128
1x TA2
10
16-QFN
14-TSSOP
14-PDIP
MSP430G2121IRSA16
MSP430G2121IPW14
MSP430G2121IN14
--
128
1x TA2
--
10
16-QFN
14-TSSOP
14-PDIP
Device
PRODUCT PREVIEW
For the most current package and ordering information, see the Package Option Addendum at the end of this document,
or see the TI web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
DVCC
P1.0/TA0CLK/ACLK
14
13
P1.1/TA0.0
P1.2/TA0.1
P1.3
P1.4/SMCLK/TCK
P1.5/TA0.0/SCLK/TMS
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/SDI/SDA/TDO/TDI
P1.6/TA0.1/SDO/SCL/TDI/TCLK
XIN/P2.6/TA0.1
12
N14
PW14
11
10
DVSS
DVSS
DVCC
DVCC
12
P1.1/TA0.0
11
XOUT/P2.7
P1.2/TA0.1
10
TEST/SBWTCK
P1.3
RST/NMI/SBWTDIO
P1.4/SMCLK/TCK
P1.5/TA0.0/SCLK/TMS
P1.6/TA0.1/SDO/SCL/TDI/TCLK
P1.7/SDI/SDA/TDO/TDI
RSA
PRODUCT PREVIEW
16 15 14 13
P1.0/TA0CLK/ACLK
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
DVCC
P1.0/TA0CLK/ACLK/A0
14
13
P1.1/TA0.0/A1
P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREFP1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/A5/SCLK/TMS
12
N14
PW14
11
10
DVSS
XIN/P2.6/TA0.1
XOUT/P2.7
TEST/SBWTCK
RST/NMI/SBWTDIO
P1.7/A7/SDI/SDA/TDO/TDI
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
DVSS
DVSS
DVCC
16 15 14 13
P1.0/TA0CLK/ACLK/A0
12
XIN/P2.6/TA0.1
P1.1/TA0.0/A1
11
XOUT/P2.7
P1.2/TA0.1/A2
10
TEST/SBWTCK
P1.3/ADC10CLK/A3/VREF-/VEREF-
RST/NMI/SBWTDIO
8
P1.7/SDI/SDA/TDO/TDI
P1.6/TA0.1/SDO/SCL/TDI/TCLK
P1.5/TA0.0/SCLK/A5/TMS
RSA
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
PRODUCT PREVIEW
DVCC
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
XOUT
DVCC
DVSS
P1.x
P2.x
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
2 I/O
Interrupt
capability
pull-up/down
resistors
ACLK
Clock
System
SMCLK
Flash
RAM
2KB
1KB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
128B
Emulation
2BP
USI
Brownout
Protection
JTAG
Interface
15-Bit
Timer0_A2
2 CC
Registers
Universal
Serial
Interface
SPI, I2C
P1.x
P2.x
Spy-Bi
Wire
PRODUCT PREVIEW
Watchdog
WDT+
RST/NMI
XOUT
DVCC
DVSS
Port P1
Port P2
8 I/O
Interrupt
capability
pull-up/down
resistors
2 I/O
Interrupt
capability
pull-up/down
resistors
ACLK
Clock
System
ADC
SMCLK
Flash
2kB
1kB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
128B
Emulation
2BP
JTAG
Interface
RAM
10-Bit
8 Ch.
Autoscan
1 ch DMA
USI
Brownout
Protection
Watchdog
WDT+
15-Bit
Timer0_A2
2 CC
Registers
Spy-Bi
Wire
Universal
Serial
Interface
SPI, I2C
RST/NMI
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
16
RSA
NO.
NO.
DESCRIPTION
I/O
P1.0/
TA0CLK/
ACLK/
A0
I/O
P1.1/
TA0.0/
A1
I/O
P1.2/
TA0.1/
A2/
I/O
I/O
I/O
I/O
P1.3/
ADC10CLK/
A3/
VREF--/VEREF/
PRODUCT PREVIEW
14
N, PW
P1.4/
SMCLK/
A4/
VREF+/VEREF+/
TCK
P1.5/
TA0.0/
A5/
SCLK/
TMS
P1.6/
TA0.1/
A6/
SDO/
SCL/
TDI/
TCLK
P1.7/
A7/
SDI/
SDA/
TDO/
TDI
I/O
I/O
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
16
RSA
DESCRIPTION
I/O
NO.
NO.
XIN/
P2.6/
TA0.1
13
12
I/O
XOUT/
P2.7
12
11
I/O
RST/
NMI/
SBWTDIO
10
Reset
Nonmaskable interrupt input
Spy-Bi-Wire test data input/output during programming and test
TEST/
SBWTCK
11
10
Selects test mode for JTAG pins on Port1. The device protection fuse is connected to TEST.
Spy-Bi-Wire test clock input during programming and test
DVCC
16
15
NA
Supply voltage
DVSS
14
14
13
NA
Ground reference
NC
--
--
NA
Not connected
QFN Pad
--
Pad
NA
NOTES: 1. If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
TDO or TDI is selected via JTAG instruction.
PRODUCT PREVIEW
NAME
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
PRODUCT PREVIEW
Program Counter
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
R4 + R5 ------> R5
e.g., CALL
PC ---->(TOS), R8----> PC
e.g., JNE
R8
Jump-on-equal bit = 0
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
F F
MOV EDE,TONI
Absolute
EXAMPLE
F F
MOV &MEM,&TCDAT
OPERATION
R10
----> R11
M(2+R5)----> M(6+R6)
M(EDE) ----> M(TONI)
M(MEM) ----> M(TCDAT)
Indirect
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
Indirect
autoincrement
MOV @Rn+,Rm
MOV @R10+,R11
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
SYNTAX
D = destination
#45
----> M(TONI)
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
operating modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
--
--
PRODUCT PREVIEW
--
CPU is disabled
--
--
--
CPU is disabled
--
--
--
CPU is disabled
--
ACLK is disabled
--
--
--
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PRODUCT PREVIEW
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed) the CPU will
go into LPM4 immediately after power-up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog Timer+
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 and 5)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
maskable
0FFF2h
25
Timer_A2
TACCR1 CCIFG.
TAIFG (see Notes 2 and 3)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
maskable
0FFEAh
21
USI
USIIFG, USISTTIFG
(see Notes 2, 3)
maskable
0FFE8h
20
I/O Port P2
(two flags)
P2IFG.6 to P2IFG.7
(see Notes 2 and 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 and 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
15 ... 0, lowest
(see Note 6)
NOTES: 1. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or
from within unused address ranges.
2. Multiple source flags
3. Interrupt flags are located in the module
4. MSP430G2x31 only.
5. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
6. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
10
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
0h
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
01h
02h
NMIIFG
RSTIFG
PORIFG
OFIFG
rw-0
WDTIFG:
OFIFG:
RSTIFG:
PORIFG:
NMIIFG:
Address
rw-(0)
rw-1
rw-(1)
0
WDTIFG
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power-up
Power-On Reset interrupt flag. Set on VCC power-up.
Set via RST/NMI-pin
7
03h
Legend
rw:
rw-0,1:
rw-(0,1):
11
PRODUCT PREVIEW
Address
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
memory organization
MSP430G2021
MSP430G2031
MSP430G2121
MSP430G2131
MSP430G2221
MSP430G2231
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
512B
0xFFFF to 0xFFC0
0xFFFF to
0xFE00
1kB
0xFFFF to 0xFFC0
0xFFFF to
0xFC00
2kB
0xFFFF to 0xFFC0
0xFFFF to
0xF800
Information memory
Size
Flash
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
256 Byte
010FFh -- 01000h
Size
128B
027Fh -- 0200h
128B
027Fh -- 0200h
128B
027Fh -- 0200h
16-bit
8-bit
8-bit SFR
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
01FFh -- 0100h
0FFh -- 010h
0Fh -- 00h
RAM
Peripherals
flash memory
PRODUCT PREVIEW
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port, or in-system by the CPU. The CPU can
perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming and erasing.
It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data
is required.
12
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, see the MSP430x2xx Family Users Guide.
D Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO CALIBRATION DATA (PROVIDED FROM FACTORY IN FLASH INFO MEMORY
SEGMENT A)
DCO FREQUENCY
CALIBRATION
REGISTER
SIZE
1 MHz
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
PRODUCT PREVIEW
ADDRESS
13
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There is one 8-bit I/O port implementedport P1and two bits of I/O port P2:
D
D
D
D
D
PRODUCT PREVIEW
Timer_A2
Timer_A2 is a 16-bit timer/counter with two capture/compare registers. Timer_A2 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A2 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A2 Signal Connections -- Device with ADC10
Input
Pin Number
14
PW, N
RSA
2 - P1.0
1 - P1.0
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
TACLK
INCLK
Module
Block
Timer
Module
Output Signal
Output
Pin Number
PW, N
RSA
NA
2 - P1.0
1 - P1.0
3 - P1.1
2 - P1.1
TA0
CCI0A
3 - P1.1
2 - P1.1
7 - P1.5
6 - P1.5
ACLK (internal)
CCI0B
7 - P1.5
6 - P1.5
VSS
GND
4 - P1.2
3 - P1.2
VCC
VCC
4 - P1.2
3 - P1.2
TA1
CCI1A
8 - P1.6
7 - P1.6
TA1
CCI1B
VSS
GND
VCC
VCC
CCR0
CCR1
TA0
TA1
8 - P1.6
7 - P1.6
13 - P2.6
12 - P2.6
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
USI
The universal serial interface (USI) module is used for serial data communication and provides the basic
hardware for synchronous communication protocols like SPI and I2C.
PRODUCT PREVIEW
The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion
result handling, allowing ADC samples to be converted and stored without any CPU intervention.
15
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
ADC control 0
ADC control 1
ADC memory
ADC10CTL0
ADC10CTL0
ADC10MEM
01B0h
01B2h
01B4h
Timer_A
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR1
TACCR0
TAR
TACCTL1
TACCTL0
TACTL
TAIV
0174h
0172h
0170h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog Timer+
Watchdog/timer control
WDTCTL
0120h
PRODUCT PREVIEW
16
ADC10
(MSP430G2x31 only)
Analog enable
ADC10AE
04Ah
USI
USI control 0
USI control 1
USI clock control
USI bit counter
USI shift register
USICTL0
USICTL1
USICKCTL
USICNT
USISR
078h
079h
07Ah
07Bh
07Ch
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
MAX
UNIT
1.8
3.6
2.2
3.6
I Version
--40
85
VCC = 1.8 V,
Duty Cycle = 50% 10%
dc
4.15
VCC = 2.7 V,
Duty Cycle = 50% 10%
dc
12
VCC 3.3 V,
Duty Cycle = 50% 10%
dc
16
MHz
16 MHz
12 MHz
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
17
PRODUCT PREVIEW
MIN
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
TEST CONDITIONS
TA
VCC
MIN
2.2 V
TYP
MAX
UNIT
220
A
3V
300
370
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
fDCO = 16 MHz
4.0
PRODUCT PREVIEW
5.0
3.0
fDCO = 12 MHz
2.0
1.0
fDCO = 8 MHz
TA = 25 C
2.0
2.0
2.5
3.0
3.5
TA = 25 C
1.0
VCC = 2.2 V
4.0
0.0
0.0
18
VCC = 3 V
TA = 85 C
fDCO = 1 MHz
0.0
1.5
TA = 85 C
3.0
4.0
8.0
12.0
16.0
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low-power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
TA
VCC
Low-power mode 0
(LPM0) current,
see Note 3
fMCLK = 0 MHz,
fSMCLK = fDCO = 1 MHz,
fACLK = 32,768 Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
25C
2.2 V
65
ILPM2
Low-power mode 2
(LPM2) current,
see Note 4
25C
2.2 V
22
ILPM3,LFXT1
Low-power mode 3
(LPM3) current,
see Note 4
25C
2.2 V
0.7
1.5
ILPM3,VLO
Low-power mode 3
current, (LPM3)
see Note 4
25C
2.2 V
0.5
0.7
25C
2.2 V
0.1
1.5
ILPM4
Low-power mode 4
(LPM4) current,
current
see Note 5
85C
2.2 V
0.8
1.5
ILPM0, 1MHz
NOTES: 1.
2.
3.
4.
5.
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PRODUCT PREVIEW
PARAMETER
All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF.
Current for brownout and WDT clocked by SMCLK included.
Current for brownout and WDT clocked by ACLK included.
Current for brownout included.
19
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- LPM3 current
9.0
8.0
7.0
6.0
5.0
Vcc = 3.6 V
4.0
Vcc = 3 V
3.0
Vcc = 2.2V
2.0
1.0
0.0
--40.0 --20.0 0.0
Vcc = 1.8 V
20.0 40.0 60.0 80.0 100.0 120.0
TA -- Temperature -- C
PRODUCT PREVIEW
10.0
9.0
8.0
7.0
6.0
5.0
Vcc = 3.6 V
4.0
Vcc = 3 V
3.0
Vcc = 2.2V
2.0
1.0
0.0
--40.0 --20.0 0.0
Vcc = 1.8 V
20.0 40.0 60.0 80.0 100.0 120.0
TA -- Temperature -- C
20
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs -- Ports Px
PARAMETER
VIT+
TEST CONDITIONS
VCC
MAX
UNIT
0.45
0.75
VCC
1.35
2.25
0.25
0.55
VCC
3V
0.75
1.65
3V
0.3
1.0
3V
20
50
3V
VIT--
Vhys
RPull
Pull-up/pull-down resistor
CI
Input Capacitance
MIN
TYP
35
5
pF
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
PARAMETER
Ilkg(Px.x)
TEST CONDITIONS
VCC
MIN
TYP
3V
MAX
UNIT
50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull-up/pull-down resistor is
disabled.
outputs -- Ports Px
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MA
X
UNIT
VOH
3V
VCC --0.3
VOL
3V
VSS+0.3
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum
voltage drop specified.
TEST CONDITIONS
VCC
fPx.y
MIN
TYP
MAX
UNIT
3V
12
MHz
fPort_CLK
Px.y, CL = 20 pF
(see Note 2)
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 k between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
21
PRODUCT PREVIEW
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
25.0
TA = 25C
TA = 85C
20.0
15.0
10.0
5.0
0.5
1.0
1.5
2.0
VCC = 2.2 V
P1.7
0.0
0.0
VCC = 3 V
P1.7
TA = 85C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
1.5
2.0
2.5
3.0
3.5
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
I OH -- Typical High-Level Output Current -- mA
VCC = 2.2 V
P1.7
--5.0
--10.0
--15.0
TA = 85C
--20.0
TA = 25C
0.5
1.0
1.5
2.0
2.5
VCC = 3 V
P1.7
--10.0
--20.0
--30.0
TA = 85C
--40.0
TA = 25C
--50.0
0.0
0.5
1.0
1.5
Figure 6
Figure 7
2.0
2.5
3.0
22
1.0
Figure 4
--25.0
0.0
TA = 25C
40.0
PRODUCT PREVIEW
30.0
3.5
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC(start)
(see Figure 8)
dVCC/dt 3 V/s
0.7 V(B_IT--)
V(B_IT--)
dVCC/dt 3 V/s
1.35
Vhys(B_IT--)
(see Figure 8)
dVCC/dt 3 V/s
140
mV
td(BOR)
(see Figure 8)
t(reset)
2000
2.2 V/3 V
s
s
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT--)
+ Vhys(B_IT--) is 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
DCO settings must not be changed until VCC VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
PRODUCT PREVIEW
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
0
t d(BOR)
23
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
VCC
3V
VCC(drop) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(drop)
0.5
0
0.001
1000
1 ns
1 ns
tpw -- Pulse Width -- s
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
PRODUCT PREVIEW
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
24
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average =
32 f DCO(RSEL,DCO) f DCO(RSEL,DCO+1)
MOD f DCO(RSEL,DCO)+(32MOD) f DCO(RSEL,DCO+1)
DCO frequency
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
RSELx = 14
2.2
3.6
Vcc
fDCO(0,0)
3V
fDCO(0,3)
3V
0.12
MHz
fDCO(1,3)
3V
0.15
MHz
fDCO(2,3)
3V
0.21
MHz
fDCO(3,3)
3V
0.30
MHz
fDCO(4,3)
3V
0.41
MHz
fDCO(5,3)
3V
0.58
MHz
fDCO(6,3)
3V
0.80
fDCO(7,3)
3V
fDCO(8,3)
3V
1.60
MHz
fDCO(9,3)
3V
2.30
MHz
fDCO(10,3)
3V
3.40
MHz
fDCO(11,3)
3V
fDCO(12,3)
3V
fDCO(13,3)
3V
fDCO(14,3)
3V
fDCO(15,3)
3V
15.25
MHz
fDCO(15,7)
3V
21.00
MHz
SRSEL
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
3V
1.35
SDCO
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
3V
1.08
3V
50
RSELx = 15
Duty Cycle
3.0
3.6
0.06
0.14
MHz
0.80
MHz
1.50
4.25
4.30
MHz
7.30
7.80
8.60
MHz
MHz
MHz
13.9
MHz
ratio
25
PRODUCT PREVIEW
PARAMETER
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30C and 3.0V
0C to 85C
3.0 V
--3
0.5
+3
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30C and 3.0V
30C
1.8 V -- 3.6 V
--3
+3
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
calibrated at 30C and 3.0V
--40C to
85C
1.8 V -- 3.6 V
--6
+6
MIN
TYP
MAX
NOTES: 1. This is the frequency change from the measured frequency at 30C over temperature.
tDCO,LPM3/4
tCPU,LPM3/4
TEST CONDITIONS
VCC
BCSCTL1= CALBC1_1MHz
DCOCTL = CALDCO_1MHz
3V
1.5
UNIT
s
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
10.00
DCO Wake Time -- us
PRODUCT PREVIEW
PARAMETER
DCO clock wake-up time from
LPM3/4
(see Note 1)
1.00
0.10
0.10
RSELx = 0...11
RSELx = 12...15
1.00
10.00
26
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
TEST CONDITIONS
VCC
fLFXT1,LF
XTS = 0, LFXT1Sx = 0 or 1
1.8 V to 3.6 V
fLFXT1,LF,logic
XTS = 0, XCAPx = 0,
LFXT1Sx = 3
1.8 V to 3.6 V
OALF
CL,eff
MIN
TYP
MAX
32768
10000
32768
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
XTS = 0, LFXT1Sx = 0,
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
200
UNIT
Hz
50000
Hz
XTS = 0, XCAPx = 0
XTS = 0, XCAPx = 1
5.5
XTS = 0, XCAPx = 2
8.5
XTS = 0, XCAPx = 3
11
Duty cycle
LF mode
XTS = 0,
Measured at P2.0/ACLK,
fLFXT1,LF = 32,768Hz
fFault,LF
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
2.2 V
30
2.2 V
10
50
pF
70
10000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and
frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep the trace between the device and the crystal as short as possible.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
VCC
MIN
TYP
MAX
fVLO
PARAMETER
VLO frequency
TEST CONDITIONS
-40 -- 85C
3.0 V
12
20
dfVLO/dT
VLO frequency
temperature drift
-40 -- 85C
3.0 V
dfVLO/dVCC
25C
1.8 V -- 3.6 V
UNIT
kHz
0.5
%/C
%/V
27
PRODUCT PREVIEW
PARAMETER
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
tTA,cap
TA0, TA1
VCC
MIN
TYP
MAX
fSYSTEM
3.0 V
20
VCC
MIN
UNIT
MHz
ns
TEST CONDITIONS
fUSI
External: SCLK;
Duty Cycle = 50% 10%;
SPI Slave Mode
VOL,I2C
TYP
MAX
fSYSTEM
3.0 V
VSS
UNIT
MHz
VSS+0.4
5.0
5.0
TA = 25C
4.0
3.0
TA = 85C
2.0
1.0
0.0
0.0
0.2
0.4
0.6
0.8
1.0
4.0
TA = 85C
3.0
2.0
1.0
0.0
0.0
28
TA = 25C
VCC = 3 V
I OL -- Low-Level Output Current -- mA
VCC = 2.2 V
I OL -- Low-Level Output Current -- mA
PRODUCT PREVIEW
0.2
0.4
0.6
0.8
1.0
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, power supply and input range conditions -- MSP430G2x31 only
TEST CONDITIONS
TA
VCC
VSS = 0 V
VAx
All Ax terminals.
Analog inputs selected in
ADC10AE register.
25C
25C
25C
IREFB,1
CI
IADC10
IREF+
IREFB,0
RI
NOTES: 1.
2.
3.
4.
VCC
3V
MIN
TYP
MAX
UNIT
2.2
3.6
VCC
3V
0.6
mA
3V
0 25
0.25
mA
25C
3V
1.1
mA
25C
3V
0.5
mA
Input capacitance
25C
3V
0V VAx VCC
25C
3V
27
1000
pF
The leakage current is defined in the leakage current table with Px.x/Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR-- for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC10.
The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a
conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.
29
PRODUCT PREVIEW
PARAMETER
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, built-in voltage reference -- MSP430G2x31 only
PARAMETER
VCC,REF+
Positive built
built-in
in reference analog
supply voltage range
VREF+
Positi e b
Positive
built-in
ilt in reference voltage
oltage
ILD,VREF+
TEST CONDITIONS
MIN
2.2
2.9
TYP
MAX
UNIT
V
3V
1.41
1.5
1.59
3V
2.35
2.5
2.65
V
V
3V
mA
3V
LSB
3V
LSB
IVREF+ =
100A900A,
VAx 0.5 x VREF+
Error of conversion
result 1 LSB
3V
400
ns
CVREF+
IVREF+ 1mA,
REFON = 1, REFOUT = 1
3V
100
pF
TCREF+
Temperature coefficient
3V
tREFON
tREFBURST
PRODUCT PREVIEW
VCC
30
ADC10SR = 0
ADC10SR = 0
100 ppm/C
3.6 V
30
3V
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, external reference -- MSP430G2x31 only
VEREF+
TEST CONDITIONS
UNIT
V
1.4
3.0
1.2
1.4
VCC
VEREF
MAX
VCC
IVEREF--
TYP
1.4
MIN
VEREF--
IVEREF+
VCC
0V VEREF+ VCC,
SREF1 = 1, SREF0 = 0
3V
3V
0V VEREF-- VCC
3V
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer
supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.
4. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
5. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied
with reduced accuracy requirements.
31
PRODUCT PREVIEW
PARAMETER
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, timing parameters -- MSP430G2x31 only
PARAMETER
For specified
performance of
ADC10 linearity
parameters
fADC10CLK
ADC10 inp
inputt clock frequency
freq enc
fADC10OSC
tCONVERT
tADC10ON
PRODUCT PREVIEW
TEST CONDITIONS
VCC
MIN
MAX
UNIT
ADC10SR = 0
3V
0.45
6.3
ADC10SR = 1
3V
0.45
1.5
ADC10DIVx=0, ADC10SSELx = 0
fADC10CLK = fADC10OSC
3V
3.7
6.3
MHz
3V
2.06
3.51
MH
MHz
13
ADC10DIV
1/fADC10CLK
TYP
(see Note 1)
s
100
ns
NOTES: 1. The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already
settled.
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
EI
3V
LSB
ED
3V
LSB
EO
Offset error
LSB
EG
Gain error
3V
1.1
LSB
ET
3V
LSB
32
3V
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
10-bit ADC, temperature sensor and built-in VMID -- MSP430G2x31 only
ISENSOR
TCSENSOR
TEST CONDITIONS
VCC
MIN
TYP
3V
60
3V
3.55
tSensor(sample)
3V
IVMID
3V
VMID
3V
tVMID(sample)
3V
MAX
A
mV/C
30
s
NA
1.5
1220
UNIT
A
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1), or (ADC10ON=1 and INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature
sensor input (INCH = 0Ah).
2. The following formula can be used to calculate the temperature sensor output voltage:
VSensor,typ = TCSensor ( 273 + T [C] ) + VOffset,sensor [mV] or
VSensor,typ = TCSensor T [C] + VSensor(TA = 0C) [mV]
3. Values are not based on calculations using TCSensor or VOffset,sensor but on measurements.
4. The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on).
5. No additional current is needed. The VMID is used during sampling.
6. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
33
PRODUCT PREVIEW
PARAMETER
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
flash memory
PARAMETER
VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
TYP
2.2
fFTG
IPGM
2.2 V/3.6 V
257
1
IERASE
2.2 V/3.6 V
tCPT
2.2 V/3.6 V
tCMErase
2.2 V/3.6 V
TJ = 25C
MAX
476
kHz
mA
mA
10
ms
ms
105
tRetention
tWord
30
tBlock, 0
25
tBlock, 1-63
tBlock, End
tMass Erase
tSeg Erase
cycles
100
years
18
see Note 2
UNIT
3.6
20
104
Program/Erase endurance
PRODUCT PREVIEW
MIN
tFTG
6
10593
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controllers state machine (tFTG = 1/fFTG).
RAM
PARAMETER
V(RAMh)
TEST CONDITIONS
CPU halted
MIN
1.6
TYP
MAX
UNIT
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
34
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
JTAG and Spy-Bi-Wire interface
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
fSBW
2.2 V / 3 V
20
MHz
tSBW,Low
2.2 V / 3 V
0.025
15
us
tSBW,En
2.2 V/ 3 V
us
tSBW,Ret
2.2 V/ 3 V
15
100
2.2 V
MHz
3V
10
MHz
2.2 V/ 3 V
25
90
fTCK
RInternal
60
us
PARAMETER
VCC(FB)
VFB
IFB
tFB
TA = 25C
VCC
MIN
TYP
MAX
2.5
6
UNIT
V
100
mA
ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible and JTAG is switched
to bypass mode.
35
PRODUCT PREVIEW
NOTES: 1. Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWTCK pin high
before applying the first SBWTCK clock edge.
2. fTCK may be restricted to meet the timing requirements of the module selected.
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 -- P1.3, input/output with Schmitt trigger -- MSP430G2x21
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
PxOUT.y
From Timer
DVSS
DVCC
PRODUCT PREVIEW
P1.0/TA0CLK/ACLK
P1.1/TA0.0
P1.2/TA0.1
P1.3
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
X
0
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
TA0CLK/
TA0.TACLK
ACLK/
ACLK
P1.0/
P1.1/
TA0.0/
P1.2/
TA0.1/
P1.3/
36
P1.x (I/O)
P1.x (I/O)
I: 0; O: 1
TA0.0
TA0.CCI0A
P1.x (I/O)
I: 0; O: 1
TA0.1
TA0.CCI1A
I: 0; O: 1
P1.x (I/O)
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 pin schematic: P1.0 -- P1.3, input/output with Schmitt trigger -- MSP430G2x21
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
PxOUT.y
From Module
DVSS
DVCC
0
1
P1.4/SMCLK/TCK
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
PxIFG.y
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
X
4
FUNCTION
P1SEL.x
JTAG
Mode
I: 0; O: 1
SMCLK/
SMCLK
TCK
TCK
P1.4/
P1.x (I/O)
P1DIR.x
37
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PxDIR.y
From USI
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE5
PxOUT.y
From USI
DVSS
DV CC
0
1
P1.5/TA0.0/SCLK/TMS
PxSEL.y
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
EN
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
X
5
FUNCTION
P1SEL.x
USIP.x
JTAG
Mode
I: 0; O: 1
TA0.0/
TA0.0
SCLK/
SCLK
SIMO0/
SIMO0
TMS
TMS
P1.5/
38
P1.x (I/O)
P1DIR.x
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE6
PxOUT.y
From Module
DVSS
DV CC
0
1
P1.6/TA0.1/SDO/SCL/TDI
PxSEL.y
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
X
6
FUNCTION
P1SEL.x
USIP.x
JTAG
Mode
I: 0; O: 1
TA0.1/
TA0.1
SDO/
SDO
TDI/TCLK
TDI/TCLK
P1.6/
P1.x (I/O)
P1DIR.x
39
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PxDIR.y
From USI
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE7
PxOUT.y
From USI
DVSS
DVCC
0
1
P1.7/SDI/SDA/TDO/TDI
PxSEL.y
PRODUCT PREVIEW
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Q
PxIFG.y
Set
Interrupt
Edge
Select
PxSEL.y
PxIES.y
From JTAG
To JTAG
From JTAG
To JTAG
P1.x (I/O)
I: 0; O: 1
SDI/SDO
SDI/SDO
TDO/TDI
TDO/TDI
P1.7/
40
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P1 pin schematic: P1.0 -- P1.2, input/output with Schmitt trigger -- MSP430G2x31
To ADC10
INCHx
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
ACLK
DVCC
0
1
Bus
Keeper
EN
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1
P1.2/TA0.1/A2
PRODUCT PREVIEW
PxOUT.y
DVSS
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
41
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
X
0
FUNCTION
P1SEL.x
ADC10AE.x
(INCH.y = 1)
I: 0; O: 1
TA0CLK/
TA0.TACLK
ACLK/
ACLK
P1.0/
A0
A0/
P1.1/
TA0.0/
A1/
P1.2/
TA0.1/
1 (y = 0)
I: 0; O: 1
TA0.0
TA0.CCI0A
A1
1 (y = 1)
P1.x (I/O)
P1.x (I/O)
I: 0; O: 1
TA0.1
TA0.CCI1A
A2
1 (y = 2)
PRODUCT PREVIEW
A2/
P1.x (I/O)
P1DIR.x
42
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
VSS
0
1
To ADC10
INCHx = y
ADC10AE0.y
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxSEL.y
PxOUT.y
ACLK
DVSS
DV CC
PRODUCT PREVIEW
PxREN.y
0
1
P1.3/ADC10CLK/A3/VREF-/VEREF-
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
X
3
FUNCTION
P1SEL.x
ADC10AE.x
(INCH.x = 1)
CAPD.y
I: 0; O: 1
ADC10CLK/
ADC10CLK
A3
A3
1 (y = 3)
VREF--/
VREF--
VEREF--
VEREF--
CA3
CA3
1 (y = 3)
P1.3/
P1.x (I/O)
P1DIR.x
43
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
ADC10AE0.y
PxSEL.y
PxDIR.y
Direction
0: Input
1: Output
PxREN.y
PRODUCT PREVIEW
PxSEL.y
PxOUT.y
ACLK
DVSS
DV CC
0
1
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
44
P1.4/SMCLK/A4/VREF+/VEREF+/TCK
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
X
4
FUNCTION
P1SEL.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
SMCLK
A4/
A4
1 (y = 4)
VREF+/
VREF+
VEREF+/
VEREF+
CA4/
CA4
TCK
TCK
PRODUCT PREVIEW
I: 0; O: 1
SMCLK/
P1.4/
P1.x (I/O)
P1DIR.x
45
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PxDIR.y
PxSEL.y
1
Direction
0: Input
1: Output
PxREN.y
PxSEL.y
PxOUT.y
From Module
DVSS
DVCC
0
1
PRODUCT PREVIEW
Bus
Keeper
EN
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
46
P1.5/TA0.0/A5/TMS
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
X
5
FUNCTION
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
TA0.0
A5/
A5
1 (y = 5)
SCLK/
SCLK
SIMO0/
SIMO0
TMS
TMS
PRODUCT PREVIEW
I: 0; O: 1
TA0.0/
P1.5/
P1.x (I/O)
P1DIR.x
47
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PxDIR.y
from USI
USIPE6
1
Direction
0: Input
1: Output
PxREN.y
PxSEL.y or
USIPE6
PxOUT.y
From USI
DVSS
DV CC
0
1
PRODUCT PREVIEW
Bus
Keeper
EN
PxSEL.y
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
48
P1.6/TA0.1/SDO/SCL/A6/TDI
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
X
6
FUNCTION
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
TA0.1
A6/
A6
1 (y = 6)
SDO/
SDO
TDI/TCLK
TDI/TCLK
PRODUCT PREVIEW
I: 0; O: 1
TA0.1/
P1.6/
P1.x (I/O)
P1DIR.x
49
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
PxDIR.y
from USI
PxREN.y
USIPE7
1
Direction
0: Input
1: Output
PxSEL.y
PxSEL.y or
USIPE7
PxOUT.y
From USI
DVSS
DVCC
0
1
PRODUCT PREVIEW
Bus
Keeper
EN
PxSEL.y
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
From JTAG
To JTAG
From JTAG
To JTAG
USI in I2C mode: Output driver drives low level only. Driver is disabled in JTAG mode.
50
P1.7/SDI/SDA/A7/TDO/TDI
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
X
7
FUNCTION
P1SEL.x
USIP.x
ADC10AE.x
(INCH.x = 1)
JTAG
Mode
A7
1 (y = 7)
SDI/SDO
SDI/SDO
TDO/TDI
TDO/TDI
PRODUCT PREVIEW
I: 0; O: 1
A7/
P1.7/
P1.x (I/O)
P1DIR.x
51
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P2 pin schematic: P2.6, input/output with Schmitt trigger -- MSP430G2x21 and MSP430G2x31
XOUT/P2.7
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
0
1
PxSEL.6
PxDIR.y
Direction
0: Input
1: Output
PRODUCT PREVIEW
PxREN.y
PxSEL.6
PxOUT.y
from Module
DV SS
DV CC
Bus
Keeper
EN
XIN/P2.6/TA0.1
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
EN
Set
PxIFG.y
Interrupt
Edge
Select
PxSEL.y
PxIES.y
X
6
FUNCTION
XIN
P2.6
P2.x (I/O)
TA0.1
Timer0_A3.TA1
52
P2SEL.6
PSEL2.7
I: 0; O: 1
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
Port P2 pin schematic: P2.7, input/output with Schmitt trigger -- MSP430G2x21 and MSP430G2x31
XIN/P2.6/TA0.1
LF off
PxSEL.6
PxSEL.7
BCSCTL3.LFXT1Sx = 11
LFXT1CLK
PxDIR.y
1
0
from P2.6/XIN
Direction
0: Input
1: Output
PRODUCT PREVIEW
PxSEL.7
PxREN.y
PxSEL.7
PxOUT.y
from Module
DVSS
DV CC
Bus
Keeper
EN
XOUT/P2.7
PxIN.y
To Module
PxIE.y
PxIRQ.y
Q
PxIFG.y
PxSEL.y
PxIES.y
EN
Set
Interrupt
Edge
Select
53
MSP430G2x21, MSP430G2x31
MIXED SIGNAL MICROCONTROLLER
SLAS694B -- FEBRUARY 2010 -- REVISED MAY 2010
FUNCTION
XOUT
P2.x (I/O)
PRODUCT PREVIEW
P2.7
54
P2DIR.x
P2SEL.6
P2SEL.7
P2SEL.7
I: 0; O: 1
www.ti.com
26-May-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
(3)
Samples
(Requires Login)
MSP430G2121IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2121IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2121IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2121IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2121IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2131IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2131IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2131IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2131IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2131IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2221IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
MSP430G2221IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2221IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2221IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2221IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
MSP430G2231IN14
ACTIVE
PDIP
14
25
Pb-Free (RoHS)
CU NIPDAU Level-1-260C-UNLIM
MSP430G2231IPW14
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
MSP430G2231IPW14R
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
Addendum-Page 1
www.ti.com
Orderable Device
26-May-2010
Status
(1)
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
(3)
Samples
(Requires Login)
MSP430G2231IRSA16R
ACTIVE
QFN
RSA
16
3000
Green (RoHS
& no Sb/Br)
MSP430G2231IRSA16T
ACTIVE
QFN
RSA
16
250
Green (RoHS
& no Sb/Br)
Purchase Samples
(1)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
PW (R-PDSO-G**)
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
7
0 8
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
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