Index

S No.

Experiment Name

Design of inverter using microwind and observe the

waveform.
Design of NAND using microwind and observe the
waveform.
Design of NOR using microwind and observe the
waveform.
Design of AND using microwind and observe the
waveform.
Design of OR using microwind and observe the
waveform.
Design of XOR using microwind and observe the
waveform.
Design of XNOR using microwind and observe the
waveform.
Design of Full adder using microwind and observe the
waveform.
10.

Design of Boolean Expression using microwind and

observe the waveform.
Vout = [(A + B) * C + (DE)]
Design of Boolean Expression using microwind and
observe the waveform.
Vout = [(A*Bbar+ B*Abar) * (C + D)*CD)]

Date

Sign

Remark

Experiment No.1
Aim- Design of inverter using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- In digital logic, an inverter or NOT gate is a logic gate which implements logical
negation. An inverter circuit outputs a voltage representing the opposite logic-level to its
input. Inverters can be constructed using two complimentary transistors in a CMOS
configuration. This configuration greatly reduces power consumption since one of the
transistors is always off in both logic states. Processing speed can also be improved due to the
relatively low resistance compared to the NMOS-only or PMOS-only type devices.
Truth table of NOT Gate:
Static CMOS Inverter:
Traditional NOT Gate logic symbol:

Result-

Experiment No.2
Aim- Design of NAND using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- The NAND gate is a digital logic gate that behaves in such a way that when A LOW
output results only if both the inputs to the gate are HIGH. If one or both inputs are LOW, a
HIGH output results. The NAND gate is a universal gate in the sense that any Boolean
function can be implemented by NAND gates.
Truth table of NAND Gate:

CMOS NAND Gate:

Result-

Traditional NAND Gate Logic symbol:

Experiment No.3
Aim- Design of NOR using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- The NOR gate is a digital logic gate that implements logical NOR. A HIGH output
(1) results if both the inputs to the gate are LOW (0). If one or both input is HIGH (1), a LOW
output (0) results. NOR is the result of the negation of the OR operator. NOR is a functionally
complete operation -- combinations of NOR gates can be combined to generate any other
logical function. By contrast, the OR operator is monotonic as it can only change LOW to
HIGH but not vice versa.
Traditional NOR Gate logic symbol:

CMOS NOR Gate:

Result-

Truth table for NOR Gate:

Experiment No.4
Aim- Design of AND using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- The AND gate is a digital logic gate that implements logical conjunction. A HIGH
output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one
input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND
effectively finds the minimum between two binary digits, just as the OR function finds the
maximum.
Traditional AND Gate logic symbol:

CMOS AND Gate:

Result-

Truth table for AND Gate:

Experiment No.5
Aim- Design of OR using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- The OR gate is a digital logic gate that implements logical disjunction. A HIGH
output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is HIGH, a
LOW output (0) results. In another sense, the function of OR effectively finds the maximum
between two binary digits, just as the complementary AND function finds the minimum.
Traditional OR Gate logic symbol:

CMOS OR Gate:

Result-

Truth table of OR Gate:

Experiment No.6
Aim- Design of XOR using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- The XOR gate (sometimes EOR gate) is a digital logic gate that implements
exclusive disjunction. A HIGH output (1) results if one, and only one, of the inputs to the gate
is HIGH (1). If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results.
XOR gate is short for exclusive OR. This means that precisely one input must be 1 (true) for
the output to be 1 (true). A way to remember XOR is "one or the other but not both." This
function is addition modulo 2. As a result, XOR gates are used to implement binary addition
in computers.
Traditional ExOR Gate logic symbol:

CMOS ExOR Gate:

Truth table for ExOR Gate:

Result-

Experiment No.7
Aim- Design of XNOR using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- The XNOR gate (sometimes spelled 'exnor') is a digital logic gate whose function is
the inverse of the exclusive OR (XOR) gate. The two-input version implements logical
equality. A HIGH output (1) results if both of the inputs to the gate are the same. If one but
not both inputs are HIGH (1), a LOW output (0) results.
Truth table for Exnor Gate:

CMOS Exnor Gate:

Result-

Traditional Exnor Gate logic symbol

Experiment No.8
Aim- Design of Full adder using microwind and observe the waveform.
Software required- Microwind 3.0
Theory- An adder or summer is a digital circuit that performs addition of numbers. A full
adder is capable of adding three bits: two bits and one carry bit of earlier calculation. It has
three inputs - A, B, and carry C, such that multiple full adders can be used to add larger
numbers.
Full Adder circuit diagram:

CMOS Full adder Circuit:

Truth table for full adder:

Result-

Experiment No.9
Aim- Design of Boolean Expression using microwind and observe the waveform.
Vout = [(A + B) * C + (DE)]
Software required- Microwind 3.0
Theory- An Euler path in a graph is a path which traverses each edge of the graph exactly
once. An Euler path which is a cycle is called an Euler cycle. For loopless graphs without
isolated vertices, the existence of an Euler path implies the connectedness of the graph, since
traversing every edge of such a graph requires visiting each vertex at least once. A connected
graph has an Euler path if it has exactly zero or two vertices of odd degree. If every vertex has
even degree, the graph has an Euler cycle.
CMOS Circuit Diagram:

Eulers Path:

Truth table for the given Boolean expression:

(A

Vo

Out = (A+B)*C + DE

Result-

Experiment No.10
Aim- Design of Boolean Expression using microwind and observe the waveform.
Vout = [(A*Bbar+ B*Abar) * (C + D)*CD)]
Software required- Microwind 3.0
Theory- An Euler path in a graph is a path which traverses each edge of the graph exactly
once. An Euler path which is a cycle is called an Euler cycle. For loopless graphs without
isolated vertices, the existence of an Euler path implies the connectedness of the graph, since
traversing every edge of such a graph requires visiting each vertex at least once. A connected
graph has an Euler path if it has exactly zero or two vertices of odd degree. If every vertex has
even degree, the graph has an Euler cycle.
CMOS Circuit Diagram:

Eulers Path:

Truth table for the given Boolean expression:

Result-