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Verilog Code For Fir Filter

The document describes Verilog code for implementing a FIR filter. It includes code for a main filterfir module that contains a dff module for a D flip-flop. It takes in an input signal x and clock and outputs a filtered dataout signal. It also contains testbench code that applies test inputs to the filter over time.

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1K views

Verilog Code For Fir Filter

The document describes Verilog code for implementing a FIR filter. It includes code for a main filterfir module that contains a dff module for a D flip-flop. It takes in an input signal x and clock and outputs a filtered dataout signal. It also contains testbench code that applies test inputs to the filter over time.

Uploaded by

sivasankarmeae
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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VERILOG CODE FOR FIR FILTER

// main module FIR


module filterfir(clk,rst,x,dataout);
input [7:0]x;
input clk,rst;
output [9:0]dataout;
wire [7:0]d1,d2,d3;
wire [7:0]m1,m2,m3,m4,m5;
wire [7:0]d11,d12,d13,d14;
parameter h0=3'b101;
parameter h1=3'b100;
parameter h2=3'b011;
parameter h3=3'b010;
parameter h4=3'b001;
assign m1=x>>h0;
dff u2(clk,rst,x,d11);
assign m2=d11>>h1;
assign d1=m1+m2;
dff u4(clk,rst,d11,d12);
assign m3=d12>>h2;
assign d2=d1+m3;
dff u6(clk,rst,d12,d13);
assign m4=d13>>h3;
assign d3=d2+m4;
dff u8(clk,rst,d13,d14);
assign m5=d14>>h4;
assign dataout=d3+m5;
endmodule

module dff(clk,rst,d,q);// sub module d flipflop


input clk,rst;
input [7:0]d;
output [7:0]q;
reg [7:0]q;

always@(posedge clk)
begin
if(rst==1)
begin
q=0;
end
else
begin
q=d;
end
end
endmodule

////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:07:00 01/29/2014
// Design Name: filterfir
// Module Name: D:/fft/floating_mul/tst.v
// Project Name: floating_mul
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: filterfir
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tst;
// Inputs
reg clk;
reg rst;

reg [7:0] x;
// Outputs
wire [9:0] dataout;
// Instantiate the Unit Under Test (UUT)
filterfir uut (
.clk(clk),
.rst(rst),
.x(x),
.dataout(dataout)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
x = 0;
#100;
rst = 1;
#100;
rst = 0;
x = 8'd5;
#100;
x = 8'd10;
#100;
x = 8'd12;
#100;
x = 8'd15;
#100;
x = 8'd16;
#100;

end
always begin #50 clk=~clk; end
endmodule

modulefir_filter(
inputclock,
inputreset,
inputwire[15:0]input_sample,
outputreg[15:0]output_sample);

parameterN=13;
regsigned[15:0]coeffs[12:0];
reg[15:0]holderBefore[12:0];
wire[15:0]toAdd[12:0];

always@(*)
begin
coeffs[0]=6375;
coeffs[1]=1;
coeffs[2]=3656;
coeffs[3]=3;
coeffs[4]=4171;
coeffs[5]=4;
coeffs[6]=28404;
coeffs[7]=4;
coeffs[8]=4171;
coeffs[9]=3;
coeffs[10]=3656;
coeffs[11]=1;
coeffs[12]=6375;
end

genvari;

generate
for(i=0;i<N;i=i+1)
begin:mult
multipliermult1(
.dataa(coeffs[i]),
.datab(holderBefore[i]),
.result(toAdd[i]));
end
endgenerate

always@(posedgeclockorposedgereset)
begin
if(reset)
begin
holderBefore[12]<=0;
holderBefore[11]<=0;
holderBefore[10]<=0;
holderBefore[9]<=0;
holderBefore[8]<=0;
holderBefore[7]<=0;

holderBefore[6]<=0;
holderBefore[5]<=0;
holderBefore[4]<=0;
holderBefore[3]<=0;
holderBefore[2]<=0;
holderBefore[1]<=0;
holderBefore[0]<=0;
output_sample<=0;
end
else
begin
holderBefore[12]<=holderBefore[11];
holderBefore[11]<=holderBefore[10];
holderBefore[10]<=holderBefore[9];
holderBefore[9]<=holderBefore[8];
holderBefore[8]<=holderBefore[7];
holderBefore[7]<=holderBefore[6];
holderBefore[6]<=holderBefore[5];
holderBefore[5]<=holderBefore[4];
holderBefore[4]<=holderBefore[3];
holderBefore[3]<=holderBefore[2];
holderBefore[2]<=holderBefore[1];
holderBefore[1]<=holderBefore[0];
holderBefore[0]<=input_sample;
output_sample<=(input_sample+toAdd[0]+toAdd[1]+
toAdd[2]+toAdd[3]+toAdd[4]+toAdd[5]+
toAdd[6]+toAdd[7]+toAdd[8]+toAdd[9]+
toAdd[10]+toAdd[11]+toAdd[12]);
end
end

endmodule

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