FAN7602B Green Current-Mode PWM Controller: Features Description

FAN7602B
Green Current-Mode PWM Controller

Features
Description
Green Current-Mode PWM Control
The FAN7602B is a green current-mode PWM controller.

It is specially designed for off-line adapter applications;
DVDP, VCR, LCD monitor applications; and auxiliary
power supplies.
Fixed 65kHz Operation

Internal High-Voltage Start-up Switch
Burst-Mode Operation
Line Voltage Feedforward to Limit Maximum Power
Line Under-Voltage Protection
Latch Protection & Internal Soft-Start (10ms) Function
Overload Protection
Over-Voltage Protection
The internal high-voltage start-up switch and the burstmode operation reduce the power loss in standby mode.
As a result, it is possible to supply 0.5W load, limiting the
input power under 1W when the input line voltage is
265VAC. On no-load condition, input power is under 0.3W.
The maximum power can be limited constantly, regardless of the line voltage change, using the power limit
function.
Low Operation Current: 1mA Typical

8-pin DIP/SOP
The switching frequency is internally fixed at 65kHz.
Applications
The FAN7602B includes various protections for the system reliability and the internal soft-start prevents the output voltage over-shoot at start-up.
Adapter
LCD Monitor Power
Auxiliary Power Supply
Related Application Notes

AN6014 - Green Current Mode PWM Controller
FAN7602
Ordering Information
Part Number
Operating Temp.
Range
Pb-Free
-25C to +125C
Yes
FAN7602BN
FAN7602BM
FAN7602BMX
2007 Fairchild Semiconductor Corporation

FAN7602B Rev. 1.0.0
Package
Packing Method
Marking
Code
8-DIP
Rail
FAN7602B
Rail
FAN7602B
Tape & Reel
FAN7602B
8-SOP
www.fairchildsemi.com
FAN7602B Green Current-Mode PWM Controller
March 2007
Typical Application Diagram
FAN7602B
Figure 1. Typical Flyback Application
Internal Block Diagram

VSTR
8
6 VCC
LUVP
LUVP
OLP
2V/1.5V
OVP
Latch
OVP
Auto Restart
Protection
SS End
Latch
Protection
Reset
Circuit
5V Ref
12V/8V
UVLO
VCC
SS End
10ms
Soft Start
19V
Driver
Circuit
PWM
Block
5 OUT
Plimit
Offset
65kHz clock
3 CS/FB
Delay
Circuit
Latch/
Plimit
0.95V/0.88V
Latch
PWM+
OLP
4V
Plimit
Offset
Plimit
Offset
Generator
Soft
Start
Power Limit
Plimit
Offset
OLP
Soft
Start
4 GND
Figure 2. Functional Block Diagram of FAN7602B

FAN7602B Rev. 1.0.0
2
VSTR
NC
VCC
Out
FAN7602B
YWW
1
LUVP
Latch/
Plimit
CS/FB
GND
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
LUVP
Line Under-Voltage Protection Pin. This pin is used to protect the set when the
input voltage is lower than the rated input voltage range.
Latch/Plimit
Latch Protection and Power Limit Pin. When the pin voltage exceeds 4V, the latch
protection works; the latch protection is reset when the VCC voltage is lower than 5V.
For the power limit function, the OCP level decreases as the pin voltage increases.
CS/FB
Current Sense and Feedback Pin. This pin is used to sense the MOSFET current
for the current mode PWM and OCP. The output voltage feedback information and
the current sense information are added using an external RC filter.
GND
Ground Pin. This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated.
OUT
Gate Drive Output Pin. This pin is an output pin to drive an external MOSFET. The
peak sourcing current is 450mA and the peak sinking current is 600mA. For proper
operation, the stray inductance in the gate driving path must be minimized.
VCC
Supply Voltage Pin. IC operating current and MOSFET driving current are supplied
using this pin.
NC
No Connection.
VSTR
Start-up Pin. This pin is used to supply IC operating current during IC start-up. After
start-up, the internal JFET is turned off to reduce power loss.

FAN7602B Rev. 1.0.0
3
Pin Assignments
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only.
Symbol
VCC
Parameter
Supply Voltage
Value
Unit
20
IOH, IOL
Peak Drive Output Current
+450/-600
mA
VCS/FB
CS/FB Input Voltage
-0.3 to 20
VLUVP
LUVP Input Voltage
-0.3 to 10
VLatch
Latch/Plimit Input Voltage
-0.3 to 10
VSTR
VSTR Input Voltage
600
TJ
Operating Junction Temperature
150
TA
Operating Temperature Range
-25 to 125
Storage Temperature Range
-55 to 150
Power Dissipation
1.2
VESD_HBM
ESD Capability, Human Body Model
2.0
kV
VESD_MM
ESD Capability, Machine Model
200
VESD_CDM
ESD Capability, Charged Device Model
500
TSTG
PD
Thermal Impedance
Symbol
JA
Parameter
Thermal Resistance, Junction-to-Ambient
8-DIP
Value
Unit
100
C/W
Note:
1. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.

FAN7602B Rev. 1.0.0
4
Absolute Maximum Ratings
VCC = 14V, TA = -25C~125C, unless otherwise specified
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
VSTR = 30V, TA = 25C
0.7
1.0
1.4
mA
START UP SECTION
ISTR
VSTR Start-up Current
UNDER VOLTAGE LOCK OUT SECTION

Vth(start)
Start Threshold Voltage
VCC increasing
11
12
13
Vth(stop)
Stop Threshold Voltage
VCC decreasing
HY(uvlo)
UVLO Hysteresis
3.6
4.0
4.4
SUPPLY CURRENT SECTION

ISTR
Start-up Supply Current
TA = 25C
250
320
ICC
Operating Supply Current
Output no switching
1.0
1.5
mA
10
15
ms
VCS/FB = 0.2V, TA = 25C
59
65
73
kHz
TA = 25C
0.9
1.0
1.1
100
150
ns
75
80
SOFT-START SECTION
tSS
Soft-Start Time(1)
PWM SECTION
fOSC
VCS/FB1
Operating Frequency
CS/FB Threshold Voltage
tD
Propagation Delay to
DMAX
Maximum Duty Cycle
DMIN
Minimum Duty Cycle
Output(1)
70
BURST MODE SECTION

VCS/FB2
Burst On Threshold Voltage
TA = 25C
0.84
0.95
1.06
VCS/FB3
Burst Off Threshold Voltage
TA = 25C
0.77
0.88
0.99
VLatch/Plimit = 2V, TA = 25C
0.12
0.16
0.20
11.5
12.0
14.0
POWER LIMIT SECTION

KPlimit
Offset Gain
OUTPUT SECTION
VOH
Output Voltage High
TA = 25C, Isource = 100mA
VOL
Output Voltage Low
TA = 25C, Isink = 100mA
1.0
2.5
tR
Rising
Time(1)
TA = 25C, CL = 1nF
45
150
ns
Falling
Time(1)
TA = 25C, CL= 1nF
35
150
ns
3.6
4.0
4.4
20
22
24
ms
30
37
44
ms
0.1
tF
PROTECTION SECTION
VLatch
tOLP
tOLP_ST
VOLP
Latch Voltage
Overload Protection Time
(1)
Overload Protection Time at Startup

Overload Protection Level
VLUVPoff
Line Under-Voltage Protection On

to Off
TA = 25C
1.9
2.0
2.1
VLUVPon
Line Under-Voltage Protection Off

to On
TA = 25C
1.4
1.5
1.6
Over-Voltage Protection
TA = 25C
18
19
20
VOVP
Note:
1. These parameters, although guaranteed by design, are not tested in production.

FAN7602B Rev. 1.0.0
5
Electrical Characteristics
8.8
12.4
8.4
VTL[V]
VTH[V]
12.8
12.0
8.0
11.6
7.6
11.2
7.2
-25
25
50
75
100
-25
125
25
50
75
100
125
Temperature [C]
Temperature [C]
Figure 4. Start Threshold Voltage vs. Temp.
Figure 5. Stop Threshold Voltage vs. Temp.
4.4
350
4.2
300
4.1
Ist [A]
UVLO Hysteresis [V]
4.3
4.0
250
3.9
3.8
200
3.7
3.6
-25
25
50
75
100
150
-25
125
Temperature [C]
25
50
75
100
125
Temperature [C]
Figure 6. UVLO Hysteresis vs. Temp.
Figure 7. Start-up Supply Current vs. Temp.
1.5
1.3
1.4
1.2
Istr [mA]
Iop [mA]
1.3
1.2
1.1
1.1
1.0
1.0
0.9
0.9
0.8
-25
25
50
75
100
0.8
-25
125
Temperature [C]
25
50
75
100
125
Temperature [C]
Figure 9. VSTR Star-up Current vs. Temp.
Figure 8. Operating Supply Current vs. Temp.

FAN7602B Rev. 1.0.0
6
Typical Performance Characteristics
70
1.10
CSFB2
CSFB3
68
1.00
Fosc [kHz]
CS/FB Threshold [V]
1.05
0.95
0.90
0.85
0.80
66
64
62
0.75
0.70
-25
25
50
75
100
60
-25
125
Temperature [C]
75
100
125
Figure 11. Operating Frequency vs. Temp.
0.20
80
0.18
78
Dmax [%]
Kplimit
50
Temperature [C]
Figure 10. Burst On/Off Voltage vs. Temp.
0.16
0.14
0.12
76
74
72
0.10
-25
25
50
75
100
70
-25
125
Temperature [C]
25
50
75
100
125
Temperature [C]
Figure 12. Offset Gain vs. Temp.
Figure 13. Maximum Duty Cycle vs. Temp.
4.4
20.0
19.6
4.2
VLATCH [V]
VOVP [V]
25
19.2
18.8
4.0
3.8
18.4
18.0
-25
25
50
75
100
3.6
-25
125
Temperature [C]
25
50
75
100
125
Temperature [C]
Figure 14. OVP Voltage vs. Temp.
Figure 15. Latch Voltage vs. Temp.

FAN7602B Rev. 1.0.0
7
Typical Performance Characteristics (Continued)
2.10
1.70
1.65
VLUVPon [V]
VLUVPoff [V]
2.05
2.00
1.60
1.55
1.50
1.95
1.45
1.90
-25
25
50
75
100
1.40
-25
125
Temperature [C]
25
50
75
100
125
Temperature [C]
Figure 16. LUVP On-to-Off Voltage vs. Temp.
CSFB1 Threshold voltage [V]
Figure 17. LUVP Off-to-On Voltage vs. Temp.
1.08
1.04
1.00
0.96
0.92
-25
25
50
75
100
125
Temperature [C]
Figure 18. CS/FB Threshold Voltage vs. Temp.

FAN7602B Rev. 1.0.0
8
Typical Performance Characteristics (Continued)
1. Start-up Circuit and Soft Start Block
charging CF to adjust the offset voltage. If IFB is zero, CF

is discharged through RF and RS to lower offset voltage.
The FAN7602B contains a start-up switch to reduce the

power loss of the external start-up circuit of the conventional PWM converters. The internal start-up circuit
charges the VCC capacitor with 0.9mA current source if
the AC line is connected. The start-up switch is turned off
15ms after IC starts up, as shown in Figure 19. The softstart function starts when the VCC voltage reaches the
start threshold voltage of 12V and ends when the internal
soft-start voltage reaches 1V. The internal start-up circuit
starts charging the VCC capacitor again if the Vcc voltage
is lowered to the minimum operating voltage, 8V. The
UVLO block shuts down the output drive circuit and
some blocks to reduce the IC operating current and the
internal soft-start voltage drops to zero. If the VCC voltage reaches the start threshold voltage, the IC starts
switching again and the soft-start block works as well.
Figure 21 shows typical voltage waveforms of the CS/FB

pin. The current-sense waveform is added to the offset
voltage, as shown in Figure 21. The CS/FB pin voltage is
compared with PWM+ that is 1V - Plimit offset. If the CS/
FB voltage meets PWM+, the output drive is shut off. If
the feedback offset voltage is low, the switch on time is
increased. If the feedback offset voltage is high, the
switch on time is decreased. In this way, the duty cycle is
controlled according to the output load condition. In general, the maximum output power increases as the input
voltage increases because the current slope during
switch on-time increases.
To limit the output power of the converter constantly, a
power-limit function is included. Sensing the converter
input voltage through the Latch/Plimit pin, the Plimit offset voltage is subtracted from 1V. As shown in Figure 21,
the Plimit offset voltage is subtracted from 1V and the
switch on-time decreases as the Plimit offset voltage
increases. If the converter input voltage increases, the
switch on-time decreases, keeping the output power
constant. The offset voltage is proportional to the Latch/
Plimit pin voltage and the gain is 0.16; if the Latch/Plimit
voltage is 1V, the offset voltage is 0.16V.
During the soft-start, the pulse-width modulated (PWM)

comparator compares the CS/FB pin voltage with the
soft-start voltage. The soft-start voltage starts from 0.5V
and the soft-start ends when it reaches 1V and the softstart time is 10ms. The start-up switch is turned off when
the soft-start voltage reaches 1.5V.
VCC
12V
8V
Vcc
Start-up
Current
1.5V
1V
0.5V
PWM
Comparator
PWM+
Soft Start
Voltage
Soft Start
Time (10ms)
Soft
Start
Plimit
Offset
RFB
Power
Limit
3
CS/FB
IFB
RF
Isw
CF
RS
5ms
Figure 19. Start-up Current and VCC Voltage
Figure 20. Current-Sense and Feedback Circuits
2. Oscillator Block
1V
Power Limit
Offset
PWM+
The oscillator frequency is set internally. The switching

frequency is 65kHz.
CS/FB
FB
Offset
3. Current Sense and Feedback Block

GND
The FAN7602B performs the current sensing for the current-mode PWM and the output voltage feedback with
only one pin, pin3. To achieve the two functions with one
pin, an internal leading edge blanking (LEB) circuit to filter the current-sense noise is not included because the
external RC filter is necessary to add the output voltage
feedback information and the current-sense information.
Figure 20 shows the current-sense and feedback circuits. RS is the current-sense resistor to sense the switch
current. The current-sense information is filtered by an
RC filter composed of RF and CF. According to the output
voltage feedback information, IFB charges or stops
1V
Power Limit
Offset
PWM+
CS/FB
GND
FB
Offset
On Time
(b) High-Power Limit Offset Case
Figure 21. CS/FB Pin Voltage Waveforms

FAN7602B Rev. 1.0.0
On Time
(a) Low-Power Limit Offset Case
9
Applications Information
voltage feedback loop is saturated, and the OLP initiates

if the LUVP condition persists more than 22ms.
The FAN7602B contains the burst-mode block to reduce

the power loss at a light load and no load. A hysteresis
comparator senses the offset voltage of the Burst+ for
the burst mode, as shown in Figure 22. The Burst+ is the
sum of the CS/FB voltage and Plimit offset voltage. The
FAN7602B enters burst mode when the offset voltage of
the Burst+ is higher than 0.95V and exits the burst mode
when the offset voltage is lower than 0.88V. The offset
voltage is sensed during the switch off time.
Vin
B u rs t+
LUVP
2V/1.5V
Figure 24. Line UVP Circuit

5.3 Latch Protection
The latch protection is provided to protect the system
against abnormal conditions using the Latch/Plimit pin.
The Latch/Plimit pin can be used for the output overvoltage protection and/or other protections. If the Latch/
Plimit pin voltage is made higher than 4V by an external
circuit, the IC is shut down. The latch protection is reset
when the VCC voltage is lower than 5V.
O ffs e t
D e la y
C irc u it
C S /F B
0 .9 5 V /0 .8 8 V
Figure 22. Burst-Mode Block
5. Protection Block
5.4 Over-Voltage Protection (OVP)

If the VCC voltage reaches 19V, the IC shuts down and
the OVP protection is reset when the VCC voltage is
lower than 5V.
The FAN7602B contains several protection functions to

improve system reliability.
5.1 Overload Protection (OLP)
The FAN7602B contains the overload protection function. If the output load is higher than the rated output current, the output voltage drops and the feedback error
amplifier is saturated. The offset of the CS/FB voltage
representing the feedback information is almost zero. As
shown in Figure 23, the CS/FB voltage is compared with
50mV reference when the internal clock signal is high
and, if the voltage is lower than 50mV, the OLP timer
starts counting. If the OLP condition persists for 22ms,
the timer generates the OLP signal. This protection is
reset by the UVLO. The OLP block is enabled after the
soft-start finishes.
6. Output Drive Block

The FAN7602B contains a single totem-pole output
stage to drive a power MOSFET. The drive output is
capable of up to 450mA sourcing current and 600mA
sinking current with typical rise and fall time of 45ns and
35ns, respectively, with a 1nF load.
Clock
OLP
3 CS/FB
22ms
Timer
Soft-Start
50mV
Figure 23. Overload Protection Circuit

5.2 Line Under-Voltage Protection
If the input voltage of the converter is lower than the minimum operating voltage, the converter input current
increases too much, causing component failure. Therefore, if the input voltage is low, the converter should be
protected. In the FAN7602B, the LUVP circuit senses the
input voltage using the LUVP pin and, if this voltage is
lower than 2V, the LUVP signal is generated. The comparator has 0.5V hysteresis. If the LUVP signal is generated, the output drive block is shut down, the output

FAN7602B Rev. 1.0.0
10
4. Burst-Mode Block
Application
Output Power
Input Voltage
Output Voltage
Adapter
48W
Universal input (85~265VAC)
12V
Features
Low stand-by power (<0.3W at 265VAC)
Constant output power control
Key Design Notes

All the IC-related components should be placed close to IC, especially C107 and C110.
If R106 value is too low, there can be subharmonic oscillation.
R109 should be designed carefully to make VCC voltage higher than 8V when the input voltage is 265VAC at no load.
R110 should be designed carefully to make VCC voltage lower than OVP when the input voltage is 85VAC at full load.
R103 should be designed to keep the MOSFET VDS voltage lower than maximum rating when the output is shorted.
1. Schematic
R206 C204
D202
D204
1 T1 12
C105
R103
C106
BD101
R114
Q101
6 D102 R109
R105
R106
ZD101
LF1
R101
C107
RT101
C101
FUSE
2 Latch/
Plimit
3
CS/FB
4
FAN7602B
R107
VSTR
LUVP
GND
NC
VCC
Out
OP1
R202
R201
R113
1
C222
R102
C110
R110
C109
C103 C104
C102
C202
C201
D101
R112
L201
R204
1
R203 C203
7
6
R111
R104
IC201
2
R205
5
D103
IC101
AC INPUT
4
3
C108
R108
OP2
R207
2
ZD201
Figure 25. Schematic

FAN7602B Rev. 1.0.0
11
Typical Application Circuit
3mm
12
3mm
Np2
Ns
Np2
NVcc
Shield
Ns
Shield
Np1
Ns
3
5
Shield
Ns
Shield
NVcc
Np1
Figure 26. Inductor Schematic Diagram
3. Winding Specification
No
Pin (sf)
32
Np1
Wire
0.3
Turns
Winding Method
31
Solenoid Winding
0.9
Not Shorted
10
Solenoid Winding
0.9
Not Shorted
10
Solenoid Winding
31
Solenoid Winding
Insulation: Polyester Tape t = 0.03mm, 2 Layers

Shield
Copper Tape

12 9
Ns
0.65 3

Shield
Copper Tape

65
NVcc
0.2 1

21
Np2
0.3 2
Outer Insulation: Polyester Tape t = 0.03mm, 2 Layers
4. Electrical Characteristics
Pin
Specification
Remarks
Inductance
1-3
607H
100kHz, 1V
Inductance
1-3
15H
9 - 12 shorted
5. Core & Bobbin

Core: EER2828
Bobbin: EER2828
Ae(mm2): 82.1

FAN7602B Rev. 1.0.0
12
2. Inductor Schematic Diagram
Part
Value
Note
Part
Fuse
FUSE
1A/250V
5D-9
Resistor
R102,
R112
Note
Capacitor
NTC
RT101
Value
C101
220nF/275V
Box Capacitor
C102
150nF/275V
Box Capacitor
C103, C104
102/1kV
Ceramic
C105
150F/400V
Electrolytic
10M
1/4W
C106
103/630V
Film
R103
56k
1/2W
C107
271
Ceramic
R104
150
1/4W
C108
103
Ceramic
R105
1k
1/4W
C109
22F/25V
Electrolytic
R106
0.5
1/2W
C110
473
Ceramic
R107
56k
1/4W
C201, C202
1000F/25V
Electrolytic
R108
10k
1/4W
C203
102
Ceramic
R109
1/4W
C204
102
Ceramic
R110
1k
1/4W
C222
222/1kV
Ceramic
R111
6k
1/4W
R113
180k
1/4W
R114
50k
1/4W
R201
1.5k
1/4W
D101, D102
UF4007
Fairchild Semiconductor
R202
1.2k
1/4W
D103
1N5819
MOSFET
Q101
FQPF8N60C
Diode
R203
20k
1/4W
D202, D204
R204
27k
1/4W
ZD101, ZD201
FYPF2010DN Fairchild Semiconductor

1N4744
R205
7k
1/4W
BD101
KBP06
FairchildSemiconductor
R206
10
1/2W
R207
10k
TNR
1/4W
R101
471
IC
470V
Filter
IC101
FAN7602B
LF101
23mH
0.8A
IC201
KA431
L201
10H
4.2A
OP1, OP2
H11A817B

FAN7602B Rev. 1.0.0
13
6. Demo Circuit Part List
7. PCB Layout
Minimize leakage
inductance
DC
Link
Minimize loop area
Pulsating high current
VSTR
NC
VCC
Out
LUVP
Latch/
Plimit
CS/FB
GND
FAN7602B
YWW
Separate power
and signal ground
Place these cap.
close to IC
Signal level low current
Figure 27. PCB Layout Recommendations for FAN7602B
8. Performance Data
85VAC
110VAC
220VAC
265VAC
Input Power at No Load
105.4mW
119.8mW
184.7mW
205.5mW
Input Power at 0.5W Load
739.4mW
761.4mW
825.4mW
872.2mW
OLP Point
4.42A
4.66A
4.60A
4.40A

FAN7602B Rev. 1.0.0
14
Mechanical Dimensions
8-DIP
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 28. 8-Lead Small Dual In-line Package (DIP)

FAN7602B Rev. 1.0.0
15
Mechanical Dimensions (Continued)

8-SOP
Dimensions are in millimeters unless otherwise noted.
Figure 29. 8-Lead Small Outline Package (SOP)

FAN7602B Rev. 1.0.0
16
ACEx
Across the board. Around the world.
ActiveArray
Bottomless
Build it Now
CoolFET
CROSSVOLT
CTL
Current Transfer Logic
DOME
2
E CMOS
EcoSPARK
EnSigna
FACT Quiet Series
FACT
FAST
FASTr
FPS
FRFET
GlobalOptoisolator
GTO
Programmable Active Droop
QFET
QS
QT Optoelectronics
Quiet Series
RapidConfigure
RapidConnect
ScalarPump
SMART START
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This datasheet contains the design specifications for product

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Rev. I24

FAN7602B Rev. 1.0.0
17
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FAN7602B Green Current-Mode PWM Controller: Features Description

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Document Informationclick to expand document informationFAN7602B is a green current-mode PWM controller. It is specially designed for off-line adapter applications; DVDP, VCR, LCD monitor applications; and auxiliary power supplies.

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FAN7602B

Green Current-Mode PWM Controller

Green Current-Mode PWM Control

The FAN7602B is a green current-mode PWM controller.

Fixed 65kHz Operation

Low Operation Current: 1mA Typical

The switching frequency is internally fixed at 65kHz.

Related Application Notes

2007 Fairchild Semiconductor Corporation

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