Application Note, V 1.

2, Feb 2002

SPI interface and use in a

daisy-chain bus
configuration

by Hannes Estl

Automotive Power
Never stop
-1-

thinking.

SPI interface used in a daisy-chain

1. Abstract
This Application Note describes the basic
principle of the Serial Peripheral Interface (SPI)
used in many Smart Power ICs and the different
ways in which it can be used for communication
with different ICs. The "daisy chain" bus
configuration will be described in detail.

2. Introduction
Complex integrated Smart Power devices can
not only control (turn on/off) the power output
stages, they can also provide configurable
functions and detailed diagnostic of various fault
conditions. To handle all this by direct control
lines or hardwired configuration would mean a
lot of external components and pins. To
increase functionality and at the same time
reduce the amount of additional components a
Serial Peripheral Interface is integrated in
modern Smart Power ICs. This SPI is a
synchronous serial bus interface for receiving
and sending data. If more than one IC with SPI
is controlled by, e.g., a C there are different
ways to connect them, depending on the
requirements of the application.

3. The SPI
3.1.

General

The SPI is a synchronous serial interface for

control and data transfer between a master and
several slaves. The interface consists of 4
ports:

CLK
SI
CS
SO

Serial Peripheral
Interface (SPI)

Serial Clock (CLK): Input for the master clock

signal. The clock signal determines the speed
of the data transfer and all receiving and
sending is done synchronous (clocks the
internal SPI shift register and the output driver)
to this signal.
Chip Select (CS):
CS activates the SPI
interface. As long as CS is high, the IC will not
accept the clock signal or data and the output
SO is in tristate. Whenever the pin is in a logic
low state, data can be transferred from the C
and vice versa (low active signal).
Serial Input (SI): Serial input port of the SPI
shift register. SI information is read in on the
rising edge of CLK into the internal shift register.
On the rising edge of the CS the input data is
latched into the internal registers of the logic.
Serial output (SO): Serial output port of the
SPI shift register. Diagnostic data bits are
shifted out serially at this pin. SO is in a high
impedance state until the CS pin goes to a logic
low state. New diagnostic data will appear at the
SO pin following the falling edge of CLK .
3.2.

Functional description

The "core" of the SPI is the shift register that is

used to receive the data from the C and to
write back the diagnostic information. This
register can be of different lengths (e.g. 8 Bit ).
Two basic concepts can be distinguished.
I.
The SPI is only using one shift register
that is connected serial to SI/SO and
parallel to the internal logic and
diagnostic registers of the IC.
II.
Two independent shift registers for
data-input (SI) and data-output (SO) are
used. Topology b) cannot be used in
daisy chain applications and will not be
Two basic SPI concepts
One common shift register

Two independant shift registers

internal logic registers

internal logic registers

Fig. 1: SPI

SI
SI

SO

n Bit SPI shift-register

diagnosis register

SO

n Bit SPI shift-register

n Bit SPI shift-register
diagnosis register

Fig. 2: Basic SPI register topologies

described here.
The second important topic the use in a daisychain configuration is the behavior of the SPI
while the input data is clocked in (CS=L).

Application Note

V1.2, 2002-02

SPI interface used in a daisy-chain

A) As long as CS is "low" the SPI register is
working as a simple shift register and
shifting through the SI data without
interpreting the different command and data
bits. When the CS goes back to "high" the
bits in the SPI register are interpreted and
the SPI logic is activated. Diagnostic
information is loaded when CS goes to low
and cannot be influenced in this write cycle.
B) The SPI logic does immediately checks
every incoming bit while CS is "low" (realtime arbitration). With this SPI configuration
the IC logic works (e.g. preparing special
output information) while the CS is low and
can therefore not be used in a daisy-chain
configuration. It is not possible to use the
SPI as a simple shift register.

CS = H


L :
diagnostic
information
is
transferred
(parallel) from the diagnostic register into
the SPI shift register.
serial input data can be clocked into the SPI
shift register.
SO changes from high impedance state to
logic high or low state corresponding to the
SO bits.
CLK

CS
SI

In the following document only SPI topology

I)+A) is described.
3.3.

Functional description

SO

0 1 0 1 1 0 1 1
0 1 0 1 1 0 1 1

Fig. 5: activate SPI, load diagnostic

LSB

MSB

CS = L : SPI is working like a shift register. With

each clock signal the actual state of the SI is
read into the SPI shift register and one
diagnostic bit is written out of SO.

internal logic registers

CS
SI

SO

n Bit SPI shift-register

Serial input
data MSB first

Serial output
(diagnosis) data
MSB first

CS

diagnosis register
LSB

MSB

CLK

Fig. 3: SPI functional blocks for topology I)+A)

CS = H : Any signals at the CLK and SI pins are
ignored and SO is in high impedance state.

low
CS
SI
011

CLK

11011

SO

0 1 1 0 0 0 1 0
0 1 0 1 1 0 1 1

Fig. 6: SPI active; reading and writing data

internal logic of the IC

high

CS = L


H:
transfer of SI bits from SPI shift register into
the internal logic registers
reset of diagnostic register (optional)
SO goes back to tristate

CS
SI
nBit SPI shift register

SO

internal registers
e.g. diagnosis register

To avoid any false clocking the serial clock input

pin SCLK should be logic low during high to low
transition of CS.

tristate

Fig. 4: SPI passive while CS = H

Application Note

V1.2, 2002-02

SPI interface used in a daisy-chain

4.2.

CLK

CS
SI

0 1 1 0 1 1 0 0
0 1 1 0 1 1 0 0

SO

Reset

Fig. 7 : SPI deactivated, process data, (optional:

reset diagnostic)

SPI Bus with several slave ICs

To reduce the number of needed driver ports,

the ICs and one SPI master can be connected
to a common bus. In this configuration the
master and all controlled ICs share the same
datalines (SO resp. SI) and clock line (CKL).
Variant a): The addressing of a single IC is
done by an individual chip select line. Only one
chip at the time can be active, but with the full
SPI bandwidth.
CLK
CLK
Tx a

This is the basic concept of a serial peripheral

interface using one central shift register. For the
use in a daisy-chain different functions can be
added to increase the functionality or to grant a
safe data transfer, but they always follow this
basic principle.

CS

Output lines

SI
Tx 1

SO

Rx 1

CLK
Tx b

CS

Output lines

SI

4. Possible Bus concepts with

SPI

SO

Number of addressed ICs = n

Number of necessary control and data ports = 3 + n
Individual ICs are addressed by the Chip Select

4.1.

Independent individual control

Each IC with an SPI is controlled individually

and independently by an SPI master, as in a bidirectional pointtopoint communication.

Variant b) of this bus configuration is described

in Fig. 10. Here all ICs also share the same
CS line.

CLK

CLK
SPI 1

Fig. 9:Individual Chip select and

common data lines for all ICs (B)

CLK

Tx a1

CS

Tx a2

SI

Rx a1

SO

CLK

Output lines
Tx a

CS

Output lines

SI
Tx 1

SO

Rx 1
CLK

CLK
SPI n

Tx b1

CS

Tx b2

SI

Rx b1

SO

Output lines

CLK
CS
SI

Number of addressed ICs = n

Output lines

SO

Number of necessary control and data ports = 4 n

Individual ICs are addressed by the Chip Select

Number of addressed ICs = n

Fig. 8: Individual independent

control of each IC with SPI (A)

Number of necessary control and data ports = 4

Individual ICs are addressed by the command word

The port requirements for this topology are the

greatest, because for each controlled IC an
individual SPI at the C is needed (CLK, CS; SI;
SO). All ICs can be addressed simultaneously
with the full SPI bandwidth.

Application Note

Fig. 10:Common SPI bus all ICs (C)

Addressing of a single chip is done by the first
bits of the command word. This topology is only
possible if all ICs check the command word
during writing (arbitration) and SO remains in
tristate until the addressing is over. ICs used in
V1.2, 2002-02

SPI interface used in a daisy-chain

such a bus configuration cannot be used in a
"daisy-chain" configuration and vice versa. Only
one chip a time can be active and SPI
bandwidth is reduced because of the address
bits.
4.3.

Daisy-chain configuration

The connection of different ICs and a C as

shown in Fig 11 is called a daisy-chain. For this
type of bus-topology only one SPI interface of
the C for two or more ICs is needed.

CLK
CS

Tx 1

SI

Rx 1

SO

max total dataate [Mbit/s]

data rate/
IC [Mbit/s]

usable bits/
IC

4*n=16
n+3=7
4
4

n*5=20
5
5
5/4=1,25

5
5
5
5/n=1,25

16
16
16-address
16

5. Basics of a daisy-chain:
For applications where fast accessibility of a
single IC is not critical and where high switching
frequencies are not necessary, the daisy-chain
is a bus concept that can drastically reduce the
number of needed C ports and wiring effort. If
the individual ICs use an SPI as described in
3.3. only then they can be connected in a daisychain configuration (Fig. 12)

CLK

Tx a

A
B
C
D

C I/O
Ports

Output lines

CLK

5V
CS
SI

5V

Output lines
Fault

SO

Number of addressed ICs = n

Number of necessary control and data ports = 4

SPI

All ICs are addressed by the common Chip Select

Fig. 11 SPI bus all ICs in a "daisychain" configuration (D)

All ICs share the same clock and chip select
port of the SPI master. That is all ICs are active
and addressed simultaneously. In contrary to a
"classical" bus, the SO and the SI lines are not
connected together. The Data Out of the C is
connected only to the SI of the first IC in the
line. Each SO of an IC is connected to the SI of
the next IC in the line and the SO of the last IC
is then connected to the Data In of the C. All
data lines form a closed chain for the data
transfer with the individual ICs as chain links.
The price for the low wiring effort is the reduced
communication frequency because in one write
cycle the data for all ICs in the daisy-chain had
to be transferred
4.4.

Vs

Listing of the 4 concepts

The following table provides a comparison for n

(4) ICs that are controlled by a 4Mhz SPI (all 4
have a 16Bit SPI and the same priority).

CS
CLK
SI
SO

Reset
PRG

IN 1

IN 4 TLE 6220 GP
CS
OUT 1
CLK
SI
SO
OUT 4
GND

5V
Vs

Fault

Reset

IN 1
IN 4

TLE 6236 G

CS
CLK
SI
SO

OUT 1

GND

OUT 8

5V
Fault

Vs

Reset

IN 1

PRG

IN 8 TLE 6240 GP
CS
OUT 1
CLK
SI
SO
OUT 16
GND

Fig. 12 SPI bus for 3 ICs in a "daisychain" configuration

In the daisy chain configuration, all ICs are
addressed by the same chip select and receive
clock signals from the same clock. They all
work synchronously.

Application Note

V1.2, 2002-02

SPI interface used in a daisy-chain

The C feeds the data and instruction bits into the SI of IC1 (first IC in the chain). The bits coming from
the SO of IC1 are directly shifted into the SI of IC2 and the bits coming from the SO of IC2 are directly
shifted into the SI of IC3. The SO bits of IC3 (last IC in the chain) are then returned to the C. As long as
the chip select is inactive (high) all three IC SPIs ignore the clock (CLK) and input signals (SI) and all
outputs (SO) are in tristate.

At the chip select transition to active (high
low) the diagnostic data or the data requested in the
previous SPI cycle is loaded into the SPI shift register.

As long as the chip select is active the SPI register works as a simple shift register. With each clock
signal one input bit is shifted into the SPI register (SI), each bit in the shift register moves one position
further within the register, and the last bit in the SPI shift register is shifted out of SO. This continues as
long as the chip select is active and clock signals are applied. For example after 11 clock cycles 11
diagnostic bits of IC3 have been returned to the C. The diagnostic word of IC2 is in the middle of the
shift register of IC3 and the diagnostic word of IC1 is half in IC2 and half in IC3. The command and data
word for IC3 is partly in IC2 and IC1.

After 26 clock cycles the diagnostic information of IC3 and IC2 has been fully returned to the C, the
diagnostic information of IC1 is still partly in the shift register of IC3. The command words for all 3 ICs
are "in-between" the different SPIs.

After 32 clock cycles (8 + 8 + 16) all the diagnostic information had been returned to the C and the
correct command and data bits are in the shift register of the respective ICs. With the chip select
transition from active to inactive (low
high) all the data that is actually in the SPI shift register is loaded
into the internal logic and processed. Now the IC will react to the commands and data, SI and CLK will
not accept input signals, and SO will change to tristate.

Application Note

V1.2, 2002-02

SPI interface used in a daisy-chain

This example also shows the danger of a invalid
number of clock cycles. If in this preceding not
exactly 32 clock signals are sent the data
loaded into the logic of the ICs will be not valid
and can cause problems, especially if the bits in
the SPI shift register accidentally "look like" a
valid command. Unwanted behaviour of the IC
can be the result. To avoid such an unwanted
behavior (e.g. caused by a spike on the clock
line or wrong number of clock cycles) a "modulo
counter" can be added to the SPI. Then the SPI
will accept and process input data (at the rising
CS edge) only if the number of clock signals
was a integer multiple of the modulo counter
(e.g. 8 or 16). To work in a daisy-chain
configuration the C must send and receive x
bits (x = sum of SPI bit-length of each IC in the
daisy-chain; in case 32) in a row without
changing the CS signal. The command and
data for the last IC in the chain (IC3 in the
example) must be the first in the bitstream from
the C, while the command and data for the first
IC (IC1) must be the last. The C will receive
the diagnostic bits from the last IC in the chain
(IC3) first, and the diagnostic bits from the first
IC last.

6. Application example:
Daisy-chain with 3 Smart Multichannel Lowside
Switches
1x TLE 6240GP
1x TLE 6220GP
1x TLE 6236G
C
TD

SI

TLE 6220 GP
IC1

SO

5
control
0
1

3
1

2
0

1
data
0

LSB
1

The previous command was

MSB
0

5
control
0
1

3
1

2
0

1
data
0

LSB
0

The diagnostic the IC will send back looks like:

MSB 6
Ch 4
1
1

4
Ch 3
0

3
1

2
Ch 2
1

1
1

LSB
Ch 1
1
1

IC2 : TLE6236G
The TLE6236G is a 8-channel, 2,3 Smart
Power Switch with 8-bit SPI for control and
diagnostic. In addition the IC has 4 parallel
inputs for control of the power stages 1 to 4. In
this example channels 1 to 4 and 7 should be
turned on, while channels 5, 6 and 8 should be
off. The load of channel 4 and 5 is shorted
(channel 4 was "on" in the previous cycle,
channel 5 was off), this means in the fault
register of channel 4 the fault condition short is
stored. No fault condition is stored in the
register of channel 5 because overload cannot
be detected in "off" state!.
The necessary command word is :
MSB
Ch 8
0

SO SI

TLE 6236 G
IC2

MSB
Ch 8
1
SO

8 Bit

6
Ch 7
1

5
Ch 6
0

4
Ch 5
0

3
Ch 4
1

2
Ch 3
1

1
Ch 2
1

LSB
Ch 1
1

TLE 6240 GP
IC3

SI

Fig. 13 Daisy-chain with 3 ICs (8Bit + 8Bit

+16Bit)

IC1 : TLE6220GP
The TLE6220GP is a 4-channel, 400m Smart
Power Switch with 8-bit SPI for control and
diagnostic. In addition the IC has 4 parallel
inputs for control of the power stages. In this
example the channels 1 and 2 should be turned
on in "OR" mode (SPI bit and parallel input of
the corresponding channel are logical ORed),
channel 3 and 4 should be off in "OR" mode.
The load of channel 3 is disconnected and the

6
Ch 7
1

5
Ch 6
0

4
Ch 5
0

3
Ch 4
1

2
Ch 3
1

1
Ch 2
1

LSB
Ch 1
0

2
D3
1

1
D2
1

LSB
D1
0

The actual diagnostic word is:

MSB
D8
1

16 Bit

Application Note

MSB

The previous command was:

8 Bit

RD

channel turned off in the previous cycle. This

means in the fault register of channel 3 Open
Load is stored. For this operation the following
command / data should be sent to IC1
(TLE6220GP).

6
D7
1

5
D6
0

4
D5
0

3
D4
0

Under normal operation of the channel, the

diagnostic bit of a channel has the same state
as the SPI input bit. In case of a fault the data
bit has the inverted state. The diagnostic
information always refers to the previous
command, not to the command actually sent!
IC2 : TLE6240GP
The TLE6240GP is a 16-channel, 1,3 /
400m Smart Power Switch with 16-bit SPI for
control and diagnostic. In addition, the IC has 8
parallel inputs for control of the power stages 1
to 4 and 9 to 12. In this example the diagnostic
for channels 1 to 8 should be requested (in the
previous command channel 1 to 4 was turned
on with Boolean "AND" and diagnostic
information for channel 1 to 8 was requested.
V1.2, 2002-02

SPI interface used in a daisy-chain

1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
1

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MSB

9
1

8
1

7
0

6
1
1
1
1
1

0
7
6
5

5
4
3
2
LSB 1

9 10 11 12 13 14 15
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1

0
0
0
0
0
0
0

Fig. 14
32 bit
downstream data

Application Note

6
5
4
3
2
0

For applications with slow or infrequent SPI data

transfer the daisy-chain is a Bus topology that
can reduce the communication I/O needs to 4
pins, independent of the number of addressed
ICs. The only requirement is a C that can send
and receive a bitstream of variable bit count
within one chip select cycle (according to the
SPI timings) .

7. Conclusion

5
4
3
2
1

These were the commands, data and diagnostic

how they are sent when only one chip is
addressed by SPI. In our example 3 ICs are
used in a daisy-chain. In this case the three
command / data words have to be lined up and
sent within one single chip select active cycle
with 32 clock signals (8 + 8 + 16). The
diagnostic info received will also be one single
queue with 32 bits of diagnostic data.
For this special application example with all the
above mentioned conditions the bitstream
showed in Feg.14 has to be sent to the first IC
(and in this way to the whole daisy-chain).

LSB
Ch 1
1
0

6
Ch 4

2
Ch 2

4
Ch 3

8
Ch 51

10
Ch 6
1
1

11

12
Ch 7
1
1

13

MSB 14
Ch 8
1
1

The actual-16 bit diagnostic word is:

LSB

3
Data

10

12
11
Command
1
0

13

14

MSB

The previous command was:

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MSB

LSB

3
Data

10

12
11
Command
0
0

The bitstream coming

from the last IC in the
chain (the diagnostic from
all ICs in the chain) looks
like this

13

LSB 1

14

MSB

For this special

application example with
all the previously
mentioned conditions the
following bitstream has to
be sent to the first IC (and
similarly to the whole
daisy-chain):
(x ... don't care)
9 10 11 12 13 14 15

Channels 5 to 16 are off). We assume that

channel 1 has an overload condition and
channel 5 an open load.
The necessary 16-bit command / data word is :

Fig.15
32 bit
upstream data

V1.2, 2002-02

SPI interface used in a daisy-chain

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Edition 2000-07-14
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Published by Infineon Technologies
8

Application Note

V1.2, 2002-02