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    I. Digital Integrated Circuits - Logic Concepts A. Logic Fundamentals

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    manohar487
    This document describes the fundamentals of digital logic circuits. It discusses binary mathematics, basic logic gates like AND, OR, and XOR. It then covers topics like fan-in, fan-out, ideal vs real inverters, transfer characteristics of inverters, noise margins, propagation delay calculations and NMOS-resistor load inverter circuits. The document provides qualitative and quantitative explanations of these concepts with diagrams.

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    I. Digital Integrated Circuits - Logic Concepts A. Logic Fundamentals

    Uploaded by

    manohar487
    22 views11 pages
    This document describes the fundamentals of digital logic circuits. It discusses binary mathematics, basic logic gates like AND, OR, and XOR. It then covers topics like fan-in, fan-out, ideal vs real inverters, transfer characteristics of inverters, noise margins, propagation delay calculations and NMOS-resistor load inverter circuits. The document provides qualitative and quantitative explanations of these concepts with diagrams.

    Original Description:

    dgital ics

    Original Title

    S98_Lecture11

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    This document describes the fundamentals of digital logic circuits. It discusses binary mathematics, basic logic gates like AND, OR, and XOR. It then covers topics like fan-in, fan-out, ideal vs real inverters, transfer characteristics of inverters, noise margins, propagation delay calculations and NMOS-resistor load inverter circuits. The document provides qualitative and quantitative explanations of these concepts with diagrams.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    22 views11 pages

    I. Digital Integrated Circuits - Logic Concepts A. Logic Fundamentals

    Uploaded by

    manohar487
    This document describes the fundamentals of digital logic circuits. It discusses binary mathematics, basic logic gates like AND, OR, and XOR. It then covers topics like fan-in, fan-out, ideal vs real inverters, transfer characteristics of inverters, noise margins, propagation delay calculations and NMOS-resistor load inverter circuits. The document provides qualitative and quantitative explanations of these concepts with diagrams.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 11

    I.

    Digital Integrated Circuits - Logic Concepts


    A. Logic Fundamentals:
    binary mathematics: only operate on 0 and 1 (Boolean algebra)
    simplest function -- inversion

    symbol for the inverter


    INPUT A OUTPUT Y
    A

    0
    1

    1
    0

    EECS 6.012 Spring 1998


    Lecture 11

    B. Other Logic Functions


    AND and NAND = not AND
    OR and NOR = not OR
    XOR
    INPUT
    A B

    A
    B

    A
    B

    AND

    0
    0
    1
    1

    NAND

    0
    1
    0
    1

    OUTPUT Y
    AND NAND
    0
    0
    0
    1

    1
    1
    1
    0

    (a)
    INPUT
    A
    B

    A
    B

    OR

    Y
    NOR

    0
    0
    1
    1

    0
    1
    0
    1

    OUTPUT Y
    NOR
    OR
    0
    1
    1
    1

    1
    0
    0
    0

    (b)
    INPUT
    A B
    A
    B

    0
    0
    1
    1

    0
    1
    0
    1

    OUTPUT Y
    XOR
    0
    1
    1
    0

    (c)

    One gate can have many inputs


    C

    ABCXYZ

    Practical limitations ... set by need to maintain both adequate


    switching speed and valid logic levels
    fan-in -- maximum number logic gates connected to the input
    fan-out -- maximum number of logic gates connected to the output

    EECS 6.012 Spring 1998


    Lecture 11

    C. An Ideal Inverter
    Let the logical variable be represented by a voltage.
    Let the 1 correspond to a high voltage (say, 5 V) and the 0
    correspond to the low voltage (say, 0 V).
    Voltage transfer curve for an inverter yields 0 V when a high voltage
    is input and the high voltage, V+, when a low voltage is input.
    VIN >VM = V+/ 2 --> VOUT = 0
    VIN < VM = V+/ 2 --> VOUT = V+

    The ideal inverter returns correct logical outputs (0 V or V+) even


    when the input voltage is corrupted by noise, voltage spikes, etc.
    which are nearly half the supply voltage!

    VOUT

    V+

    V+
    +

    VIN

    VOUT

    VOUT = VIN

    V +/2

    0
    0
    (a)

    VM =

    V+
    2
    (b)

    V+

    VIN

    EECS 6.012 Spring 1998


    Lecture 11

    D. Real Inverters
    Inverters which we can build are approximations to the ideal
    inverter. A typical inverter characteristic is:
    VOUT
    VMAX
    VOH
    = 1
    VM

    VOL
    VMIN
    0

    VIL

    VM

    VIH

    V+

    VIN

    On the output and input axes, several voltages are defined:


    VM = input voltage for which VOUT = VIN
    VOL = voltage output low = max. output voltage for a valid 0
    VOH = voltage output high = min. output voltage for a valid 1
    VIL = voltage input low = smaller input voltage where slope equals -1
    VIH = voltage input high = larger input voltage where slope equals -1
    VMAX = VOUT for VIN = 0 V; usually, VMAX = V+, the supply voltage
    VMIN = VOUT for VIN = V+ and is the minimum output voltage

    EECS 6.012 Spring 1998


    Lecture 11

    E. Inverter Transfer Function - Hand Calculations


    Problem: evaluating where slope = -1 is an algebraic mess.
    Adopt more convenient definitions of VM, VIL,VIH (new in H&S)
    VOUT
    VOH = VMAX
    Slope Av

    VM

    VOL = VMIN
    VIL

    VM

    VIH

    VIN

    Use small-signal model to evaluate tangent to transfer curve


    VOL = VMIN and VOH = VMAX
    VM = Input voltage VIN at which VOUT = VIN
    VIL = intersection of tangent to VOUT (VIN) curve at VM and the line
    VOUT = VMAX (= V+, typically)
    VIH = intersetion of tangent to VOUT(VIN) curve at VM and the line
    VOUT = VMIN (= 0 V, typically)
    If VIN <VIL, then VOUT is considered a valid 1
    If VIN >VIH, then VOUT is considered a valid 0

    EECS 6.012 Spring 1998


    Lecture 11

    F. Noise Margins
    Cascade of two logic inverters-- output of #1 is input to #2
    Output of inverter #1 is at least,VOH1
    Margin of VOH1 - VIH2 to spare before the input to inverter #2 has an
    invalid high input.

    NMH = VOH - VIH = noise margin (high)


    NML = VIL - VOL = noise margin (low)

    vNOISE
    1

    VOH1
    NMH

    VIH1
    Voltage

    VOH2

    VIL1

    VIH2
    VIL2

    VOL1

    NML

    VOL2

    NMH = VOH VIH


    NML = VIL VOL

    EECS 6.012 Spring 1998


    Lecture 11

    G. Propagation Delay
    Time is required for an inverter to change states from 0 to 1 and
    vice versa
    Charging and discharging MOSFET and parasitic capacitance
    VIN

    VOH

    90%
    50%
    10%
    0

    VOL

    tPHL

    VOUT

    tF

    tR

    tPLH
    VOH

    90%
    50%
    10%
    0

    tF

    VOL
    tR

    tCYCLE

    Definitions:tR = risetime; tF = falltime -- both 10% to 90% of total


    swing
    tPHL = delay between 50% points on the input and output waveforms
    during the high-to-low transition
    tPLH = delay between 50% points on the input and output waveforms
    during the low-to-high transition

    EECS 6.012 Spring 1998


    Lecture 11

    H. Propagation Delay - Hand Calculations


    For hand calculations, make the input waveform ideal
    Find delay in the output waveform before it reaches the 50% point.

    VIN
    VOH

    tCYCLE

    VOL
    t
    VOUT

    tPHL

    tPLH

    VOH

    VOH
    50%

    tCYCLE

    VOL
    t

    Transient analysis can only be roughly approximated in hand


    calculations
    SPICE is essential for accurate analysis.

    EECS 6.012 Spring 1998


    Lecture 11

    II. Inverter Circuits:

    NMOS-Resistor Load

    A. MOSFET is an excellent switch:


    open-circuit at control terminal (gate)
    drain-source connection is open for VGS < VTn (cutoff region)
    drain-source connection is a resistor for VGS >VTn (triode region)

    B. Qualitative Circuit Operation

    VDD

    VIN

    CL

    +
    VOUT
    _

    V+ = VDD = 5 V (typically)
    CL = load capacitance (from interconnections and from other
    inverters connected to the output
    VBS = 0 V -- bulk-to-source short circuit is typically not shown
    VIN < VTn MOSFET-OFF ---VOUT = VDD
    VIN >> VTn MOSFET - ON --- VOUT is small ( value is set by
    resistive divider)

    EECS 6.012 Spring 1998


    Lecture 11

    C. Quantitative Calculation of Transfer Characteristic


    Key concept: the static output current is zero
    MOSFET drain current = ID = IR = current through resistor

    V OUT
    V
    1
    DD
    = ----------------------------- = --------- --RV

    DD

    OUT

    Plotting these equations on the drain characteristics of the MOSFET


    since VDS = VOUT:

    ID

    VIN

    VDD
    R

    VDD

    VOUT

    The transfer characteristic can be found by plotting the intersections


    between the ID (VIN, VOUT) characteristics with the load line
    IR(VOUT)

    EECS 6.012 Spring 1998


    Lecture 11

    D. Transfer Characteristic
    VOUT
    V+
    VOH

    VM

    VOL
    VMIN
    0

    VIL

    VM

    VIH

    V+

    VIN

    E. Small Signal Model


    Use small signal model to calculate the gain vout/vin at VM
    Gain is the slope of the inverter transfer characteristic at VM
    Gain =vout/vin = -gm(ro || R) -gmR

    EECS 6.012 Spring 1998


    Lecture 11

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