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CMOS Interview Questions

This document contains 43 CMOS interview questions related to MOSFET operation, CMOS inverter design and characteristics, transistor sizing, noise margin, power dissipation, body effect, scaling effects, delay calculation, SRAM design including read/write operations and sense amplifier design, testing vs verification, latchup, sequential logic design, and other digital design topics. The questions cover topics from transistor-level circuit design to system-level concepts.

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679 views3 pages

CMOS Interview Questions

This document contains 43 CMOS interview questions related to MOSFET operation, CMOS inverter design and characteristics, transistor sizing, noise margin, power dissipation, body effect, scaling effects, delay calculation, SRAM design including read/write operations and sense amplifier design, testing vs verification, latchup, sequential logic design, and other digital design topics. The questions cover topics from transistor-level circuit design to system-level concepts.

Uploaded by

3nadhs
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Interview Questions


One Stop site for all the VLSI Interview Questions.

Monday, November 17, 2008

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CMOS Interview Questions


1. Explain why & how a MOSFET works
2. Draw Vds-Ids curve for a MOSFET. Now, show how this curve
changes (a) with increasing Vgs (b) with increasing transistor
width (c) considering Channel Length Modulation
3. Explain the various MOSFET Capacitances & their significance
4. Draw a CMOS Inverter. Explain its transfer characteristics
5. Explain sizing of the inverter
6. How do you size NMOS and PMOS transistors to increase the
threshold voltage?
7. What is Noise Margin? Explain the procedure to determine Noise
Margin
8. Give the expression for CMOS switching power dissipation
9. What is Body Effect?
10. Describe the various effects of scaling
11. Give the expression for calculating Delay in CMOS circuit
12. What happens to delay if you increase load capacitance?
13. What happens to delay if we include a resistance at the output
of a CMOS circuit?
14. What are the limitations in increasing the power supply to
reduce delay?
15. How does Resistance of the metal lines vary with increasing
thickness and increasing length?
16. You have three adjacent parallel metal lines. Two out of phase
signals pass through the outer two metal lines. Draw the
waveforms in the center metal line due to interference. Now, draw
the signals if the signals in outer metal lines are in phase with
each other
17. What happens if we increase the number of contacts or via
from one metal layer to the next?
18. Draw a transistor level two input NAND gate. Explain its sizing
(a) considering Vth (b) for equal rise and fall times
19. Let A & B be two inputs of the NAND gate. Say signal A arrives
at the NAND gate later than signal B. To optimize delay, of the two
series NMOS inputs A & B, which one would you place near the
output?
20. Draw the stick diagram of a NOR gate. Optimize it
21. For CMOS logic, give the various techniques you know to
minimize power consumption
22. What is Charge Sharing? Explain the Charge Sharing problem
while sampling data from a Bus
23. Why do we gradually increase the size of inverters in buffer
design? Why not give the output of a circuit to one large inverter?

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24. In the design of a large inverter, why do we prefer to connect


small transistors in parallel (thus increasing effective width) rather
than lay out one transistor with large width?
25. Given a layout, draw its transistor level circuit. (I was given a 3
input AND gate and a 2 input Multiplexer. You can expect any
simple 2 or 3 input gates)
26. Give the logic expression for an AOI gate. Draw its transistor
level equivalent. Draw its stick diagram
27. Why dont we use just one NMOS or PMOS transistor as a
transmission gate?
28. For a NMOS transistor acting as a pass transistor, say the gate
is connected to VDD, give the output for a square pulse input
going from 0 to VDD
29. Draw a 6-T SRAM Cell and explain the Read and Write
operations
30. Draw the Differential Sense Amplifier and explain its working.
Any idea how to size this circuit? (Consider Channel Length
Modulation)
31. What happens if we use an Inverter instead of the Differential
Sense Amplifier?
32. Draw the SRAM Write Circuitry
33. Approximately, what were the sizes of your transistors in the
SRAM cell? How did you arrive at those sizes?
34. How does the size of PMOS Pull Up transistors (for bit & bitlines) affect SRAMs performance?
35. Whats the critical path in a SRAM?
36. Draw the timing diagram for a SRAM Read. What happens if we
delay the enabling of Clock signal?
37. Give a big picture of the entire SRAM Layout showing your
placements of SRAM Cells, Row Decoders, Column Decoders, Read
Circuit, Write Circuit and Buffers
38. In a SRAM layout, which metal layers would you prefer for
Word Lines and Bit Lines? Why?
39. How can you model a SRAM at RTL Level?
40. Whats the difference between Testing & Verification?
41. For an AND-OR implementation of a two input Mux, how do
you test for Stuck-At-0 and Stuck-At-1 faults at the internal nodes?
(You can expect a circuit with some redundant logic)
42. What is Latch Up? Explain Latch Up with cross section of a
CMOS Inverter. How do you avoid Latch Up?
========================================
=======================
1. Give two ways of converting a two input NAND gate to an
inverter
2. Given a circuit, draw its exact timing response. (I was given a
Pseudo Random Signal Generator; you can expect any sequential
ckt)
3. What are set up time & hold time constraints? What do they
signify? Which one is critical for estimating maximum clock
frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle.

11/25/2014 3:48 PM

VLSI Interview Questions: CMOS Interview Questions

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http://vlsichip.blogspot.in/2008/11/cmos-interview-questions.html

(Hint: Double the Clock)


6. Suppose you have a combinational circuit between two registers
driven by a clock. What will you do if the delay of the
combinational circuit is greater than your clock signal? (You cant
resize the combinational circuit transistors)
7. The answer to the above question is breaking the combinational
circuit and pipelining it. What will be affected if you do this?
8. What are the different Adder circuits you studied?
9. Give the truth table for a Half Adder. Give a gate level
implementation of the same.
10. Draw a Transmission Gate-based D-Latch.
11. Design a Transmission Gate based XOR. Now, how do you
convert it to XNOR? (Without inverting the output)
12. How do you detect if two 8-bit signals are same?
13. How do you detect a sequence of "1101" arriving serially from
a signal line?
14. Design any FSM in VHDL or Verilog.
15. Explain RC circuits charging and discharging.
16. Explain the working of a binary counter.
17. Describe how you would reverse a singly linked list.

Posted by VLSI_Rules at 10:43 AM


Labels: analysis, asic, backend, buffer, chip, clock, cmos,
delay, design, layout, physical, routing, sta, synthesis,
timing, vlsi
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