SEQUENTIAL CIRCUITS

Kirti P_Didital Design

Introduction
The digital system consists of two types of circuits, namely
(i) Combinational circuits and
(ii) Sequential circuit
the logic circuits whose outputs at any instant of time depend on the
present inputs as well as on the past outputs are called sequential
circuits. In sequential circuits, the output signals are fed back to the
input side.

Kirti P_Didital Design

 A memory element is a medium in which one bit of information (0

or 1) can be stored or retained until necessary, and thereafter its
contents can be replaced by a new value.
The contents of memory elements can be changed by the outputs of
combinational circuits that are connected to its input.
Combinational circuits are often faster than sequential circuits since
the combinational circuits do not require memory elements whereas
the sequential circuit needs memory elements to perform its
operations in sequence.
Sequential circuits are broadly classified into two main categories,
known as synchronous or clocked and asynchronous or unclocked
sequential circuits, depending on the timing of their signals.

Kirti P_Didital Design

A sequential circuit whose behavior can be defined from the

knowledge of its signal at discrete instants of time is referred to as
a synchronous sequential circuit.
A sequential circuit whose behavior depends upon the sequence
in which the input signals change is referred to as an asynchronous
sequential circuit

Kirti P_Didital Design

FLIP-FLOPS
The basic 1-bit digital memory circuit is known as a flip-flop. It can
have only two states, either the 1 state or the 0 state. A flip-flop is
also known as a bistable multivibrator. Flip-flops can be obtained by
using NAND or NOR gates. The general block diagram
representation of a flip-flop is shown in Figure.

It has one or more inputs and two outputs. The two outputs are
complementary to each other. If Q is 1 i.e., Set, then Q' is 0; if Q is 0
i.e., Reset, then Q' is 1. That means Q and Q' cannot be at the same
state simultaneously.
Kirti P_Didital Design
5

Kirti P_Didital Design

Latch
We consider the fundamental circuit shown in Figure. It consists of
two inverters G1and G2 (NAND gates are used as inverters). The
output of G1 is connected to the input of G2 (A2) and the output of
G2 is connected to the input of G1 (A1).

Let us assume the output of G1 to be Q = 0, which is also the input

of G2 (A2 = 0). Therefore, the output of G2 will be Q' = 1, which
makes A1= 1 and consequently Q = 0 which is according to our
ssumption
Similarly, we can demonstrate that if Q = 1, then Q' = 0 and this is
also consistent with the circuit connections. Hence we see that Q and
7
Q' are always complementary.Kirti P_Didital Design

And if the circuit is in 1 state, it continues to remain in this state

and vice versa is also true. Since this information is locked or
latched in this circuit, therefore, this circuit is also referred to as a
latch.

In this circuit there is no way to enter the desired digital

information to be stored in it. To make that possible we have to
modify the circuit by replacing the inverters by NAND gates and
then it becomes a flip-flop.

Kirti P_Didital Design

TYPES OF FLIP-FLOPS
There are different types of flip-flops depending on how their inputs
and clock pulses cause transition between two states. viz., S-R, D, JK, and T. Basically D, J-K, and T are three different modifications of
the S-R flip-flop.
S-R (Set-Reset) Flip-fl op
An S-R flip-flop has two inputs named
Set (S) and Reset (R), and two outputs Q
and Q'. The outputs are complement of
each other, i.e., if one of the outputs is 0
then the other should be 1. This can be
implemented using NAND or NOR
gates.
Kirti P_Didital Design

S-R Flip-flop Based on NOR Gates

An S-R flip-flop can be constructed with NOR gates at ease by
connecting the NOR gates back to back as shown in Figure. The
cross-coupled connections from the output of gate 1 to the input of
gate 2 constitute a feedback path. This circuit is not clocked and is
classified as an asynchronous sequential circuit. The truth table for
the S-R flip-flop based on a NOR gate is shown in the table

Kirti P_Didital Design

10

Case 1. For S = 0 and R = 0, the flip-flop remains in its present state (Qn). It
means that the next state of the flip-flop does not change, i.e., Qn+1= 0 if Qn = 0
and vice versa.
First let us assume that Qn = 1 and Q'n = 0.
Thus the inputs of NOR gate 2 are 1 and 0, and therefore its output Q'n+1 = 0.
This output Q'n+1 = 0 is fed back as the input of NOR gate 1, thereby
producing a 1 at the output, as both of the inputs of NOR gate 1 are 0 and 0;
so Qn+1 = 1 as originally assumed
Kirti P_Didital Design

11

Case 2. The second input condition is S = 0 and R = 1. The 1 at R input forces

the output of NOR gate 1 to be 0 (i.e., Qn+1 = 0). Hence both the inputs of
NOR gate 2 are 0 and 0 and so its output Q'n+1 = 1. Thus the condition S = 0
and R = 1 will always reset the flip-flop to 0. Now if the R returns to 0 with S
= 0, the flip-flop will remain in the same state.
Case 3. The third input condition is S = 1 and R = 0. The 1 at S input forces
the output of NOR gate 2 to be 0 (i.e., Q'n+1 = 0). Hence both the inputs of
NOR gate 1 are 0 and 0 and so its output Qn+1 = 1. Thus the condition S = 1
and R = 0 will always set the flip-flop to 1. Now if the S returns to 0 with R =
0, the flip-flop will remain in the same state
Case 4. The fourth input condition is S = 1 and R = 1. The 1 at R input and 1
at S input forces the output of both NOR gate 1 and NOR gate 2 to be 0.
Hence both the outputs of NOR gate 1 and NOR gate 2 are 0 and 0; i.e., Qn+1
= 0 and Q'n+1= 0. Hence this condition S = 1 and R = 1 violates the fact that
the outputs of a flip-flop will always be the complement of each other. Since
the condition violates the basic definition of flip-flop, it is called the
undefined condition. Generally this condition must be avoided by making
sure that 1s are not applied simultaneously to both of the inputs.
Kirti P_Didital Design

12

Case 5. If case 4 arises at all, then S and R both return to 0 and 0

simultaneously, and then any one of the NOR gates acts faster than the other
and assumes the state. For example, if NOR gate 1 is faster than NOR gate 2,
then Qn+1 will become 1 and this will make Q'n+1= 0. Similarly, if NOR gate 2
is faster than NOR gate 1, then Q'n+1 will become 1 and this will make Qn+1 =
0. Hence, this condition is determined by the flip-flop itself. Since this
condition cannot be controlled and predicted it is called the indeterminate
condition.

Kirti P_Didital Design

13

S'-R' Flip-flop Based on NAND Gates

An S'-R' flip-flop can be constructed with
NAND gates by connecting the NAND
gates back to back as shown in Figure. The
operation of the S'-R' flip-flop can be
analyzed in a similar manner as that
employed for the NOR-based S-R flip-flop.
This circuit is also not clocked and is
classified as an asynchronous sequential
circuit. The truth table for the S'-R' flip-flop
based on a NAND gate is shown in the table
in Figure.

Kirti P_Didital Design

14

Case 1. For S' = 1 and R' = 1, the flip-flop remains in its present state (Qn). It
means that the next state of the flip-flop does not change, i.e., Qn+1= 0 if Qn
= 0 and vice versa. First let us assume that Qn =1 and Q'n = 0. Thus the
inputs of NAND gate 1 are 1 and 0, and therefore its output Qn+1= 1. This
output Qn+1 = 1 is fed back as the input of NAND gate 2, thereby producing
a 0 at the output, as both of the inputs of NAND gate 2 are 1 and 1; so Q'n+1=
0 as originally assumed.
Now let us assume the opposite case, i.e., Qn = 0 and Q'n = 1. Thus the
inputs of NAND gate 2 are 1 and 0, and therefore its output Q'n+1= 1. This
output Q'n+1 = 1 is fed back as the input of NAND gate 1, thereby producing
a 0 at the output, as both of the inputs of NAND gate 1 are 1 and 1; so Qn+1=
0 as originally assumed. Thus we find that the condition S' = 1 and R' = 1 do
not affect the outputs of the flip-flop, which means this is the memory
condition of the S'-R' flip-flop.
Case 2. The second input condition is S' = 1 and R' = 0. The 0 at R' input
forces the output of NAND gate 2 to be 1 (i.e., Q'n+1 = 1). Hence both the
inputs of NAND gate 1 are 1 and 1 and so its output Qn+1 = 0. Thus the
condition S' = 1 and R' = 0 will always reset the flip-flop to 0. Now if the R'
15
returns to 1 with S' = 1, the fl ip-fl Kirti
opP_Didital
willDesign
remain in the same state.

Case 3. The third input condition is S' = 0 and R' = 1. The 0 at S' input forces
the output of NAND gate 1 to be 1 (i.e., Qn+1 = 1). Hence both the inputs of
NAND gate 2 are 1 and 1 and so its output Q'n+1 = 0. Thus the condition S' =
0 and R' = 1 will always set the flip-flop to 1. Now if the S' returns to 1 with
R' = 1, the flip-flop will remain in the same state.
Case 4. The fourth input condition is S' = 0 and R' = 0. The 0 at R' input and 0
at S' input forces the output of both NAND gate 1 and NAND gate 2 to be 1.
Hence both the outputs of NAND gate 1 and NAND gate 2 are 1 and 1; i.e.,
Qn+1 = 1 and Q'n+1= 1. Hence this condition S' = 0 and R' = 0 violates the fact
that the outputs of a flip-flop will always be the complement of each other.
Since the condition violates the basic definition of a flip-flop, it is called the
undefined condition. Generally, this condition must be avoided by making
sure that 0s are not applied simultaneously to both of the inputs.

Kirti P_Didital Design

16

Case 5. If case 4 arises at all, then S' and R' both return to 1 and 1
simultaneously, and then any one of the NAND gates acts faster than the
other and assumes the state. For example, if NAND gate 1 is faster than
NAND gate 2, then Qn+1 will become 1 and this will make Q'n+1 = 0.
Similarly, if NAND gate 2 is faster than NAND gate 1, then Q'n+1 will
become 1 and this will make Qn+1= 0. Hence, this condition is determined by
the fl ip-fl op itself. Since this condition cannot be controlled and predicted
it is called the indeterminate condition.
Thus, comparing the NOR flip-flop and the NAND fl ip-fl op, we fi nd
that they basically operate in just the complement fashion of each other.
Hence, to convert a NAND-based S'-R' flip-flop into a NOR-based S-R
flip-flop, we have to place an inverter at each input of the flip-flop. The
resulting circuit is shown in Figure, which behaves in the same manner
as an S-R flip-flop

Kirti P_Didital Design

17

Kirti P_Didital Design

18

CLOCKED S-R FLIP-FLOP

Generally, synchronous circuits change their states only when clock
pulses are present. The operation of the basic flip-flop can be modified by
including an additional input to control the behaviour of the circuit.
Such a circuit is shown in Figure. The circuit shown in Figure consists of
two AND gates. The clock input is connected to both of the AND gates,
resulting in LOW outputs when the clock input is LOW.
In this situation the changes in S and R inputs will not affect the state (Q)
of the flip-flop.

Kirti P_Didital Design

19

On the other hand, if the clock input is HIGH, the changes in S and R
will be passed over by the AND gates and they will cause changes in
the output (Q) of the flip-flop.
This way, any information, either 1 or 0, can be stored in the flip-flop
by applying a HIGH clock input and be retained for any desired period
of time by applying a LOW at the clock input.
This type of flip-flop is called a clocked S-R flip-flop. Such a clocked SR flip-flop made up of two AND gates and two NOR gates is shown in
Figure.

Kirti P_Didital Design

20

Now the same S-R flip-flop can be constructed using the basic
NAND latch and two other NAND gates as shown in Figure

The logic symbol of the S-R flip-flop is shown in Figure. It has three
inputs: S, R, and CLK. The CLK input is marked with a small triangle.
The triangle is a symbol that denotes the fact that the circuit responds to
an edge or transition at CLK input
Kirti P_Didital Design

21

Kirti P_Didital Design

22

Preset and Clear

If Pr = 1 and Cr = 0, the output of NAND gate 4 is forced to be 1, i.e., Q'

= 1 and the flip-flop is reset, overwriting the previous state of the flip-flop.
If Pr = 0 and Cr = 1, the output of NAND gate 3 is forced to be 1, i.e., Q
= 1 and the flip-flop is set, overwriting the previous state of the flip-flop.
The condition Pr = Cr = 0 must not be applied, since this leads to an
Kirti P_Didital Design
23
uncertain state

The logic symbol of an S-R fl ip-fl op with Pr and Cr

inputs is shown in Figure. Here, bubbles are used for
Pr and Cr inputs, which indicate these are active low
inputs, which means that the intended function is
performed if the signal applied to Pr and Cr is LOW.
The operation of Figure. is shown in the table in
Figure. The circuit can be designed such that the
asynchronous inputs override the clock, i.e., the circuit
can be set or reset even in the presence of the clock
pulse.

Kirti P_Didital Design

24

Characteristic Table of an S-R Flip-flop

We know that the next state flip-flop output (Qn+1) depends on the present
inputs as well as the present output (Qn). So in order to know the next state
output of a flip-flop, we have to consider the present state output also. The
characteristic table of an S-R flip-flop is given in the table in Figure.

Kirti P_Didital Design

25

From the characteristic table we have to find out the characteristic

equation of the S-R flip-flop.

Kirti P_Didital Design

26

CLOCKED D FLIP-FLOP
The D flip-flop has only one input referred to as the D input, or data
input, and two outputs as usual Q and Q'.
It transfers the data at the input after the delay of one clock pulse at the
output Q. So in some cases the input is referred to as a delay input and the
flip-flop gets the name delay (D) flip-flop.
It can be easily constructed from an S-R flip-flop by simply incorporating
an inverter between S and R such that the input of the inverter is at the S
end and the output of the inverter is at the R end.
The D flip-flop is either used as a delay device or as a latch to store one
bit of binary information

Kirti P_Didital Design

27

Case 1. If the CLK input is low, the value of the D input has no effect, since
the S and R inputs of the basic NAND flip-flop are kept as 1.
Kirti P_Didital Design

28

Case 2. If the CLK = 1, and D = 1, the NAND gate 1 produces 0, which

forces the output of NAND gate 3 as 1. On the other hand, both the inputs
of NAND gate 2 are 1, which gives the output of gate 2 as 0. Hence, the
output of NAND gate 4 is forced to be 1, i.e., Q = 1, whereas both the
inputs of gate 5 are 1 and the output is 0, i.e., Q' = 0. Hence, we find that
when D = 1, after one clock pulse passes Q = 1, which means the output
follows D
Case 3. If the CLK = 1, and D = 0, the NAND gate 1 produces 1. Hence
both the inputs of NAND gate 3 are 1, which gives the output of gate 3 as
0. On the other hand, D = 0 forces the output of NAND gate 2 to be 1.
Hence the output of NAND gate 5 is forced to be 1, i.e., Q' = 1, whereas
both the inputs of gate 4 are 1 and the output is 0, i.e., Q = 0. Hence, we fi
nd that when D = 0, after one clock pulse passes Q = 0, which means the
output again follows D.

Kirti P_Didital Design

29

A simple way to construct a D flip-flop using an S-R flip-flop is

shown in Figure (a).The logic symbol of a D flip-flop is shown in
Figure (b). A D flip-flop is most often used in the construction of
sequential circuits like registers.

Kirti P_Didital Design

30

Preset and Clear

If Pr = 1 and Cr = 0, the output of NAND gate 5 is forced to be 1, i.e., Q' = 1

and the flip-flop is reset, overwriting the previous state of the flip-flop.
If Pr = 0 and Cr = 1, the output of NAND gate 4 is forced to be 1, i.e., Q = 1
and the flip-flop is set, overwriting the previous state of the flip-flop.
The condition Pr = Cr = 0 must not be applied, since this leads to an
uncertain state.
Kirti P_Didital Design

31

Kirti P_Didital Design

32

Characteristic Table of a D Flip-flop

We can similarly find out the characteristic equation of a D flip-fl op.
The characteristic table of a D fl ip-flop is given in the table in Figure.
From the characteristic table we have to find out the characteristic
equation of the D flip-flop.

Kirti P_Didital Design

33

Now we will find out the characteristic equation of the D fl ip-flop

from the characteristic table with the help of the Karnaugh map

Kirti P_Didital Design

34

J-K FLIP-FLOP
A J-K flip-flop has very similar characteristics to an S-R flip-flop. The only
difference is that the undefined condition for an S-R flip-flop, i.e., Sn = Rn
= 1 condition, is also included.
In this case. Inputs J and K behave like inputs S and R to set and reset the
flip-flop respectively. When J = K = 1, the flip-flop is said to be in a toggle
state, which means the output switches to its complementary state every
time a clock passes.
The data inputs are J and K, which are ANDed with Q' and Q
respectively to obtain the inputs for S and R respectively. A J-K flip-flop
thus obtained is shown in Figure

Kirti P_Didital Design

35

Kirti P_Didital Design

36

Kirti P_Didital Design

37

Case 1. When the clock is applied and J = 0, whatever the value of

Q'n (0 or 1), the output of NAND gate 1 is 1. Similarly, when K = 0,
whatever the value of Qn (0 or 1), the output of gate 2 is also 1.
Therefore, when J = 0 and K = 0, the inputs to the basic flip-flop
are S = 1 and R = 1. This condition forces the flip-flop to remain in
the same state

Case 2. When the clock is applied and J = 0 and K = 1 and the previous state
of the flip-flop is reset (i.e., Qn = 0 and Q'n = 1), then S = 1 and R = 1. Since S
= 1 and R = 1, the basic flip-flop does not alter the state and remains in the
reset state. But if the flip-flop is in set condition (i.e., Qn = 1 and Q'n = 0),
then S = 1 and R = 0. Since S = 1 and R = 0, the basic flip-flop changes its
state and resets.
Kirti P_Didital Design

38

Case 3. When the clock is applied and J = 1 and K = 0 and the previous
state of the flip-fl op is reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R =
1. Since S = 0 and R = 1, the basic flip-flop changes its state and goes to
the set state. But if the flip-flop is already in set condition (i.e., Qn = 1
and Q'n = 0), then S = 1 and R = 1. Since S = 1 and R = 1, the basic flipflop does not alter its state and remains in the set state
Case 4. When the clock is applied and J = 1 and K = 1 and the previous
state of the fl ip-fl op is reset (i.e., Qn = 0 and Q'n = 1), then S = 0 and R
= 1. Since S = 0 and R = 1, the basic flip-flop changes its state and goes to
the set state. But if the flip-flop is already in set condition (i.e., Qn = 1
and Q'n = 0), then S = 1 and R = 0. Since S = 1 and R = 0, the basic fl ip-fl
op changes its state and goes to the reset state. So we find that for J = 1
and K = 1, the flip-flop toggles its state from set to reset and vice versa.
Toggle means to switch to the opposite state

Kirti P_Didital Design

39

Characteristic Table of a J-K Flip-fl op

The characteristic table of a J-K flip-flop is given in the table in
Figure. From the characteristic table we have to find out the
characteristic equation of the J-K flip-flop

Kirti P_Didital Design

40

Now we will find out the characteristic equation of the J-K flip-flop
from the characteristic table with the help of the Karnaugh map in
Figure.

From the Karnaugh map, we obtain

Qn+1 = JQ'n + K'Qn.
Hence, the characteristic equation of a J-K flip-flop is
Qn+1 = JQ'n + K'Qn.
Kirti P_Didital Design

41

Race-around Condition of a J-K Flip-flop

The inherent difficulty of an S-R flip-flop (i.e., S = R = 1) is eliminated by
using the feedback connections from the outputs to the inputs of gate 1 and
gate 2 as shown in Figure.
Truth tables in figure were formed with the assumption that the inputs do
not change during the clock pulse (CLK = 1). But the consideration is not
true because of the feedback connections.

Kirti P_Didital Design

42

Consider, for example, that the inputs are J = K = 1 and Q = 1, and a pulse as
shown in Figure is applied at the clock input.
After a time interval t equal to the propagation delay through two NAND
gates in series, the outputs will change to Q = 0. So now we have J = K = 1
and Q = 0.
After another time interval of t the output will change back to Q = 1.
Hence, we conclude that for the time duration of tP of the clock pulse, the
output will oscillate between 0 and 1. Hence, at the end of the clock pulse, the
value of the output is not certain. This situation is referred to as a racearound condition.
Generally, the propagation delay of TTL gates is of the order of
nanoseconds. So if the clock pulse is of the order of microseconds, then the
output will change thousands of times within the clock pulse.
This race-around condition can be avoided if tp < t < T. Due to the small
propagation delay of the ICs it may be difficult to satisfy the above condition.
A more practical way to avoid the problem is to use the master-slave (M-S)
configuration as discussed belowKirti P_Didital Design
43

Master-Slave J-K Flip-fl op

A master-slave (M-S) flip-flop is shown in Figure. Basically, a master-slave
flip-flop is a system of two flip-flopsone being designated as master and
the other is the slave.
From the figure we see that a clock pulse is applied to the master and the
inverted form of the same clock pulse is applied to the slave

Kirti P_Didital Design

44

When CLK = 1, the first flip-flop (i.e., the master) is enabled and the
outputs Qm and Q'm respond to the inputs J and K according to the
table
At this time the second flip-flop (i.e., the slave) is disabled because
the CLK is LOW to the second flip-flop. Similarly, when CLK becomes
LOW, the master becomes disabled and the slave becomes active, since
now the CLK to it is HIGH.
Therefore, the outputs Q and Q' follow the outputs Qm and Q'm
respectively. Since the second flip-flop just follows the first one, it is
referred to as a slave and the first one is called the master. Hence, the
configuration is referred to as a master-slave (M-S) flip-flop.

Kirti P_Didital Design

45

In this type of circuit configuration the inputs to the gates 5 and 6 do not
change at the time of application of the clock pulse.
Hence the race-around condition does not exist. The state of the masterslave flip-flop, shown in Figure, changes at the negative transition (trailing
edge) of the clock pulse. Hence, it becomes negative triggering a masterslave flip-flop.
This can be changed to a positive edge triggering flip-flop by adding two
inverters to the systemone before the clock pulse is applied to the master
and an additional one in between the master and the slave. The logic
symbol of a negative edge master-slave is shown in Figure.

Kirti P_Didital Design

46

T FLIP-FLOP
With a slight modification of a J-K flip-flop, we can construct a new flipflop called a T flip-flop.
If the two inputs J and K of a J-K flip-flop are tied together it is referred to
as a T flip-flop.
Hence, a T flip-flop has only one input T and two outputs Q and Q'. The
name T flip-flop actually indicates the fact that the flip-flop has the ability to
toggle.
It has actually only two statestoggle state and memory state. Since there
are only two states, a T flip - flop is a very good option to use in counter
design and in sequential circuits design where switching an operation is
required.

Kirti P_Didital Design

47

The truth table of a T flip-flop is given in Figure

If the T input is in 0 state (i.e., J = K = 0) prior to a clock pulse, the Q

output will not change with the clock pulse.
On the other hand, if the T input is in 1 state (i.e., J = K = 1) prior to a
clock pulse, the Q output will change to Q' with the clock pulse.
In other words, we may say that, if T = 1 and the device is clocked, then
the output toggles its state.

Kirti P_Didital Design

48

The truth table shows that when T = 0, then Qn+1= Qn, i.e., the next state
is the same as the present state and no change occurs.

When T = 1, then Qn+1= Q'n, i.e., the state of the flip-flop is

complemented. The circuit diagram of a T flip-flop is shown in Figure.

Kirti P_Didital Design

49

And the block diagram of the flip-flop is shown in Figure

A J-K flip-flop converted into

a T flip-flop
Kirti P_Didital Design

The logic symbol of a

T flip flop
50

Characteristic Table of a T Flip-fl op

The characteristic table of a T flip-flop is given in Figure. From the
characteristic table we have to find out the characteristic equation of
the T flip-flop.

Qn+1 = T Q'n + T Qn

Kirti P_Didital Design

51

TRIGGERING OF FLIP-FLOPS
Flip-fl ops are synchronous sequential circuits. This type of circuit
works with the application of a synchronization mechanism, which
is termed as a clock.
Based on the specific interval or point in the clock during or at
which triggering of the flip-flop takes place, it can be classified into
two different typeslevel triggering and edge triggering.
A clock pulse starts from an initial value of 0, goes momentarily to
1, and after a short interval, returns to the initial value

Kirti P_Didital Design

52

Level Triggering of Flip-flops

If a flip-flop gets enabled when a clock pulse goes HIGH and remains
enabled throughout the duration of the clock pulse remaining HIGH, the
flip-flop is said to be a level triggered flip-flop.
If the flip-flop changes its state when the clock pulse is positive, it is
termed as a positive level triggered flip-flop.
On the other hand, if a NOT gate is introduced in the clock input
terminal of the flip-flop, then the flip-flop changes its state when the
clock pulse is negative, it is termed as a negative level triggered flip-flop.
The main drawback of level triggering is that, as long as the clock pulse
is active, the flip-flop changes its state more than once or many times for
the change in inputs. If the inputs do not change during one clock pulse,
then the output remains stable.
On the other hand, if the frequency of the input change is higher than
the input clock frequency, the output of the flip-flop undergoes multiple
changes as long as the clock remains active
Kirti P_Didital Design

53

Edge-triggering of Flip-flops
A clock pulse goes from 0 to 1 and then returns from 1 to 0. Figure
shows the two transitions and they are defined as the positive
edge (0 to 1 transition) and the negative edge (1 to 0 transition).
The term edge-triggered means that the flip-flop changes its state
only at either the positive or negative edge of the clock pulse

Kirti P_Didital Design

54

One way to make the flip-flop respond to only the edge of the
clock pulse is to use capacitive coupling. An RC circuit is shown
in Figure

Kirti P_Didital Design

55