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Explain the three different types of dependencies in instructions

Or
Explain the various types of dependencies in ILP
Or
What is instruction level parallelism? Explain in detail about the various dependencies caused in ILP
Or
Explain the data and the name dependencies with suitable examples
Or
Explain in detail the concept involved in instruction level parallelism

Instruction Level Parallelism

Instruction-level parallelism (ILP) is the potential overlap the execution of
instructions using pipeline concept to improve performance of the system. The various
techniques that are used to increase amount of parallelism are reduces the impact of data and
control hazards and increases processor ability to exploit parallelism. There are mainly two
approaches to exploit ILP.
i) Hardware based approach: An approach that relies on hardware to help discover and
exploit the parallelism dynamically. Intel Pentium series uses this approach.
ii) Software based approach: An approach that relies on software technology to find
parallelism statically at compile time. This approach has limited use in scientific or
application specific environment. Static approach of exploiting ILP is found in Intel Itanium.
Factors of both programs and processors limit the amount of parallelism that can be
exploited among instructions and these limit the performance achievable. The performance of
the pipelined processors is given by:
Pipeline CPI= Ideal Pipeline CPI + Structural stalls + Data hazard stalls + Control stalls
CPI (Cycles per Instruction) for a pipelined processor is the sum of the base CPI and
all contributions from stalls. The ideal pipeline CPI is a measure of the maximum
performance attainable by the implementation. By reducing each of the terms of the righthand side, we minimize the overall pipeline CPI and thus increase the IPC (Instructions per
Clock).
By reducing each of the terms on the right hand side, it is possible to minimize the
overall pipeline CPI.
To exploit the ILP, the primary focus is on Basic Block (BB). The BB is a straight line
code sequence with no branches in except the entry and no branches out except at the exit.
The average size of the BB is very small i.e., about 4 to 6 instructions. The amount of overlap
that can be exploited within a Basic Block is likely to be less than the average size of BB. To
further enhance ILP, it is possible to look at ILP across multiple BB.
The simplest and most common way to increase the ILP is to exploit the parallelism
among iterations of a loop (Loop level parallelism). Each iteration of a loop can overlap with
any other iteration. Here is a simple example of a loop, which adds two 1000-element arrays,
that is completely parallel:
for (i=1;i<=1000; i=i+1) x[i] = x[i] + y[i];

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Various Types of Dependences in ILP.

To exploit instruction-level parallelism, determine which instructions can be executed in
parallel. If two instructions are parallel, they can execute simultaneously in a pipeline of
arbitrary length without causing any stalls, assuming the pipeline has sufficient resources. If
two instructions are dependent, they are not parallel and must be executed in sequential order.
There are three different types dependences.
Data Dependences (True Data Dependency)
Name Dependences
Control Dependences
Data Dependences
An instruction j is data dependant on instruction i if either of the following holds:
i) Instruction i produces a result that may be used by instruction j
Eg1:
i:
L.D
F0, 0(R1)
j:
ADD.D
F4, F0, F2
ith instruction is loading the data into the F0 and jth instruction use F0 as one the
operand. Hence, jth instruction is data dependant on ith instruction.
Eg2:
DADD
R1, R2, R3
DSUB
R4, R1, R5
ii) Instruction j is data dependant on instruction k and instruction k data dependant on
instruction i
Eg:
L.D
F4, 0(R1)
MUL.D
F0, F4, F6
ADD.D
F5, F0, F7
Dependences are the property of the programs. A Data value may flow between instructions
either through registers or through memory locations. Detecting the data flow and
dependence that occurs through registers is quite straight forward. Dependences that flow
through the memory locations are more difficult to detect. A data dependence conveys three
things.
a) The possibility of the Hazard.
b) The order in which results must be calculated and
c) An upper bound on how much parallelism can possibly be exploited.

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Name Dependences
A Name Dependence occurs when two instructions use the same Register or Memory
location, but there is no flow of data between the instructions associated with that name.
Two types of Name dependences:
i) Antidependence: between instruction i and instruction j occurs when instruction j writes a
register or memory location that instruction i reads. The original ordering must be preserved
to ensure that i reads the correct value.
Eg:
L.D
F0, 0(R1)
DADDUI
R1, R1, R3
ii) Output dependence: Output Dependence occurs when instructions i and j write to the
same register or memory location.
Eg:
ADD.D
F4, F0, F2
SUB.D
F4, F3, F5
The ordering between the instructions must be preserved to ensure that the value finally
written corresponds to instruction j. The above instruction can be reordered or can be
executed simultaneously if the name of the register is changed. The renaming can be easily
done either statically by a compiler or dynamically by the hardware.
Control Dependence:
A control dependence determines the ordering of an instruction i with respect to a branch
instruction,
Eg:
if P1 {
S1;
}
if P2 {
S2;
}
S1 is Control dependent on P1 and S2 is control dependent on P2 but not on P1.
In general, there are two constraints imposed by control dependences:
a)An instruction that is control dependent on a branch cannot be moved before the branch ,so
that its execution is no longer controlled by the branch.
b)An instruction that is not control dependent on a branch cannot be moved after the branch
so that its execution is controlled by the branch.
Control dependence is preserved by two properties in a simple pipeline. First, instructions
execute in program order. This ordering ensures that an instruction that occurs before a
branch is executed before the branch. Second, the detection of control or branch hazards
ensures that an instruction that is control dependent on a branch is not executed until the
branch direction is known.

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Data Hazard and various hazards in ILP.
Data Hazards
A hazard is created whenever there is dependence between instructions, and they are
close enough that the overlap caused by pipelining, or other reordering of instructions, would
change the order of access to the operand involved in the dependence. Because of the
dependence, we must preserve what is called program order, ie, the order that the instructions
would execute in, if executed sequentially one at a time as determined by the original source
program. The goal of both our software and hardware techniques is to exploit parallelism by
preserving program order only where it affects the outcome of the program. Detecting and
avoiding hazards ensures that necessary program order is preserved.
Data hazards may be classified as one of three types, depending on the order of read and
write accesses in the instructions.
Consider two instructions i and j, with i occurring before j in program order. The possible
data hazards are,
RAW (read after write) j tries to read a source before i writes it, so j incorrectly gets the
old value. This hazard is the most common type and corresponds to a true data dependence.
Program order must be preserved to ensure that j receives the value from i. In the simple
common five-stage static pipeline a load instruction followed by an integer ALU instruction
that directly uses the load result will lead to a RAW hazard.
WAW (write after write) j tries to write an operand before it is written by i. The writes
end up being performed in the wrong order, leaving the value written by i rather than the
value written by j in the destination. This hazard corresponds to an output dependence. WAW
hazards are present only in pipelines that write in more than one pipe stage or allow an
instruction to proceed even when a previous instruction is stalled. The classic five stage
integer pipeline writes a register only in the WB stage and avoids this class of hazards.
WAR (write after read) j tries to write a destination before it is read by i, so i incorrectly
gets the new value. This hazard arises from an anti dependence. WAR hazards cannot occur
in most static issue pipelines even deeper pipelines or floating point pipelines because all
reads are early (in ID) and all writes are late (in WB). A WAR hazard occurs either when
there are some instructions that write results early in the instruction pipeline, and other
instructions that read a source late in the pipeline or when instructions are reordered.