Question Paper Solutions
Question Paper Solutions
BINDU RAJAPPA
COMPUTE resumes;
IMPORTANT POINTS:
The routine executed in response to an interrupt
request is called the interrupt service routine – PRINT
Interrupt latency
INTERRUPT HARDWARE
(Vectored interrupts)
(Interrupt nesting)
(Daisy-chain)
VECTOR INTERRUPTS:
INTERRUPT NESTING:
Priority structure
INTR 1 I NTR p
Processor
INTA1 INTAp
Priority arbitration
circuit
Figure 4.7. Implementation of interrupt priority using individual
interruptrequest and acknowledge lines.
Simultaneous Requests
Example
Consider a processor that uses the vectored interrupt
scheme, where the starting address of the interrupt-
service routine is stored at memory location INTVEC.
Assume,
Interrupt - enable bit is 9th bit.
Steps:
Locality of reference
What is cache?
ADDRESS TRANSLATION:
Assume,
31 30 1 0
Status and control
IRQ Done
IE R/ W
Starting address
Word count
Main
Processor
memory
System bus
Disk/DMA DMA
controller controller Printer Keyboard
Figure 4.19. Use of DMA controllers in a computer system.
• MREMORY ACCESS
• Memory access by the processor and the DMA
controller are interwoven.
• DMA device has higher priority for using bus than
processor
• Among all DMA requests to priority is given to high
speed peripherals.
• Cycling stealing-since processor originates most
memory access cycles the dma controller can be said
to steal memory cycle from the processor.
• block(brust) modern DMA controller may be given
execlusive access to the main memory to transfer a
bloack data without interruption.
(B)Assembler Directives
Allow programmer to specify other information
needed to translate the source program into object
program – assembler directives/commands.
For eg., SUM is used to represent the value 200. This
fact is conveyed to the assembler program through a
statement such as SUM EQU 200 - informs the
assembler the name SUM should be replaced by the
value 200 wherever it appears in the program.
Starting address
generator
IR
Cloc µPC
k
Control
store
COMPUTE resumes;
sequence of data
Figure 1.3. Singlebus structure.
Solution:-
Big-Endian: lower byte addresses are used
for the most significant bytes of the word.
1 0 0 1 1 (-1 3 )
0 1 0 1 1 (+11)
11111 1 0 0 1 1
1111 10 0 1 1
sign extension is shown in bold
000 0 0 000
111 001 1
00 0 000
1 1 0 1 1 1 1 0 0 0 1 (-143)
0 +1 -1 +1 0 -1 0 +1 0 0
-1 +1 -1 +1 0 +1 0 0
Figure Booth recoding of a multiplier
The booth technique for recording multiplier is
summarized in below table.
The transformation 011….110 +100…0-10 is called
skipping over 1s
Multiplier version
of multiplication
Bit i bit i-1 selected by bit i.
0 0 0 ×M
0 1 1 ×M
1 0 -1 ×M
1 1 0× M
Figure Booth multiplier recoding table