Microcontrollers

4 Sem ECE

Microcontrollers Notes for IV Sem ECE Students

Saneesh Cleatus Thundiyil
Associate. Professor,
Department of Electronics and Communication Engineering,
BMS Institute of Technology
Bangalore - 64

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

SYLLABUS
MICROCONTROLLERS
(Common to EC/TC/EE/IT/BM/ML)
Sub Code : 10ES42 IA Marks : 25
Hrs/ Week : 04 Exam Hours : 03
Total Hrs. : 52 Exam Marks : 100
UNIT 1: Microprocessors and microcontroller. Introduction, Microprocessors and
Microcontrollers, RISC & CISC CPU Architectures, Harvard & Von- Neumann CPU
architecture, Computer software. The 8051 Architecture: Introduction, Architecture of
8051, Pin diagram of 8051, Memory organization, External Memory interfacing, Stacks.
6 Hrs
UNIT 2: Addressing Modes: Introduction, Instruction syntax, Data types, Subroutines,
Addressing modes: Immediate addressing , Register addressing, Direct addressing, Indirect
addressing, relative addressing, Absolute addressing, Long addressing, Indexed addressing,
Bit inherent addressing, bit direct
addressing. Instruction set: Instruction timings, 8051 instructions: Data transfer
instructions, Arithmetic instructions, Logical instructions, Branch instructions, Subroutine
instructions, Bit manipulation instruction.
6 Hrs
UNIT 3: 8051 programming: Assembler directives, Assembly language programs and
Time delay calculations.
6 Hrs
UNIT 4: 8051 Interfacing and Applications: Basics of I/O concepts, I/O Port Operation,
Interfacing 8051 to LCD, Keyboard, parallel and serial ADC, DAC, Stepper motor interfacing
and DC motor interfacing and programming
7 Hrs
UNIT 5: 8051 Interrupts and Timers/counters: Basics of interrupts, 8051 interrupt
structure, Timers and Counters, 8051 timers/counters, programming 8051 timers in
assembly and C .
6 Hrs
UNIT 6: 8051 Serial Communication: Data communication, Basics of Serial Data
Communication, 8051 Serial Communication, connections to RS-232, Serial communication
Programming in assembly and C.
8255A Programmable Peripheral Interface:, Architecture of 8255A, I/O addressing,, I/O
devices interfacing with 8051 using 8255A.
6 Hrs
Course Aim The MSP430 microcontroller is ideally suited for development of low-power
embedded systems that must run on batteries for many years. There are also applications
where MSP430 microcontroller must operate on energy harvested from the environment. This
is possible due to the ultra-low power operation of MSP430 and the fact that it provides a
complete system solution including a RISC CPU, flash memory, on-chip data converters and
on-chip peripherals.
Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

UNIT 7:
Motivation for MSP430microcontrollers Low Power embedded systems, On-chip
peripherals (analog and digital), low-power RF capabilities. Target applications (Singlechip, low cost, low power, high performance system design).
2 Hrs
MSP430 RISC CPU architecture, Compiler-friendly features, Instruction set, Clock system,
Memory subsystem. Key differentiating factors between different MSP430 families. 2 Hrs
Introduction to Code Composer Studio (CCS v4). Understanding how to use CCS for
Assembly, C, Assembly+C projects for MSP430 microcontrollers. Interrupt programming.
3 Hrs
Digital I/O I/O ports programming using C and assembly, Understanding the muxing
scheme of the MSP430 pins.
2 Hrs
UNIT 8:
On-chip peripherals. Watchdog Timer, Comparator, Op-Amp, Basic Timer, Real Time
Clock (RTC), ADC, DAC, SD16, LCD, DMA.
2 Hrs
Using the Low-power features of MSP430. Clock system, low-power modes, Clock
request feature, Low-power programming and Interrupt.
2 Hrs
Interfacing LED, LCD, External memory. Seven segment LED modules interfacing.
Example Real-time clock.
2 Hrs
Case Studies of applications of MSP430 - Data acquisition system, Wired Sensor network,
Wireless sensor network with Chipcon RF interfaces.
3 Hrs
TEXT BOOKS:
1. The 8051 Microcontroller and Embedded Systems using assembly and C -,
Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. McKinlay; PHI, 2006 /
Pearson, 2006
2. MSP430 Microcontroller Basics, John Davies, Elsevier, 2010 (Indian edition
available)
REFERENCE BOOKS:
1. The 8051 Microcontroller Architecture, Programming & Applications, 2e Kenneth
J. Ayala ;, Penram International, 1996 / Thomson Learning 2005.
2. The 8051 Microcontroller, V.Udayashankar and MalikarjunaSwamy, TMH, 2009
3. MSP430 Teaching CD-ROM, Texas Instruments, 2008 (can be requested
http://www.uniti.in )
4. Microcontrollers: Architecture, Programming, Interfacing and System Design,Raj
Kamal, Pearson Education, 2005

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

UNIT - 1
1.1 MICROPROCESSORS AND MICROCONTROLLERS
Microprocessor

Microcontroller

Arithmetic and logic

unit

ALU

Timer/
Counter

Accumulator

Accumulator

Registers

Working Registers

Internal RAM

Program Counter

Stack Pointer

Clock Circuit

Interrupt circuit

Block diagram of microprocessor

Internal
ROM

Stack Pointer

IO Ports
Interrupt
Circuits

Clock
Circuits

Program Counter
Block diagram of microcontroller

Microprocessor contains ALU, General purpose Microcontroller contains the circuitry of

registers, stack pointer, program counter, clock microprocessor, and in addition it has built in
timing circuit, interrupt circuit
ROM, RAM, I/O Devices, Timers/Counters etc.
It has many instructions to move data between It has few instructions to move data between
memory and CPU
memory and CPU
Few bit handling instruction

It has many bit handling instructions

Less number of pins are multifunctional

More number of pins are multifunctional

Single memory map for data and code Separate memory map for data and code
(program)
(program)
Access time for memory and IO are more
Microprocessor
based
additional hardware

system

Less access time for built in memory and IO.

requires It requires less additional hardwares

More flexible in the design point of view

Less flexible since the additional circuits which is

residing inside the microcontroller is fixed for a
particular microcontroller

Large number of instructions with flexible Limited number of instructions with few
addressing modes
addressing modes

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

1.2. RISC AND CISC CPU ARCHITECTURES

Microcontrollers with small instruction set are called reduced instruction set computer (RISC)
machines and those with complex instruction set are called complex instruction set computer
(CISC). Intel 8051 is an example of CISC machine whereas microchip PIC 18F87X is an example of
RISC machine.
RISC

CISC

Instruction takes one or two cycles

Instruction takes multiple cycles

Only load/store instructions are used to access In additions to load and store instructions,
memory
memory access is possible with other
instructions also.
Instructions executed by hardware

Instructions executed by the micro program

Fixed format instruction

Variable format instructions

Few addressing modes

Many addressing modes

Few instructions

Complex instruction set

Most of the have multiple register banks

Single register bank

Highly pipelined

Less pipelined

Complexity is in the compiler

Complexity in the microprogram

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

1.2. HARVARD & VON- NEUMANN CPU ARCHITECTURE

Von-Neumann (Princeton architecture)

Harvard architecture

Data

Program
Memory

Data
CPU

CPU
Data
Memory

Address Bus

Data
Memory

Address Bus
Data

Program
Memory

Address Bus
Von-Neumann (Princeton architecture)
It uses single memory
instructions and data.

space

for

Harvard architecture
both It has separate program memory and data
memory

It is not possible to fetch instruction code and Instruction code and data can be fetched
data
simultaneously
Execution of instruction takes more machine Execution of instruction takes less machine
cycle
cycle
Uses CISC architecture

Uses RISC architecture

Instruction pre-fetching is a main feature

Instruction parallelism is a main feature

Also known as control flow or control driven Also known as data flow or data driven
computers
computers
Simplifies the chip design because of single Chip design is complex due to separate memory
memory space
space
Eg. 8085, 8086, MC6800

Eg. General purpose microcontrollers, special

DSP chips etc.

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

1.3 COMPUTER SOFTWARE

A set of instructions written in a specific sequence for the computer to solve a specific task is called
a program and software is a collection of such programs.
The program stored in the computer memory in the form of binary numbers is called machine
instructions. The machine language program is called object code.
An assembly language is a mnemonic representation of machine language. Machine language and
assembly language are low level languages and are processor specific.
The assembly language program the programmer enters is called source code. The source code
(assembly language) is translated to object code (machine language) using assembler.
Programs can be written in high level languages such as C, C++ etc. High level language will be
converted to machine language using compiler or interpreter. Compiler reads the entire program
and translate into the object code and then it is executed by the processor. Interpreter takes one
statement of the high level language as input and translate it into object code and then executes.
1.4 THE 8051 ARCHITECTURE
Introduction
Salient features of 8051 microcontroller are given below.
Eight bit CPU
On chip clock oscillator
4Kbytes of internal program memory (code memory) [ROM]
128 bytes of internal data memory [RAM]
64 Kbytes of external program memory address space.
64 Kbytes of external data memory address space.
32 bi directional I/O lines (can be used as four 8 bit ports or 32 individually addressable I/O
lines)
Two 16 Bit Timer/Counter :T0, T1
Full Duplex serial data receiver/transmitter
Four Register banks with 8 registers in each bank.
Sixteen bit Program counter (PC) and a data pointer (DPTR)
8 Bit Program Status Word (PSW)
8 Bit Stack Pointer
Five vector interrupt structure (RESET not considered as an interrupt.)
8051 CPU consists of 8 bit ALU with associated registers like accumulator A , B register,
PSW, SP, 16 bit program counter, stack pointer.
ALU can perform arithmetic and logic functions on 8 bit variables.
8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 1F]
o Bit addressable memory area [20 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

The 8051 architecture.

ALU

PSW

Port 0

SFR
General
Purpose
RAM

PC

E
A
ALE
PSEN
XTAL1
XTAL2

System
Timing
System
interrupt
timers

RESET
Data
buffers

Port 1

Memory
control

I/O
A8A15

ROM

Port 3

General
purpose
area

Bit addressible
area
Register Bank 3
Register Bank 2
Register Bank 1

VCC
GND

D0-D7

I/O

Port 2
DPTR
DPH
DPL

I/O
A0-A7

Register Bank 0

I/O
INT
CNTR
SERIAL
RD/WR

IE
IP
PCON
SBUF
SCON
TCON
TMOD
TL0
TH0
TL1
TH1

SFR and
General Purpose RAM

8051 has 4 K Bytes of internal ROM. The address space is from 0000 to 0FFFh. If the
program size is more than 4 K Bytes 8051 will fetch the code automatically from external
memory.
Accumulator is an 8 bit register widely used for all arithmetic and logical operations.
Accumulator is also used to transfer data between external memory. B register is used along
with Accumulator for multiplication and division. A and B registers together is also called
MATH registers.

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

PSW (Program Status Word). This is an 8 bit register which contains the arithmetic status of
ALU and the bank select bits of register banks.
CY AC F0 RS1 RS0 OV - P
CY
carry flag
AC
auxiliary carry flag
F0
available to the user for general purpose
RS1,RS0 register bank select bits
OV
overflow
P
parity
Stack Pointer (SP) it contains the address of the data item on the top of the stack. Stack
may reside anywhere on the internal RAM. On reset, SP is initialized to 07 so that the default
stack will start from address 08 onwards.
Data Pointer (DPTR) DPH (Data pointer higher byte), DPL (Data pointer lower byte). This
is a 16 bit register which is used to furnish address information for internal and external
program memory and for external data memory.
Program Counter (PC) 16 bit PC contains the address of next instruction to be executed.
On reset PC will set to 0000. After fetching every instruction PC will increment by one.

1.5

PIN DIAGRAM

Pinout Description
Pins 1-8

PORT 1. Each of these pins can be configured as an input or an output.

Pin 9

RESET. A logic one on this pin disables the microcontroller and clears the contents of
most registers. In other words, the positive voltage on this pin resets the
microcontroller. By applying logic zero to this pin, the program starts execution from
the beginning.

Pins10-17

PORT 3. Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions

Saneesh Cleatus Thundiyil

BMS Institute of Technology, Bangalore 64

Microcontrollers

4 Sem ECE

Pin 10

RXD. Serial asynchronous communication input or Serial synchronous communication

output.

Pin 11

TXD. Serial asynchronous

communication clock output.

Pin 12

INT0.External Interrupt 0 input

Pin 13

INT1. External Interrupt 1 input

Pin 14

T0. Counter 0 clock input

Pin 15

T1. Counter 1 clock input

Pin 16

WR. Write to external (additional) RAM

Pin 17

RD. Read from external RAM

Pin 18, 19

XTAL2, XTAL1. Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins.

Pin 20

GND. Ground.

Pin 21-28

Port 2. If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher
address byte, i.e. addresses A8-A15 will appear on this port. Even though memory
with capacity of 64Kb is not used, which means that not all eight port bits are used for
its addressing, the rest of them are not available as inputs/outputs.

Pin 29

PSEN. If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.

Pin 30

ALE. Prior to reading from external memory, the microcontroller puts the lower
address byte (A0-A7) on P0 and activates the ALE output. After receiving signal from
the ALE pin, the external latch latches the state of P0 and uses it as a memory chip
address. Immediately after that, the ALE pin is returned its previous logic state and P0
is now used as a Data Bus.

Pin 31

EA. By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that
even there is a program written to the microcontroller, it will not be executed. Instead,
the program written to external ROM will be executed. By applying logic one to the EA
pin, the microcontroller will use both memories, first internal then external (if exists).

Pin 32-39

PORT 0. Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when
the ALE pin is driven high (1) or as data output (Data Bus) when the ALE pin is driven
low (0).

Pin 40

VCC. +5V power supply.

communication

output

or

Serial

synchronous

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BMS Institute of Technology, Bangalore 64

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Microcontrollers

4 Sem ECE

1.6 MEMORY ORGANIZATION

Internal RAM organization
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0
R7
R6
R5
R4
R3
R2
R1
R0

1F
1E
1D
1C
1B
1A
19
18
17
16
15
14
13
12
11
10
0F
0E
0D
0C
0B
0A
09
08
07
06
05
04
03
02
01
00

B
A
N
K
3

7F

78

77

70

6F

68

67

60

5F

58

57

50

29

4F

48

28

47

40

27

3F

38

26

37

30
28

2F
2E
2D
2C
2B

B
A
N
K
2

2A

25

2F

B
A
N
K
1

24

27

20

23

1F

18

22

17

10

21

0F

08

20

07

00

B
A
N
K
0

7F
7E
.
.
.
.
.
.
.
.
32
31
30
General purpose memory

Bit addressable memory

Working Registers
Register Banks: 00h to 1Fh. The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1,
R2, R3, R4, R5, R6, and R7). There are four such register banks. Selection of register bank can be
done through RS1,RS0 bits of PSW. On reset, the default Register Bank 0 will be selected.
Bit Addressable RAM: 20h to 2Fh . The 8051 supports a special feature which allows access to bit
variables. This is where individual memory bits in Internal RAM can be set or cleared. In all there
are 128 bits numbered 00h to 7Fh. Being bit variables any one variable can have a value 0 or 1. A bit
variable can be set with a command such as SETB and cleared with a command such as CLR.
Example instructions are:
SETB 25h ; sets the bit 25h (becomes 1)
CLR 25h ; clears bit 25h (becomes 0)
Note, bit 25h is actually bit 5 of Internal RAM location 24h.
The Bit Addressable area of the RAM is just 16 bytes of Internal RAM located between 20h and 2Fh.
General Purpose RAM: 30h to 7Fh. Even if 80 bytes of Internal RAM memory are available for
general-purpose data storage, user should take care while using the memory location from 00 -2Fh
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BMS Institute of Technology, Bangalore 64

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Microcontrollers

4 Sem ECE

since these locations are also the default register space, stack space, and bit addressable space. It is
a good practice to use general purpose memory from 30 7Fh. The general purpose RAM can be
accessed using direct or indirect addressing modes.

1.7 EXTERNAL MEMORY INTERFACING

Eg. Interfacing of 16 K Byte of RAM and 32 K Byte of EPROM to 8051
Number of address lines required for 16 Kbyte memory is 14 lines and that of 32Kbytes of
memory is 15 lines.
The connections of external memory is shown below.
PSEN

PSEN
A14
A13
A12

A9
A8

WR
RD
AL
E

LE
A0-A7

8051

__
EA
GND

LOWER BYTE
ADDRESS
[AD0 AD7]

AD0
AD7

A13
A12
..
A8
WE
OE
A7
..
A1
A0

A14
A13
A12

16 Kbyte
RAM
A0-A7

.
.
.
A3
A2
A1
A0

32 Kbyte
RAM

DAT
A
O/P

DAT
A
O/P

8 BIT

8 BIT

DATA BUS [AD0 AD7]

The lower order address and data bus are multiplexed. De-multiplexing is done by the latch.
Initially the address will appear in the bus and this latched at the output of latch using ALE signal.
The output of the latch is directly connected to the lower byte address lines of the memory. Later
data will be available in this bus. Still the latch output is address it self. The higher byte of address
bus is directly connected to the memory. The number of lines connected depends on the memory
size.
The RD and WR (both active low) signals are connected to RAM for reading and writing the data.
PSEN of microcontroller is connected to the output enable of the ROM to read the data from the
memory.
EA (active low) pin is always grounded if we use only external memory. Otherwise, once the
program size exceeds internal memory the microcontroller will automatically switch to external
memory.
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BMS Institute of Technology, Bangalore 64

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1.8 STACK
A stack is a last in first out memory. In 8051 internal RAM space can be used as stack. The address
of the stack is contained in a register called stack pointer. Instructions PUSH and POP are used for
stack operations. When a data is to be placed on the stack, the stack pointer increments before
storing the data on the stack so that the stack grows up as data is stored (pre-increment). As the
data is retrieved from the stack the byte is read from the stack, and then SP decrements to point the
next available byte of stored data (post decrement). The stack pointer is set to 07 when the 8051
resets. So that default stack memory starts from address location 08 onwards (to avoid overwriting
the default register bank ie., bank 0).
Eg; Show the stack and SP for the following.
MOV R6, #25H
MOV R1, #12H
MOV R4, #0F3H

[SP]=07
[R6]=25H
[R1]=12H
[R4]=F3H

//CONTENT OF SP IS 07 (DEFAULT VALUE)

//CONTENT OF R6 IS 25H
//CONTENT OF R1 IS 12H
//CONTENT OF R4 IS F3H

PUSH 6
PUSH 1
PUSH 4

[SP]=08
[SP]=09
[SP]=0A

[08]=[06]=25H
[09]=[01]=12H
[0A]=[04]=F3H

POP 6
POP 1
POP 4

[06]=[0A]=F3H
[01]=[09]=12H
[04]=[08]=25H

//CONTENT OF 08 IS 25H
//CONTENT OF 09 IS 12H
//CONTENT OF 0A IS F3H

[SP]=09 //CONTENT OF 06 IS F3H

[SP]=08 //CONTENT OF 01 IS 12H
[SP]=07 //CONTENT OF 04 IS 25H

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BMS Institute of Technology, Bangalore 64

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4 Sem ECE

UNIT 2
2.1 INSTRUCTION SYNTAX.
General syntax for 8051 assembly language is as follows.
LABEL: OPCODE OPERAND ;COMMENT
LABEL : (THIS IS NOT NECESSARY UNLESS THAT SPECIFIC LINE HAS TO BE ADDRESSED). The label is a symbolic
address for the instruction. When the program is assembled, the label will be given specific address
in which that instruction is stored. Unless that specific line of instruction is needed by a branching
instruction in the program, it is not necessary to label that line.
OPCODE: Opcode is the symbolic representation of the operation. The assembler converts the
opcode to a unique binary code (machine language).
OPERAND: While opcode specifies what operation to perform, operand specifies where to perform
that action. The operand field generally contains the source and destination of the data. In some
cases only source or destination will be available instead of both. The operand will be either
address of the data, or data itself.
COMMENT: Always comment will begin with ; or // symbol. To improve the program quality,
programmer may always use comments in the program.

2.2 ADDRESSING MODES

Various methods of accessing the data are called addressing modes.
8051 addressing modes are classified as follows.
1. Immediate addressing.
2. Register addressing.
3. Direct addressing.
4. Indirect addressing.
5. Relative addressing.
6. Absolute addressing.
7. Long addressing.
8. Indexed addressing.
9. Bit inherent addressing.
10. Bit direct addressing.
1. Immediate addressing.
In this addressing mode the data is provided as a part of instruction itself. In other words
data immediately follows the instruction.
Eg.

MOV A,#30H
ADD A, #83

# Symbol indicates the data is immediate.

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2. Register addressing.
In this addressing mode the register will hold the data. One of the eight general registers
(R0 to R7) can be used and specified as the operand.
Eg.

MOV A,R0
ADD A,R6
R0 R7 will be selected from the current selection of register bank. The default register bank will be bank 0.

3. Direct addressing
There are two ways to access the internal memory. Using direct address and indirect address. Using
direct addressing mode we can not only address the internal memory but SFRs also. In direct addressing, an 8
bit internal data memory address is specified as part of the instruction and hence, it can specify the address
only in the range of 00H to FFH. In this addressing mode, data is obtained directly from the memory.
Eg.
MOV A,60h
ADD A,30h
4.

Indirect addressing
The indirect addressing mode uses a register to hold the actual address that will be used in data
movement. Registers R0 and R1 and DPTR are the only registers that can be used as data pointers. Indirect
addressing cannot be used to refer to SFR registers. Both R0 and R1 can hold 8 bit address and DPTR can hold
16 bit address.
Eg.
MOV A,@R0
ADD A,@R1
MOVX A,@DPTR

5. Indexed addressing.
In indexed addressing, either the program counter (PC), or the data pointer (DTPR)is
used to hold the base address, and the A is used to hold the offset address. Adding the value of the
base address to the value of the offset address forms the effective address. Indexed addressing is
used with JMP or MOVC instructions. Look up tables are easily implemented with the help of index
addressing.
Eg.

MOVC A, @A+DPTR
// copies the contents of memory location pointed by the sum of the
accumulator A and the DPTR into accumulator A.
MOVC A, @A+PC
// copies the contents of memory location pointed by the sum of the
accumulator A and the program counter into accumulator A.

6. Relative Addressing.
Relative addressing is used only with conditional jump instructions. The relative address,
(offset), is an 8 bit signed number, which is automatically added to the PC to make the address of
the next instruction. The 8 bit signed offset value gives an address range of +127 to 128 locations.
The jump destination is usually specified using a label and the assembler calculates the jump offset
accordingly. The advantage of relative addressing is that the program code is easy to relocate and
the address is relative to position in the memory.
Eg.

7.

SJMP LOOP1
JC BACK

Absolute addressing
Absolute addressing is used only by the AJMP (Absolute Jump) and ACALL (Absolute Call)
instructions. These are 2 bytes instructions. The absolute addressing mode specifies the lowest 11
bit of the memory address as part of the instruction. The upper 5 bit of the destination address are
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BMS Institute of Technology, Bangalore 64

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Microcontrollers

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the upper 5 bit of the current program counter. Hence, absolute addressing allows branching only
within the current 2 Kbyte page of the program memory.
Eg.

AJMP LOOP1
ACALL LOOP2

8. Long Addressing
The long addressing mode is used with the instructions LJMP and LCALL. These are 3 byte
instructions. The address specifies a full 16 bit destination address so that a jump or a call can be
made to a location within a 64 Kbyte code memory space.
Eg.

LJMP FINISH
LCALL DELAY

9. Bit Inherent Addressing

In this addressing, the address of the flag which contains the operand, is implied in the opcode
of the instruction.
Eg.

CLR C ;

Clears the carry flag to 0

10. Bit Direct Addressing

In this addressing mode the direct address of the bit is specified in the instruction. The RAM
space 20H to 2FH and most of the special function registers are bit addressable. Bit address values
are between 00H to 7FH.
Eg.

CLR 07h
SETB 07H

;
;

Clears the bit 7 of 20h RAM space

Sets the bit 7 of 20H RAM space.

2.3 INSTRUCTION SET.

1. Instruction Timings
The 8051 internal operations and external read/write operations are controlled by the oscillator
clock.
T-state, Machine cycle and Instruction cycle are terms used in instruction timings.
T-state is defined as one subdivision of the operation performed in one clock period. The terms 'Tstate' and 'clock period' are often used synonymously.
Machine cycle is defined as 12 oscillator periods. A machine cycle consists of six states and each
state lasts for two oscillator periods. An instruction takes one to four machine cycles to execute an
instruction. Instruction cycle is defined as the time required for completing the execution of an
instruction. The 8051 instruction cycle consists of one to four machine cycles.
Eg. If 8051 microcontroller is operated with 12 MHz oscillator, find the execution time for the
following four instructions.
1. ADD A, 45H
2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB
Since the oscillator frequency is 12 MHz, the clock period is, Clock period = 1/12 MHz = 0.08333 S.
Time for 1 machine cycle = 0.08333 S x 12 =1 S.
Instruction
No. of machine cycles
Execution time
1. ADD A, 45H
1
1 s
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BMS Institute of Technology, Bangalore 64

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2. SUBB A, #55H
3. MOV DPTR, #2000H
4. MUL AB

4 Sem ECE
2
2
4

2 s
2 s
4 s

2. 8051 Instructions
The instructions of 8051 can be broadly classified under the following headings.
1. Data transfer instructions
2. Arithmetic instructions
3. Logical instructions
4. Branch instructions
5. Subroutine instructions
6. Bit manipulation instructions
Data transfer instructions.
In this group, the instructions perform data transfer operations of the following types.
a. Move the contents of a register Rn to A
i. MOV A,R2
ii. MOV A,R7

b. Move the contents of a register A to Rn

i. MOV R4,A
ii. MOV R1,A

c. Move an immediate 8 bit data to register A or to Rn or to a memory location(direct or

indirect)
i. MOV A, #45H
ii. MOV R6, #51H
iii. MOV 30H, #44H

iv. MOV @R0, #0E8H

v. MOV DPTR, #0F5A2H
vi. MOV DPTR, #5467H

d. Move the contents of a memory location to A or A to a memory location using direct and
indirect addressing
i. MOV A, 65H
ii. MOV A, @R0

iii. MOV 45H, A

iv. MOV @R1, A

e. Move the contents of a memory location to Rn or Rn to a memory location using direct

addressing
i. MOV R3, 65H
ii. MOV 45H, R2

f.

Move the contents of memory location to another memory location using direct and
indirect addressing
i. MOV 47H, 65H
ii. MOV 45H, @R0

g. Move the contents of an external memory to A or A to an external memory

i. MOVX A,@R1
ii. MOVX @R0,A

iii. MOVX A,@DPTR

iv. MOVX@DPTR,A

h. Move the contents of program memory to A

i. MOVC A, @A+PC
ii. MOVC A, @A+DPTR
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BMS Institute of Technology, Bangalore 64

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FIG. Addressing Using MOV, MOVX and MOVC

i.

Push and Pop instructions

MOV R6, #25H
MOV R1, #12H
MOV R4, #0F3H

[SP]=07
[R6]=25H
[R1]=12H
[R4]=F3H

//CONTENT OF SP IS 07 (DEFAULT VALUE)

//CONTENT OF R6 IS 25H
//CONTENT OF R1 IS 12H
//CONTENT OF R4 IS F3H

PUSH 6
PUSH 1
PUSH 4

[SP]=08
[SP]=09
[SP]=0A

[08]=[06]=25H //CONTENT OF 08 IS 25H

[09]=[01]=12H //CONTENT OF 09 IS 12H
[0A]=[04]=F3H //CONTENT OF 0A IS F3H

POP 6
POP 1
POP 4

[06]=[0A]=F3H [SP]=09
[01]=[09]=12H [SP]=08
[04]=[08]=25H [SP]=07

//CONTENT OF 06 IS F3H
//CONTENT OF 01 IS 12H
//CONTENT OF 04 IS 25H

j. Exchange instructions
The content of source ie., register, direct memory or indirect memory will be exchanged
with the contents of destination ie., accumulator.
i. XCH A,R3
ii. XCH A,@R1
iii. XCH A,54h

k. Exchange digit. Exchange the lower order nibble of Accumulator (A0-A3) with lower
order nibble of the internal RAM location which is indirectly addressed by the register.
i. XCHD A,@R1
ii. XCHD A,@R0

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BMS Institute of Technology, Bangalore 64

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Arithmetic instructions.
The 8051 can perform addition, subtraction. Multiplication and division operations on 8 bit
numbers.
Addition
In this group, we have instructions to
i. Add the contents of A with immediate data with or without carry.
i. ADD A, #45H
ii. ADDC A, #OB4H
ii. Add the contents of A with register Rn with or without carry.
i. ADD A, R5
ii. ADDC A, R2
iii. Add the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. ADD A, 51H
ii. ADDC A, 75H
iii. ADD A, @R1
iv. ADDC A, @R0
CY AC and OV flags will be affected by this operation.
Subtraction
In this group, we have instructions to
i. Subtract the contents of A with immediate data with or without carry.
i. SUBB A, #45H
ii. SUBB A, #OB4H
ii. Subtract the contents of A with register Rn with or without carry.
i. SUBB A, R5
ii. SUBB A, R2
iii. Subtract the contents of A with contents of memory with or without carry using direct and
indirect addressing
i. SUBB A, 51H
ii. SUBB A, 75H
iii. SUBB A, @R1
iv. SUBB A, @R0
CY AC and OV flags will be affected by this operation.
Multiplication
MUL AB. This instruction multiplies two 8 bit unsigned numbers which are stored in A and B
register. After multiplication the lower byte of the result will be stored in accumulator and higher
byte of result will be stored in B register.
Eg.

MOV A,#45H
MOV B,#0F5H
MUL AB

;[A]=45H
;[B]=F5H
;[A] x [B] = 45 x F5 = 4209
;[A]=09H, [B]=42H

Division

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DIV AB. This instruction divides the 8 bit unsigned number which is stored in A by the 8 bit
unsigned number which is stored in B register. After division the result will be stored in
accumulator and remainder will be stored in B register.
Eg.

MOV A,#45H
MOV B,#0F5H
DIV AB

;[A]=0E8H
;[B]=1BH
;[A] / [B] = E8 /1B = 08 H with remainder 10H

;[A] = 08H, [B]=10H

DA A (Decimal Adjust After Addition).
When two BCD numbers are added, the answer is a non-BCD number. To get the result in BCD, we
use DA A instruction after the addition. DA A works as follows.
If lower nibble is greater than 9 or auxiliary carry is 1, 6 is added to lower nibble.
If upper nibble is greater than 9 or carry is 1, 6 is added to upper nibble.
Eg 1:

Eg 2:

MOV A,#23H
MOV R1,#55H
ADD A,R1
DA A

// [A]=78
// [A]=78

MOV A,#53H
MOV R1,#58H
ADD A,R1
DA A

// [A]=ABh
// [A]=11, C=1 . ANSWER IS 111. Accumulator data is changed after DA A

no changes in the accumulator after da a

Increment: increments the operand by one.

INC A

INC Rn

INC DIRECT

INC @Ri INC DPTR

INC increments the value of source by 1. If the initial value of register is FFh, incrementing the value
will cause it to reset to 0. The Carry Flag is not set when the value "rolls over" from 255 to 0.
In the case of "INC DPTR", the value two-byte unsigned integer value of DPTR is incremented. If the
initial value of DPTR is FFFFh, incrementing the value will cause it to reset to 0.

Decrement: decrements the operand by one.

DEC A

DEC Rn DEC DIRECT

DEC @Ri

DEC decrements the value of source by 1. If the initial value of is 0, decrementing the value will cause
it to reset to FFh. The Carry Flag is not set when the value "rolls over" from 0 to FFh.
Logical Instructions
Logical AND
ANL destination, source:
ANL does a bitwise "AND" operation between source and destination,
leaving the resulting value in destination. The value in source is not affected. "AND" instruction
logically AND the bits of source and destination.
ANL A,#DATA ANL A, Rn
ANL A,DIRECT ANL A,@Ri
ANL DIRECT,A ANL DIRECT, #DATA

Logical OR
ORL destination, source:

ORL does a bitwise "OR" operation between source and destination,

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leaving the resulting value in destination. The value in source is not affected. " OR " instruction
logically OR the bits of source and destination.
ORL A,#DATA ORL A, Rn
ORL A,DIRECT ORL A,@Ri
ORL DIRECT,A ORL DIRECT, #DATA

Logical Ex-OR
XRL destination, source:
XRL does a bitwise "EX-OR" operation between source and
destination, leaving the resulting value in destination. The value in source is not affected. " XRL "
instruction logically EX-OR the bits of source and destination.
XRL A,#DATA XRL A,Rn
XRL A,DIRECT XRL A,@Ri
XRL DIRECT,A XRL DIRECT, #DATA

Logical NOT
CPL complements operand, leaving the result in operand. If operand is a single bit then the state of
the bit will be reversed. If operand is the Accumulator then all the bits in the Accumulator will be
reversed.
CPL A, CPL C,

CPL bit address

SWAP A Swap the upper nibble and lower nibble of A.

Rotate Instructions
RR A
This instruction is rotate right the accumulator. Its operation is illustrated below. Each bit is shifted one
location to the right, with bit 0 going to bit 7.

RL A
Rotate left the accumulator. Each bit is shifted one location to the left, with bit 7 going to bit 0

RRC A
Rotate right through the carry. Each bit is shifted one location to the right, with bit 0 going into the carry bit in
the PSW, while the carry was at goes into bit 7

RLC A
Rotate left through the carry. Each bit is shifted one location to the left, with bit 7 going into the carry bit in
the PSW, while the carry goes into bit 0.

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BMS Institute of Technology, Bangalore 64

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Branch (JUMP) Instructions

Jump and Call Program Range
There are 3 types of jump instructions. They are:1. Relative Jump
2. Short Absolute Jump
3. Long Absolute Jump
Relative Jump
Jump that replaces the PC (program counter) content with a new address that is greater than (the
address following the jump instruction by 127 or less) or less than (the address following the jump
by 128 or less) is called a relative jump. Schematically, the relative jump can be shown as follows: -

The advantages of the relative jump are as follows:1. Only 1 byte of jump address needs to be specified in the 2's complement form, ie. For
jumping ahead, the range is 0 to 127 and for jumping back, the range is -1 to -128.
2. Specifying only one byte reduces the size of the instruction and speeds up program
execution.
3. The program with relative jumps can be relocated without reassembling to generate
absolute jump addresses.
Disadvantages of the absolute jump: 1. Short jump range (-128 to 127 from the instruction following the jump instruction)
Instructions that use Relative Jump
SJMP <relative address>; this is unconditional jump

The remaining relative jumps are conditional jumps

JC <relative address>
JNC <relative address>
JB bit, <relative address>
JNB bit, <relative address>
JBC bit, <relative address>
CJNE <destination byte>, <source byte>, <relative address>
DJNZ <byte>, <relative address>
JZ <relative address>
JNZ <relative address>

Short Absolute Jump

In this case only 11bits of the absolute jump address are needed. The absolute jump address is
calculated in the following manner.
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In 8051, 64 kbyte of program memory space is divided into 32 pages of 2 kbyte each. The
hexadecimal addresses of the pages are given as follows:Page (Hex)

Address (Hex)

00
01
02
03
.
.
1E
1F

0000 - 07FF
0800 - 0FFF
1000 - 17FF
1800 - 1FFF
F000 - F7FF
F800 - FFFF

It can be seen that the upper 5bits of the program counter (PC) hold the page number and the lower
11bits of the PC hold the address within that page. Thus, an absolute address is formed by taking
page numbers of the instruction (from the program counter) following the jump and attaching the
specified 11bits to it to form the 16-bit address.
Advantage: The instruction length becomes 2 bytes.
Example of short absolute jump: ACALL <address 11>
AJMP <address 11>

Long Absolute Jump/Call

Applications that need to access the entire program memory from 0000H to FFFFH use long
absolute jump. Since the absolute address has to be specified in the op-code, the instruction length
is 3 bytes (except for JMP @ A+DPTR). This jump is not re-locatable.
Example: LCALL <address 16>
LJMP <address 16>
JMP @A+DPTR
Another classification of jump instructions is
1. Unconditional Jump
2. Conditional Jump
1.

The unconditional jump is a jump in which control is transferred unconditionally to the target location.
a. LJMP (long jump). This is a 3-byte instruction. First byte is the op-code and second and third
bytes represent the 16-bit target address which is any memory location from 0000 to FFFFH
eg: LJMP 3000H
b. AJMP: this causes unconditional branch to the indicated address, by loading the 11 bit address to
0 -10 bits of the program counter. The destination must be therefore within the same 2K blocks.
c. SJMP (short jump). This is a 2-byte instruction. First byte is the op-code and second byte is the
relative target address, 00 to FFH (forward +127 and backward -128 bytes from the current PC
value). To calculate the target address of a short jump, the second byte is added to the PC value
which is address of the instruction immediately below the jump.

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BMS Institute of Technology, Bangalore 64

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2.

4 Sem ECE

Conditional Jump instructions.

JBC
Jump if bit 1 and clear bit
JNB
Jump if bit 0
JB
Jump if bit 1
JNC
Jump if CY 0
JC
Jump if CY 1
CJNE reg,#data
Jump if byte #data
CJNE A,byte Jump if A byte
DJNZ
Decrement and Jump if A 0
JNZ
Jump if A 0
JZ
Jump if A 0

All conditional jumps are short jumps.

Bit level jump instructions:

Bit level JUMP instructions will check the conditions of the bit and if condition is true, it jumps to the
address specified in the instruction. All the bit jumps are relative jumps.
JB bit, rel
JNB bit, rel
JBC bit, rel

; jump if the direct bit is set to the relative address specified.

; jump if the direct bit is clear to the relative address specified.
; jump if the direct bit is set to the relative address specified and then clear the bit.

Subroutine CALL And RETURN Instructions

Subroutines are handled by CALL and RET instructions
There are two types of CALL instructions
1. LCALL address(16 bit)
This is long call instruction which unconditionally calls the subroutine located at the indicated 16 bit
address. This is a 3 byte instruction. The LCALL instruction works as follows.
a. During execution of LCALL, [PC] = [PC]+3; (if address where LCALL resides is say, 0x3254;
during execution of this instruction [PC] = 3254h + 3h = 3257h
b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08
c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 57 will be stored in memory location 08.
d. [SP]=[SP]+1; (SP increments again and [SP]=09)
e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 32 will be stored in memory location 09.
With these the address (0x3254) which was in PC is stored in stack.
f. [PC]= address (16 bit); the new address of subroutine is loaded to PC. No flags are affected.
2. ACALL address(11 bit)
This is absolute call instruction which unconditionally calls the subroutine located at the indicated 11
bit address. This is a 2 byte instruction. The SCALL instruction works as follows.
a. During execution of SCALL, [PC] = [PC]+2; (if address where LCALL resides is say, 0x8549;
during execution of this instruction [PC] = 8549h + 2h = 854Bh
b. [SP]=[SP]+1; (if SP contains default value 07, then SP increments and [SP]=08
c. [[SP]] = [PC7-0]; (lower byte of PC content ie., 4B will be stored in memory location 08.
d. [SP]=[SP]+1; (SP increments again and [SP]=09)
e. [[SP]] = [PC15-8]; (higher byte of PC content ie., 85 will be stored in memory location 09.
With these the address (0x854B) which was in PC is stored in stack.
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BMS Institute of Technology, Bangalore 64

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f.

[PC10-0]= address (11 bit);

affected.

4 Sem ECE
the new address of subroutine is loaded to PC. No flags are

RET instruction
RET instruction pops top two contents from the stack and load it to PC.
g. [PC15-8] = [[SP]]
;content of current top of the stack will be moved to higher byte of PC.
h. [SP]=[SP]-1; (SP decrements)
i. [PC7-0] = [[SP]] ;content of bottom of the stack will be moved to lower byte of PC.
j. [SP]=[SP]-1; (SP decrements again)
Bit manipulation instructions.
8051 has 128 bit addressable memory. Bit addressable SFRs and bit addressable PORT pins. It is possible to
perform following bit wise operations for these bit addressable locations.
1.

LOGICAL AND
a. ANL C,BIT(BIT ADDRESS)
; LOGICALLY AND CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ANL C, /BIT;
; LOGICALLY AND CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY

2.

LOGICAL OR
a. ORL C,BIT(BIT ADDRESS)
; LOGICALLY OR CARRY AND CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
b. ORL C, /BIT;
; LOGICALLY OR CARRY AND COMPLEMENT OF CONTENT OF BIT ADDRESS, STORE RESULT IN CARRY
CLR bit
a. CLR bit
; CONTENT OF BIT ADDRESS SPECIFIED WILL BE CLEARED.
b. CLR C
; CONTENT OF CARRY WILL BE CLEARED.
CPL bit
a. CPL bit
; CONTENT OF BIT ADDRESS SPECIFIED WILL BE COMPLEMENTED.
b.
CPL C
; CONTENT OF CARRY WILL BE COMPLEMENTED.

3.
4.

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BMS Institute of Technology, Bangalore 64

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UNIT 3
3.1 ASSEMBLER DIRECTIVES.
Assembler directives tell the assembler to do something other than creating the machine code for
an instruction. In assembly language programming, the assembler directives instruct the assembler
to
1. Process subsequent assembly language instructions
2. Define program constants
3. Reserve space for variables
The following are the widely used 8051 assembler directives.
ORG (origin)
The ORG directive is used to indicate the starting address. It can be used only when the
program counter needs to be changed. The number that comes after ORG can be either in
hex or in decimal.
Eg: ORG 0000H

;Set PC to 0000.

EQU and SET

EQU and SET directives assign numerical value or register name to the specified symbol
name.
EQU is used to define a constant without storing information in the memory. The symbol
defined with EQU should not be redefined.
SET directive allows redefinition of symbols at a later stage.
DB (DEFINE BYTE)
The DB directive is used to define an 8 bit data. DB directive initializes memory with 8 bit
values. The numbers can be in decimal, binary, hex or in ASCII formats. For decimal, the 'D'
after the decimal number is optional, but for binary and hexadecimal, 'B' and H are
required. For ASCII, the number is written in quotation marks (LIKE This).
DATA1:
:DATA2:
DATA3:
DATA4:

DB 40H
DB 01011100B
DB 48
DB

'HELLOW

; hex
; binary
; decimal
; ASCII

END
The END directive signals the end of the assembly module. It indicates the end of the
program to the assembler. Any text in the assembly file that appears after the END directive
is ignored. If the END statement is missing, the assembler will generate an error message.

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BMS Institute of Technology, Bangalore 64

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3.2 ASSEMBLY LANGUAGE PROGRAMS.

1. Write a program to add the values of locations 50H and 51H and store the result in locations
in 52h and 53H.
ORG 0000H
; Set program counter 0000H
MOV A,50H
; Load the contents of Memory location 50H into A ADD ADD A,51H
; Add the contents of memory 51H with CONTENTS A
MOV 52H,A
; Save the LS byte of the result in 52H
MOV A, #00
; Load 00H into A
ADDC A, #00
; Add the immediate data and carry to A
MOV 53H,A
; Save the MS byte of the result in location 53h
END
2. Write a program to store data FFH into RAM memory locations 50H to 58H using direct
addressing mode
ORG 0000H
; Set program counter 0000H
MOV A, #0FFH ; Load FFH into A
MOV 50H, A
; Store contents of A in location 50H
MOV 51H, A
; Store contents of A in location 5IH
MOV 52H, A
; Store contents of A in location 52H
MOV 53H, A
; Store contents of A in location 53H
MOV 54H, A
; Store contents of A in location 54H
MOV 55H, A
; Store contents of A in location 55H
MOV 56H, A
; Store contents of A in location 56H
MOV 57H, A
; Store contents of A in location 57H
MOV 58H, A
; Store contents of A in location 58H
END
3. Write a program to subtract a 16 bit number stored at locations 51H-52H from 55H-56H and
store the result in locations 40H and 41H. Assume that the least significant byte of data or the
result is stored in low address. If the result is positive, then store 00H, else store 01H in 42H.
ORG 0000H
; Set program counter 0000H
MOV A, 55H ; Load the contents of memory location 55 into A
CLR C
; Clear the borrow flag
SUBB A,51H ; Sub the contents of memory 51H from contents of A
MOV 40H, A ; Save the LSByte of the result in location 40H
MOV A, 56H ; Load the contents of memory location 56H into A
SUBB A, 52H ; Subtract the content of memory 52H from the content A
MOV 41H,
; Save the MSbyte of the result in location 415.
MOV A, #00
; Load 005 into A
ADDC A, #00 ; Add the immediate data and the carry flag to A
MOV 42H, A ; If result is positive, store00H, else store 0lH in 42H
END

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BMS Institute of Technology, Bangalore 64

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4. Write a program to add two 16 bit numbers stored at locations 51H-52H and 55H-56H and
store the result in locations 40H, 41H and 42H. Assume that the least significant byte of
data and the result is stored in low address and the most significant byte of data or the result
is stored in high address.
ORG 0000H
; Set program counter 0000H
MOV A,51H
; Load the contents of memory location 51H into A
ADD A,55H
; Add the contents of 55H with contents of A
MOV 40H,A
; Save the LS byte of the result in location 40H
MOV A,52H
; Load the contents of 52H into A
ADDC A,56H
; Add the contents of 56H and CY flag with A
MOV 41H,A
; Save the second byte of the result in 41H
MOV A,#00
; Load 00H into A
ADDC A,#00 ; Add the immediate data 00H and CY to A
MOV 42H,A
; Save the MS byte of the result in location 42H
END
5. Write a program to store data FFH into RAM memory locations 50H to 58H using indirect
addressing mode.
ORG 0000H
; Set program counter 0000H
MOV A, #0FFH
; Load FFH into A
MOV RO, #50H
; Load pointer, R0-50H
MOV R5, #08H
; Load counter, R5-08H
Start:MOV @RO, A
; Copy contents of A to RAM pointed by R0
INC RO
; Increment pointer
DJNZ R5, start ; Repeat until R5 is zero
END
6. Write a program to add two Binary Coded Decimal (BCD) numbers stored at locations 60H
and 61H and store the result in BCD at memory locations 52H and 53H. Assume that the
least significant byte of the result is stored in low address.
ORG 0000H
MOV A,60H
ADD A,61H
DA A
MOV 52H, A
MOV A,#00
ADDC A,#00H
MOV 53H,A
END

; Set program counter 00004

; Load the contents of memory location 6.0.H into A
; Add the contents of memory location 61H with contents of A
; Decimal adjustment of the sum in A
; Save the least significant byte of the result in location 52H
; Load 00H into .A
; Add the immediate data and the contents of carry flag to A
; Save the most significant byte of the result in location 53:,

7. Write a program to clear 10 RAM locations starting at RAM address 1000H.

ORG 0000H
;Set program counter 0000H
MOV DPTR, #1000H ;Copy address 1000H to DPTR
CLR A
;Clear A
MOV R6, #0AH
;Load 0AH to R6
again: MOVX @DPTR,A
;Clear RAM location pointed by DPTR
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BMS Institute of Technology, Bangalore 64

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8.

9.

10.

11.

4 Sem ECE

INC DPTR
;Increment DPTR
DJNZ R6, again
;Loop until counter R6=0
END
Write a program to compute 1 + 2 + 3 + N (say N=15) and save the sum at70H
OR G 0000H
; Set program counter 0000H
N EQU 15
M OV R 0,#00
; Clear R0
CLR A
; Clear A
a ga in: INC R 0
; Increment R0
ADD A, R0
; Add the contents of R0 with A
CJNE R 0,#N,aga in ; Loop until counter, R0, N
M OV 70H,A
; Save the result in location 70H END
Write a program to multiply two 8 bit numbers stored at locations 70H and 71H and store the
result at memory locations 52H and 53H. Assume that the least significant byte of the result is
stored in low address.
ORG 0000H ; Set program counter 00 OH
MOV A, 70H ; Load the contents of memory location 70h into A
MOV B, 71H ; Load the contents of memory location 71H into B
MUL AB
; Perform multiplication
MOV 52H,A ; Save the least significant byte of the result in location 52H MOV 53H,B ; Save the most
significant byte of the result in location 53
END
Ten 8 bit numbers are stored in internal data memory from location 5oH. Write a
program to increment the data.
Assume that ten 8 bit numbers are stored in internal data memory from location 50H, hence
R0 or R1 must be used as a pointer.
The program is as follows.
OPT 0000H
MOV R0,#50H
MOV R3,#0AH
Loopl: INC @R0
INC RO
DJNZ R3, loopl END
END
Write a program to find the average of five 8 bit numbers. Store the result in H.
(Assume that after adding five 8 bit numbers, the result is 8 bit only).
ORG 0000H
MOV 40H,#05H
MOV 41H,#55H
MOV 42H,#06H
MOV 43H,#1AH
MOV 44H,#09H
MOV R0,#40H
MOV R5,#05H
MOV B,R5
CLR A
Loop: ADD A,@RO
INC RO

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DJNZ R5,Loop
DIV AB
MOV 55H,A
END
12. Write a program to find the cube of an 8 bit number program is as follows
ORG 0000H
MOV R1,#N
MOV A,R1
MOV B,R1
MUL AB
//SQUARE IS COMPUTED
MOV R2, B
MOV B, R1
MUL AB
MOV 50,A
MOV 51,B
MOV A,R2
MOV B, R1
MUL AB
ADD A, 51H
MOV 51H, A
MOV 52H, B
MOV A, # 00H
ADDC A, 52H
MOV 52H, A
//CUBE IS STORED IN 52H,51H,50H
END
13. Write a program to exchange the lower nibble of data present in external memory 6000H and
6001H
ORG 0000H
M OV DPTR , #6000H
MOVX A, @DPTR
MOV R0, #45H
MOV @RO, A
INC DPL
MOVX A, @DPTR
XCHD A, @R0
MOVX @DPTR, A
DEC DPL
MOV A, @R0
MOVX @DPTR, A
END

;
;
;
;
;
;

; Set program counter 00h

Copy a ddress 6000 H t o DP TR
Copy contents of 60008 to A
Load pointer, R0=45H
Copy cont of A to RAM pointed by 80
Increment pointer
Copy contents of 60018 to A

; Exchange lower nibble of A with RAM pointed by RO

; Copy contents of A to 60018

; Decrement pointer
; Copy cont of RAM pointed by R0 to A
; Copy cont of A to RAM pointed by DPTR

14. Write a program to count the number of and o's of 8 bit data stored in location 6000H.
ORG 00008
MOV DPTR, #6000h
MOVX A, @DPTR
MOV R0,#08
MOV R2,#00
MOV R3,#00
CLR C
BACK: RLC A

; Set program counter 00008

; Copy address 6000H to DPTR
; Copy number to A
; Copy 08 in RO
; Copy 00 in R2
; Copy 00 in R3
; Clear carry flag
; Rotate A through carry flag

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JC NEXT
; If CF = 1, branch to next
INC R2
; I f C F = 0 , i n c r e m e n t R 2 AJMP NEXT2
NEXT: INC R3
; If CF = 1, increment R3
NEXT2: DJNZ RO,BACK
; Repeat until RO is zero
END
15. Write a program to shift a 24 bit number stored at 57H-55H to the left logically four places.
Assume that the least significant byte of data is stored in lower address.
ORG 0000H
; Set program counter 0000h
MOV R1,#04 ; Set up loop count to 4
again: MOV A,55H
; Place the least significant byte of data in A
CLR C
; Clear tne carry flag
RLC A
; Rotate contents of A (55h) left through carry
MOV 55H,A
MOV A,56H
RLC A
; Rotate contents of A (56H) left through carry
MOV 56H,A
MOV A,57H
RLC A
; Rotate contents of A (57H) left through carry
MOV 57H,A
DJNZ R1,again ; Repeat until R1 is zero
END

16. Two 8 bit numbers are stored in location 1000h and 1001h of external data memory.
Write a program to find the GCD of the numbers and store the result in 2000h.
ALGORITHM

Step 1
Step 2
Step 3
Step 4
Step 5
Step 6
Step 7
Step 8
Step 9

:Initialize external data memory with data and DPTR with address
:Load A and TEMP with the operands
:Are the two operands equal? If yes, go to step 9
:Is (A) greater than (TEMP) ? If yes, go to step 6
:Exchange (A) with (TEMP) such that A contains the bigger number
:Perform division operation (contents of A with contents of TEMP)
:If the remainder is zero, go to step 9
:Move the remainder into A and go to step 4
:Save the contents 'of TEMP in memory and terminate the program

ORG 0000H
; Set program counter 0000H
TEMP EQU 70H
TEMPI EQU 71H
MOV DPTR, #1000H
; Copy address 100011 to DPTR
MOVX A, @DPTR
; Copy First number to A
MOV TEMP, A
; Copy First number to temp INC DPTR
MOVX A, @DPTR
; Copy Second number to A
LOOPS: CJNE A, TEMP, LOOP1 ; (A) /= (TEMP) branch to LOOP1
AJMP LOOP2
; (A) = (TEMP) branch to L00P2
LOOP1:
JNC LOOP3
; (A) > (TEMP) branch to LOOP3
NOV TEMPI, A
; (A) < (TEMP) exchange (A) with (TEMP)
MOV A, TEMP
MOV TEMP, TEMPI
LOOP3:
MOV B, TEMP
DIV AB
; Divide (A) by (TEMP)
MOV A, B
; Move remainder to A
CJNE A,#00, LOOPS
; (A)/=00 branch to LOOPS
LOOP2:
MOV A, TEMP
MOV DPTR, #2000H
MOVX @DPTR, A
; Store the result in 2000H
END
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UNIT 5
5.1 BASICS OF INTERRUPTS.
During program execution if peripheral devices needs service from microcontroller, device will
generate interrupt and gets the service from microcontroller. When peripheral device activate the
interrupt signal, the processor branches to a program called interrupt service routine. After
executing the interrupt service routine the processor returns to the main program.
Steps taken by processor while processing an interrupt:
1.
2.
3.
4.
5.

It completes the execution of the current instruction.

PSW is pushed to stack.
PC content is pushed to stack.
Interrupt flag is reset.
PC is loaded with ISR address.

ISR will always ends with RETI instruction. The execution of RETI instruction results in the
following.
1. POP the current stack top to the PC.
2. POP the current stack top to PSW.
Classification of interrupts.
1. External and internal interrupts.
External interrupts are those initiated by peripheral devices through the external pins of
the microcontroller.
Internal interrupts are those activated by the internal peripherals of the microcontroller
like timers, serial controller etc.)
2. Maskable and non-maskable interrupts.
The category of interrupts which can be disabled by the processor using program is called
maskable interrupts.
Non-maskable interrupts are those category by which the programmer cannot disable it
using program.
3. Vectored and non-vectored interrupt.
Starting address of the ISR is called interrupt vector. In vectored interrupts the starting
address is predefined. In non-vectored interrputs, the starting address is provided by the
peripheral as follows.
Microcontroller receives an interrupt request from external device.
Controller sends an acknowledgement (INTA) after completing the execution of
current instruction.
The peripheral device sends the interrupt vector to the microcontroller.
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5.2 8051 INTERRUPT STRUCTURE.

8051 has five interrupts. They are maskable and vectored interrupts. Out of these five, two are
external interrupt and three are internal interrupts.

Interrupt source

Type

Vector address Priority

External interrupt 0 External

0003

Timer 0 interrupt

Internal

000B

External interrupt 1 External

0013

Timer 1 interrupt

Internal

001B

Serial interrupt

Internal

0023

Highest

Lowest

8051 makes use of two registers to deal with interrupts.

1. IE Register
This is an 8 bit register used for enabling or disabling the interrupts. The structure of IE
register is shown below.

2. IP Register.
This is an 8 bit register used for setting the priority of the interrupts.

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5.2 TIMERS AND COUNTERS

Timers/Counters are used generally for
Time reference
Creating delay
Wave form properties measurement
Periodic interrupt generation
Waveform generation
8051 has two timers, Timer 0 and Timer 1.

Timer in 8051 is used as timer, counter and baud rate generator. Timer always counts up
irrespective of whether it is used as timer, counter, or baud rate generator: Timer is always
incremented by the microcontroller. The time taken to count one digit up is based on master clock
frequency.
If Master CLK=12 MHz,
Timer Clock frequency = Master CLK/12 = 1 MHz
Timer Clock Period = 1micro second
This indicates that one increment in count will take 1 micro second.

The two timers in 8051 share two SFRs (TMOD and TCON) which control the timers, and each timer
also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).
The following are timer related SFRs in 8051.
SFR Name
TH0
TL0
TH1
TL1
TCON
TMOD

Description
Timer 0 High Byte
Timer 0 Low Byte
Timer 1 High Byte
Timer 1 Low Byte
Timer Control
Timer Mode

SFR Address
8Ch
8Ah
8Dh
8Bh
88h
89h

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TMOD Register

TCON Register

Timer/ Counter Control Logic.

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TIMER MODES
Timers can operate in four different modes. They are as follows
Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows.

Fig. Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.Upper 3 bits of TLX are
ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt is
generated. The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0,
the counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the
counter is controlled by input. This mode is useful to measure the width of a given pulse fed to
input.
Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in 16-bit
mode.

Fig: Operation of Timer in Mode 1

Timer Mode-2: (Auto-Reload Mode): This is a 8 bit counter/timer operation. Counting is
performed in TLX while THX stores a constant value. In this mode when the timer overflows i.e. TLX
becomes FFH, it is fed with the value stored in THX. For example if we load THX with 50H then the

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timer in mode 2 will count from 50H to FFH. After that 50H is again reloaded. This mode is useful in
applications like fixed time sampling.

Fig: Operation of Timer in Mode 2

Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0.
Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.

Fig: Operation of Timer in Mode 3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and TF0
are available to Timer-0 lower 8 bits(TL0).

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5.2 PROGRAMMING 8051 TIMERS IN ASSEMBLY

In order to program 8051 timers, it is important to know the calculation of initial count value to be
stored in the timer register. The calculations are as follows.
In any mode, Timer Clock period =
1/Timer Clock Frequency.
=
1/(Master Clock Frequency/12)
a. Mode 1 (16 bit timer/counter)
Value to be loaded in decimal = 65536 (Delay Required/Timer clock period)
Convert the answer into hexadecimal and load onto THx and TLx register.
(65536D = FFFFH+1)

b. Mode 0 (13 bit timer/counter)

Value to be loaded in decimal = 8192 (Delay Required/Timer clock period)
Convert the answer into hexadecimal and load onto THx and TLx register.
(8192D = 1FFFH+1)

c. Mode 2 (8 bit auto reload)

Value to be loaded in decimal = 256 (Delay Required/Timer clock period)
Convert the answer into hexadecimal and load onto THx register. Upon starting the
timer this value from THx will be reloaded to TLx register.
(256D = FFH+1)

Steps for programming timers in 8051

Mode 1:
Load the TMOD value register indicating which timer (0 or 1) is to be used and
which timer mode is selected.
Load registers TL and TH with initial count values.
Start the timer by the instruction SETB TR0 for timer 0 and SETB TR1 for timer 1.
Keep monitoring the timer flag (TF) with the JNB TFx,target instruction to see if it
is raised. Get out of the loop when TF becomes high.
Stop the timer with the instructions CLR TR0 or CLR TR1, for timer 0 and timer
1, respectively.
Clear the TF flag for the next round with the instruction CLR TF0 or CLR TF1, for
timer 0 and timer 1, respectively.
Go back to step 2 to load TH and TL again.
Mode 0:
The programming techniques mentioned here are also applicable to counter/timer
mode 0. The only difference is in the number of bits of the initialization value.
Mode 2:
Load the TMOD value register indicating which timer (0 or 1) is to be used; select
timer mode 2.
Load TH register with the initial count value. As it is an 8-bit timer, the valid range
is from 00 to FFH.
Start the timer.
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Keep monitoring the timer flag (TFx) with the JNB TFx,target instruction to see if it
is raised. Get out of the loop when TFx goes high.
Clear the TFx flag.
Go back to step 4, since mode 2 is auto-reload.

1. Write a program to continuously generate a square wave of 2 kHz frequency on pin

P1.5 using timer 1. Assume the crystal oscillator frequency to be 12 MHz.
The period of the square wave is T = 1/(2 kHz) = 500 s. Each half pulse = 250 s.
The value n for 250 s is: 250 s /1 s = 250
65536 - 250 = FF06H.
TL = 06H and TH = 0FFH.
MOV TMOD,#10
;Timer 1, mode 1
AGAIN:
MOV TL1,#06H
;TL0 = 06H
MOV TH1,#0FFH ;TH0 = FFH
SETB TR1
;Start timer 1
BACK:
JNB TF1,BACK
;Stay until timer rolls over
CLR TR1
;Stop timer 1
CPL P1.5
;Complement P1.5 to get Hi, Lo
CLR TF1
;Clear timer flag 1
SJMP AGAIN
;Reload timer
2. Write a program segment that uses timer 1 in mode 2 to toggle P1.0 once whenever the
counter reaches a count of 100. Assume the timer clock is taken from external
source P3.5 (T1).
The TMOD value is 60H
The initialization value to be loaded into TH1 is
256 - 100 = 156 = 9CH

BACK: JNB

MOV TMOD,#60h ;Counter1, mode 2, C/T= 1

MOV TH1,#9Ch
;Counting 100 pulses
SETB P3.5
;Make T1 input
SETB TR1
;Start timer 1
TF1,BACK
;Keep doing it if TF = 0
CPL P1.0
;Toggle port bit
CLR TF1
;Clear timer overflow flag
SJMP BACK
;Keep doing it

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UNIT 6
6.1 SERIAL COMMUNICATION.
6.1.1. DATA COMMUNICATION
The 8051 microcontroller is parallel device that transfers eight bits of data simultaneously
over eight data lines to parallel I/O devices. Parallel data transfer over a long is very expensive.
Hence, a serial communication is widely used in long distance communication. In serial data
communication, 8-bit data is converted to serial bits using a parallel in serial out shift register and
then it is transmitted over a single data line. The data byte is always transmitted with least
significant bit first.
6.1.2. BASICS OF SERIAL DATA COMMUNICATION,
Communication Links
1. Simplex communication link: In simplex transmission, the line is dedicated for transmission.
The transmitter sends and the receiver receives the data.
Transmitter

Receiver

2. Half duplex communication link: In half duplex, the communication link can be used for either
transmission or
reception. Data is transmitted in only one direction at a time.
Transmitter

Receiver

Receiver

Transmitter

3. Full duplex communication link: If the data is transmitted in both ways at the same time, it is a
full duplex i.e. transmission and reception can proceed simultaneously. This communication link
requires two wires for data, one for transmission and one for reception.
Transmitter

Receiver

Receiver

Transmitter

Types of Serial communication:

Serial data communication uses two types of communication.
1. Synchronous serial data communication: In this transmitter and receiver are synchronized. It
uses a common clock to synchronize the receiver and the transmitter. First the synch character is
sent and then the data is transmitted. This format is generally used for high speed transmission. In
Synchronous serial data communication a block of data is transmitted at a time.
Transmitter

Sync

Receiver

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Data
Clock

2. Asynchronous Serial data transmission: In this, different clock sources are used for transmitter
and receiver. In this mode, data is transmitted with start and stop bits. A transmission begins with
start bit, followed by data and then stop bit. For error checking purpose parity bit is included just
prior to stop bit. In Asynchronous serial data communication a single byte is transmitted at a time.
Transmitter

Start D0 D1 D2 D3 D4 D5 D6 D7 D8 Stop

Receiver

Data
Clock 1
Clock2
Baud rate:
The rate at which the data is transmitted is called baud or transfer rate. The baud rate is the
reciprocal of the time to send one bit. In asynchronous transmission, baud rate is not equal to
number of bits per second. This is because; each byte is preceded by a start bit and followed by
parity and stop bit. For example, in synchronous transmission, if data is transmitted with 9600
baud, it means that 9600 bits are transmitted in one second. For bit transmission time = 1 second/
9600 = 0.104 ms.
6.1.3. 8051 SERIAL COMMUNICATION
The 8051 supports a full duplex serial port.
Three special function registers support serial communication.
1. SBUF Register: Serial Buffer (SBUF) register is an 8-bit register. It has separate SBUF
registers for data transmission and for data reception. For a byte of data to be transferred
via the TXD line, it must be placed in SBUF register. Similarly, SBUF holds the 8-bit data
received by the RXD pin and read to accept the received data.
2. SCON register: The contents of the Serial Control (SCON) register are shown below. This
register contains mode selection bits, serial port interrupt bit (TI and RI) and also the ninth
data bit for transmission and reception (TB8 and RB8).

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3. PCON register: The SMOD bit (bit 7) of PCON register controls the baud rate in
asynchronous mode transmission.

6.1.4. SERIAL COMMUNICATION MODES

1. Mode 0
In this mode serial port runs in synchronous mode. The data is transmitted and received
through RXD pin and TXD is used for clock output. In this mode the baud rate is 1/12 of
clock frequency.
2. Mode 1
In this mode SBUF becomes a 10 bit full duplex transceiver. The ten bits are 1 start bit, 8
data bit and 1 stop bit. The interrupt flag TI/RI will be set once transmission or reception is
over. In this mode the baud rate is variable and is determined by the timer 1 overflow rate.
Baud rate
=
[2smod/32] x Timer 1 overflow Rate
=
[2smod/32] x [Oscillator Clock Frequency] / [12 x [256 [TH1]]]
3. Mode 2
This is similar to mode 1 except 11 bits are transmitted or received. The 11 bits are, 1 start
bit, 8 data bit, a programmable 9th data bit, 1 stop bit.
Baud rate
=
[2smod/64] x Oscillator Clock Frequency
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4. Mode 3
This is similar to mode 2 except baud rate is calculated as in mode 1
6.1.5. CONNECTIONS TO RS-232
RS-232 standards:
To allow compatibility among data communication equipment made by various
manufactures, an interfacing standard called RS232 was set by the Electronics Industries
Association (EIA) in 1960. Since the standard was set long before the advent of logic family, its
input and output voltage levels are not TTL compatible.
In RS232, a logic one (1) is represented by -3 to -25V and referred as MARK while logic zero
(0) is represented by +3 to +25V and referred as SPACE. For this reason to connect any RS232 to a
microcontroller system we must use voltage converters such as MAX232 to convert the TTL logic
level to RS232 voltage levels and vice-versa. MAX232 IC chips are commonly referred as line
drivers.
In RS232 standard we use two types of connectors. DB9 connector or DB25 connector.

DB9 Male Connector

DB25 Male Connector

The pin description of DB9 and DB25 Connectors are as follows

The 8051 connection to MAX232 is as follows.

The 8051 has two pins that are used specifically for transferring and receiving data serially. These
two pins are called TXD, RXD. Pin 11 of the 8051 (P3.1) assigned to TXD and pin 10 (P3.0) is
designated as RXD. These pins TTL compatible; therefore they require line driver (MAX 232) to
make them RS232 compatible. MAX 232 converts RS232 voltage levels to TTL voltage levels and
vice versa. One advantage of the MAX232 is that it uses a +5V power source which is the same as
the source voltage for the 8051. The typical connection diagram between MAX 232 and 8051 is
shown below.

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6.1.6. SERIAL COMMUNICATION PROGRAMMING IN ASSEMBLY AND C.

Steps to programming the 8051 to transfer data serially
1. The TMOD register is loaded with the value 20H, indicating the use of the Timer 1 in
mode 2 (8-bit auto reload) to set the baud rate.
2. The TH1 is loaded with one of the values in table 5.1 to set the baud rate for serial
data transfer.
3. The SCON register is loaded with the value 50H, indicating serial mode 1, where an
8-bit data is framed with start and stop bits.
4. TR1 is set to 1 start timer 1.
5. TI is cleared by the CLR TI instruction.
6. The character byte to be transferred serially is written into the SBUF register.
7. The TI flag bit is monitored with the use of the instruction JNB TI, target to see if the
character has been transferred completely.
8. To transfer the next character, go to step 5.
Example 1. Write a program for the 8051 to transfer letter A serially at 4800- baud rate, 8 bit data,
1 stop bit continuously.
ORG 0000H
LJMP START
ORG 0030H
START: MOV TMOD, #20H
MOV TH1, #0FAH
MOV SCON, #50H

; select timer 1 mode 2

; load count to get baud rate of 4800
; initialize UART in mode 2
; 8 bit data and 1 stop bit
SETB TR1
; start timer
AGAIN: MOV SBUF, #'A'
; load char A in SBUF
BACK: JNB TI, BACK ; Check for transmit interrupt flag
CLR TI
; Clear transmit interrupt flag
SJMP AGAIN
END
Example 2. Write a program for the 8051 to transfer the message EARTH serially at 9600 baud, 8
bit data, 1 stop bit continuously.
ORG 0000H
LJMP START
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ORG 0030H
START: MOV TMOD, #20H
MOV TH1, #0FDH
MOV SCON, #50H
SETB TR1
LOOP: MOV A, #'E'
ACALL LOAD
MOV A, #'A'
ACALL LOAD
MOV A, #'R'
ACALL LOAD
MOV A, #'T'
ACALL LOAD
MOV A, #'H'
ACALL LOAD
SJMP LOOP

4 Sem ECE

; select timer 1 mode 2

; load count to get reqd. baud rate of 9600
; initialise uart in mode 2
; 8 bit data and 1 stop bit
; start timer
; load 1st letter E in a
; call load subroutine
; load 2nd letter A in a
; call load subroutine
; load 3rd letter R in a
; call load subroutine
; load 4th letter T in a
; call load subroutine
; load 4th letter H in a
; call load subroutine
; repeat steps

LOAD: MOV SBUF, A

HERE: JNB TI, HERE ; Check for transmit interrupt flag
CLR TI
; Clear transmit interrupt flag
RET
END
6.2 8255A PROGRAMMABLE PERIPHERAL INTERFACE
Introduction
The 8255A programmable peripheral interface (PPI) implements a general-purpose I/O interface to
connect peripheral equipment to a microcomputer system bus.
Features
Three 8-bit Peripheral Ports - Ports A, B, and C
Three programming modes for Peripheral Ports: Mode 0 (Basic Input/Output), Mode 1
(Strobed Input/Output), and Mode 2 (Bidirectional)
Total of 24 programmable I/O lines
8-bit bidirectional system data bus with standard microprocessor interface controls
6.2.1. ARCHITECTURE OF 8255A

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Read/Write Control Logic has six connections.

Read, Write: This control signal enables the Read/Write operation. When the signal is low, the
controller reads/writes data from/to a selected I/O Port of the 8255.
RESET: This is an active high signal; it clears the control register and sets all ports in the input
mode.
CS, A0 and A1: Theses are device select signals. Chip Select is connected to a decoded address, and
A0 and A1 are generally connected to MPU address lines A0 and A1 respectively

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Control register is an 8 bit register. The contents of this register called control word. This register
can be accessed to write a control word when A0 and A1 are at logic 1. This control register is not
accessible for a read operation.
Bit D7 of the control register specifies either I/O function or the Bit Set/Reset function. If bit
D7=1, bits D6-D0 determines I/O functions in various modes. If bit D7=0, Port C operates in the Bit
Set/Reset (BSR) mode. The BSR control word does not affect the functions of Port A and Port B.

6.2.2. I/O ADDRESSING

8051 can be interfaced with the processor by two methods
Isolated I/O, I/O mapped I/O.
In this addressing method, IN,OUT instructions (microprocessors) are used to access the
input/output devices.
Memory mapped I/O.
The instructions used to access the memory itself will be used for accessing I/O devices. The
I/O devices are connected to the addresses where it can be accessed using simple memory
accessing mechanism.

ADDITIONAL NOTES
THEORY RELATED TO ADC
ADC Devices:

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Analog to digital converters are among the most widely used devices for data acquisitions. Digital
computers use binary (discrete) value but in physical world everything is analog (continuous). A
physical
quantity is converted to electrical signals using device called transducer or also called as sensors.
Sensors and many other natural quantities produce an output that is voltage (or current). Therefore
we need an
analog - to - digital converter to translate the analog signal to digital numbers so that the
microcontroller can read and process them.
An ADC has an n bit resolution where n can be 8, 10, 16, 0r even 24 bits. The higher resolution ADC
provides a smaller step size, where step size is smallest change that can be discerned by an ADC.
This is shown below.

In addition to resolution, conversion time is another major factor in judging an ADC. Conversion
time is defined as the time it takes the ADC to convert the analog input to digital (binary) number.
The ADC chips are either parallel or serial. In parallel ADC, we have 8 or more pins dedicated to
bring out the binary data, but in serial ADC we have only one pin for data out.
ADC 0808

ADC0808, has 8 analog inputs. ADC0808 allows us to monitor up to 8 different analog inputs using
only a single chip. ADC0808 has an 8-bit data output. The 8 analog inputs channels are multiplexed
and selected according to table given below using three address pins, A, B, and C.

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In ADC0808 Vref (+) and Vref (-) set the reference voltage. If Vref (-) = Gnd and Vref (+) = 5V, the
step size is 5V/ 256 = 19.53 mV. Therefore,to get a 10 mV step size we need to set Vref (+) = 2.56V
and Vref(-) = Gnd. ALE is used to latch in the address. SC for start conversion. EOC is for end-ofconversion, and OE is for output enable (READ). Table shows the step size relation to the Vref
Voltage.

Steps to access data from ADC0808

1. Select an analog channel by providing bits to A, B, and C addresses according to table.
2. Activate the ALE (address latch enable) pin. It needs an L-to-H pulse to latch in the address.
3. Activate SC (start conversion) by an L-to-H pulse to initiate conversion.
4. Monitor EOC (end of conversion) to see whether conversion is finished. H-to-l output
indicates that data is converted and ready to be picked up.
5. Activate OE (output enable) to read data out of ADC chip. An L-to-H pulse to the OE pin will
bring digital data out of the chip. Also notice that the OE is the same as the RD pin in other
ADC chip.
6. Notice that in ADC0808 there is no self-clocking and the clock must be provided from an
external source to the CLK pin. Although the speed of conversion depends on the frequency
of the clock connected to the CLK pin, it cannot be faster than 100 microseconds.

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UNIT 7: Motivation for MSP430microcontrollers

Low Power embedded systems, On-chip
peripherals (analog and digital), low-power RF
capabilities. Target applications (Single-chip, low
cost, low power, high performance system design). 2
Hrs
MSP430 RISC CPU architecture, Compiler-friendly
features, Instruction set, Clock system, Memory
subsystem. Key differentiating factors between
different MSP430 families. 2 Hrs.
Introduction to Code Composer Studio (CCS v4).
Understanding how to use CCS for Assembly, C,
Assembly+C projects for MSP430 microcontrollers.
Interrupt programming. 3 Hrs

Digital I/O I/O ports programming using C and

assembly, Understanding the muxing scheme of the
MSP430 pins. 2 Hrs
UNIT 8: On-chip peripherals. Watchdog Timer,
Comparator, Op-Amp, Basic Timer, Real Time Clock
(RTC), ADC, DAC, SD16, LCD, DMA. 2 Hrs
Using Low-power features of MSP430. Clock system,
low-power modes, Clock request feature, Lowpower programming and Interrupt. 2 Hrs
Interfacing LED, LCD, External memory. Seven
segment LED modules interfacing. Example Realtime clock. 2 Hrs
Case Studies of applications of MSP430 - Data
acquisition system, Wired Sensor network, Wireless
sensor network with Chipcon RF interfaces. 3 Hrs

LOW POWER EMBEDDED SYSTEMS

1. EMBEDDED SYSTEM DESIGN CYCLE
Market requirements > Functional Specification> Architecture > Component Design > System Integration >
Testing
2. NEED FOR LOW-POWER EMBEDDED SYSTEMS
a. Why Low-Power is important
Longer battery life
Smaller products
Simpler power supplies
Less EMI simplifies PCB
Permanent battery
Environmental Stewardship
b. Examples of low power applications
RFID based forest monitoring
Structural monitoring
Wildlife habitat monitoring
3. POWER AWARE ARCHITECTURE
a. Sources of power consumption
o Dynamic power: Charging and discharging of capacitors and on switching activity
o Short circuit power
o Leakage - leaking diodes and transistors
b. Trade-off between power and speed.
o Power consumption of CMOS circuits (ignoring leakage), P = C LV2dd f,
Where, = parameter on switching activity, C = load capacitance, V dd = supply voltage, f =
frequency
o Decreasing voltage reduces power consumption(quadratically)
o Higher supply voltages reduce delay but increase power consumption (due to quadratic
relation)
c. Power saving techniques
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Trade-off performance to save power

o Reduce power supply voltage
o Reduce frequency
Structural power saving techniques
o Disable peripheral when not in use (E.g. Clock Gating)
o Disconnect modules from power supply when not in use (E.g. Power Gating)
o Clock gating Deactivate clocks to unused registers
o Signal gating Deactivate signals that cause activity if not in use
o Power gating Deactivate Vdd for unused HW blocks

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Pin diagram of the MSP430F2003 and F2013

4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.

VCC and VSS are the supply voltage and ground for the whole device (the analog and digital supplies
are separate in the 16-pin package).
P1.0P1.7, P2.6, and P2.7 are for digital input and output, grouped into ports P1 and P2.
TACLK, TA0, and TA1 are associated with Timer_A; TACLK can be used as the clock input to the timer,
while TA0 and TA1 can be either inputs or outputs. These can be used on several pins because of the
importance of the timer.
A0, A0+, and so on, up to A4, are inputs to the analog-to-digital converter. It has four differential
channels, each of which has negative and positive inputs. VREF is the reference voltage for the
converter.
ACLK and SMCLK are outputs for the microcontrollers clock signals. These can be used to supply a
clock to external components or for diagnostic purposes.
SCLK, SDO, and SCL are used for the universal serial interface, which communicates with external
devices using the serial peripheral interface (SPI) or inter-integrated circuit (I2C) bus.
XIN and XOUT are the connections for a crystal, which can be used to provide an accurate, stable
clock frequency.
RST is an active low reset signal. Active low means that it remains high near VCC for normal operation
and is brought low near VSS to reset the chip. Alternative notations to show the active low nature are
_RST and /RST.
NMI is the non-maskable interrupt input, which allows an external signal to interrupt the normal
operation of the program.
TCK, TMS, TCLK, TDI, TDO, and TEST form the full JTAG interface, used to program and debug the
device.
SBWTDIO and SBWTCK provide the Spy-Bi-Wire interface, an alternative to the usual JTAG
connection that saves pins.
Architecture of MSP 430
Block diagram of the MSP430F2003 and F2013, taken from data sheet.

The main features of the MSP RISC CPU architecture are,

1. On the left is the CPU and its supporting hardware, including the clock generator. The emulation,
JTAG interface and Spy-Bi-Wire are used to communicate with a desktop computer when
downloading a program and for debugging
2. Clock generator generates up to three different clocks (MCLK, ACLK & SMCLK) using four different
sources (VCO, DCO, LFXT1 and XT2).
3. The main blocks are linked by the memory address bus (MAB) and memory data bus (MDB).
4. These devices have flash memory, 1KB in the F2003 or 2KB in the F2013, and 128 bytes of RAM.
5. Six blocks are shown for peripheral functions (there are many more in larger devices).
a. Input/output ports,
b. Timer_A,
c. Watchdog timer (resets the processor if program becomes stuck in the infinite loop).
d. The universal serial interface (USI) (SPI, I2C, RS232, USB, CAN etc)
e. Sigmadelta analog-to-digital converter (SD16_A)
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The brownout protection comes into action if the supply voltage drops to a dangerous level. Most
devices include this but not some of the MSP430x1xx family.
There are ground and power supply connections. Ground is labeled VSS and is taken to define 0V.
The supply connection is VCC which is mostly in the range of 1.83.6V.

REGISTERS OF MSP 430

MSP 430 has sixteen 16-bit registers. These registers do not have address in the main memory map.
First four registers have dedicated alternate functions and the remaining 12 registers are used as working
registers for general purposes.
R0/PC (PROGRAM COUNTER)
R8 (GENERAL PURPOSE)
R1/SP (STACK POINTER)
R9 (GENERAL PURPOSE)
R2/SR (STATUS REGISTER)
R10 (GENERAL PURPOSE)
R3/CG (CONSTANT GENERATOR)
R11 (GENERAL PURPOSE)
R4 (GENERAL PURPOSE)
R12 (GENERAL PURPOSE)
R5 (GENERAL PURPOSE)
R13 (GENERAL PURPOSE)
R6 (GENERAL PURPOSE)
R14 (GENERAL PURPOSE)
R7 (GENERAL PURPOSE)
R15 (GENERAL PURPOSE)

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Program counter, PC: This contains the address of the next instruction to be executed
Stack pointer, SP: MSP430 uses the top (high addresses) of the main RAM as stack memory. The stack
pointer holds the address of the most recently added word and is automatically adjusted as the stack grows
downward in memory or shrinks upward.
Status register, SR: This contains a set of flags (single bits), whose functions fall into three categories.
The most commonly used flags are C, Z, N, and V, which give information about the result of the last
arithmetic or logical operation. The Z flag is set if the result was zero and cleared if it was nonzero, for
instance. Setting the GIE bit enables maskable interrupts. The final group of bits is CPUOFF, OSCOFF, SCG0,
and SCG1, which control the mode of operation of the MCU. All systems are active when all bits are clear.
Constant generator: This provides the six most frequently used values so that they need not be fetched from
memory whenever they are needed. It uses both R2 and R3 to provide a range of useful values by exploiting
the CPUs addressing modes.
General purpose registers: The remaining 12 registers, R4R15, are general working registers. They may be
used for either data or addresses because both are 16-bit values, which simplify the operation significantly.
COMPILER FRIENDLY FEATURES
MSP430 stems from its recent introduction is that it is designed with compilers in mind. Most small
microcontrollers are now programmed in C, and it is important that a compiler can produce compact, efficient
code. The MSP430 has 16 registers in its CPU, which enhances efficiency because they can be used for local
variables, parameters passed to subroutines, and either addresses or data. This is a typical feature of a RISC,
but unlike a pure RISC, it can perform arithmetic directly on values in main memory. Microcontrollers
typically spend much of their time on such operations.
MEMORY ADDRESS SPACE

The MSP430 von Neumann architecture has one address space shared with
o special function registers (SFRs),
o peripherals,
o RAM, and
o Flash/ROM memory
Code access are always performed on even addresses.

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Data can be accessed as bytes or words.

The addressable memory space is 64 KB
Flash/ROM
The start address depends on the amount of Flash/ROM present and varies by device.
The end address is 0FFFFh for devices with less than 60kB of Flash/ROM; otherwise, it is device
dependent.
Flash can be used for both code and data.
Word or byte tables can be stored and used without the need to copy the tables to RAM before using
them.
The interrupt vector table is mapped into the upper 16 words of address space, with the highest
priority interrupt vector at address (0FFFEh).
RAM
RAM starts at 0200h.
End address depends on the amount of RAM present and varies by device.
RAM can be used for both code and data.
Peripheral Modules
0100 to 01FFh is reserved for 16-bit peripheral modules.
Accessed with word instructions.
If Byte instructions are used ,then high byte of the result is always 0.
010h to 0FFh is reserved for 8-bit peripheral modules.
These modules should be accessed with byte instructions.
Accessed using word instructions results in unpredictable data in the high byte.
If word data is written to a byte module only the low byte is written into the peripheral register,
ignoring the high byte.
SFRs
Peripheral functions are configured in the SFRs.
Located in the lower 16 bytes of the address space and are organized by byte.
SFRs must be accessed using byte instructions only
ADDRESSING MODES
1. Register addressing mode. The address is formed by adding a constant base address to the
contents of a CPU register; the value in the register is not changed.
Eg:
MOV R10, R11
Length: One or two words
Operation: Move the content of R10 to R11. R10 is not affected.
Before:
After:
R10 - 0A023h
R10 - 0A023h
R11 - 0FA15h
R11 - 0A023h
PC - PC old
PC - PC old + 2
2. Indexed addressing mode. In this case the program counter PC is used as the base address, so the
constant is the offset to the data from the PC.
Eg:
MOV 2(R5),6(R6)
Length: 2 or 3 words
Operation: Move the contents of the source address (contents of R5 + 2) to the destination
address (contents of R6 + 6).
3. Symbolic Mode (PC Relative)
In this case the program counter PC is used as the base address, so the constant is the offset to the
data from the PC
Eg:
MOV EDE,TONI
Length: Two or three words
Operation: Move the contents of the source address EDE (contents of PC + X) to the
destination address TONI (contents of PC + Y).
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4. Absolute Mode: The constant in this form of indexed addressing is the absolute address of the data.
This is already the complete address required so it should be added to a register that contains 0.
Absolute addressing is shown by the prefix & and should be used for special function and peripheral
registers, whose addresses are fixed in the memory map.
Eg:
mov.b &P1IN ,R6 ;
copies the port 1 input register into register R6
5. Indirect Register Mode:
Eg:
MOV @R10,0(R11)
Operation: Move the contents of the source whose address is in (R10) to the destination
address (R11). Indirect addressing cannot be used for the destination.
6. Indirect Auto increment Mode:
This is available only for the source and is shown by the
symbol @ in front of a register with a + sign after it, such as @R5+. It uses the value in R5 as a pointer
and automatically increments it afterward by 1 if a byte has been fetched or by 2 for a word.
Eg:
MOV @R10+,0(R11)
7. Immediate Mode
Eg:
MOV #45h,TONI: Operation: Move the immediate constant 45h, which is contained in the
word following the instruction, to destination address TONI. When fetching the source, the program
counter points to the word following the instruction and moves the contents to the destination.

CLOCK SYSTEM
Figure below shows a simplified diagram of the Basic Clock Module+ (BCM+) for the MSP430F2xx
family. The clock module provides three outputs:
Master clock, MCLK is used by the CPU and a few peripherals.
Sub-system master clock, SMCLK is distributed to peripherals.
Auxiliary clock, ACLK is also distributed to peripherals.
Most peripherals can choose either SMCLK, which is often the same as MCLK and in the megahertz
range, or ACLK, which is typically much slower and usually 32 KHz. A few peripherals, such as
analog-to-digital converters, can also use MCLK and some, such as timers, have their own clock
inputs. The frequencies of all three clocks can be divided in the BCM+ as shown in figure.

Up to four sources are available for the clock, depending on the family and variant:
Low- or high-frequency crystal oscillator, LFXT1: Available in all devices. It is usually used with a
low-frequency crystal (32 KHz) but can also run with a high-frequency crystal (typically a few MHz)
in most devices. An external clock signal can be used instead of a crystal if it is important to
synchronize the MSP430 with other devices in the system.
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High-frequency crystal oscillator, XT2: Similar to LFXT1 except that it is restricted to high
frequencies. It is available in only a few devices and LFXT1 (or VLO) is used instead if XT2 is missing.
Internal very low-power, low-frequency oscillator, VLO: Available in only the more recent
MSP430F2xx devices. It provides an alternative to LFXT1 when the accuracy of a crystal is not
needed.
Digitally controlled oscillator, DCO: Available in all devices and one of the highlights of the
MSP430. It is basically a highly controllable RC oscillator that starts in less than 1s in newer devices.
WATCH DOG TIMERS.
The main purpose of the watchdog timer is to protect the system against failure of the software, such
as the program becoming trapped in an unintended, infinite loop. Watchdog counts up and resets the
MSP430 when it reaches its limit. The code must therefore keep clearing the counter before the limit
is reached to prevent a reset. The operation of the watchdog is controlled by the 16-bit register
WDTCTL

SMCLK
Clock
ACLK

WDT SSEL

WDT CNTCL
(clear)

WDT CNT
(16 bit)
up counter

WDT IFG

PUC

Mode selection

WDT TMSEL
WDT CTL

WDTIE & GIE =1

Control Register

The watchdog counter is a 16-bit register WDTCNT, which is not visible to the user. It is clocked from
either SMCLK (default) or ACLK, according to the WDTSSEL bit. The watchdog is always active after
the MSP430 has been reset. By default the clock is SMCLK, which is in turn derived from the DCO at
about 1 MHz. The default period of the watchdog is the maximum value of 32,768 counts, which is
therefore around 32 ms. We must clear, stop, or reconfigure the watchdog before this time has
elapsed. If the watchdog is left running, the counter must be repeatedly cleared to prevent it counting
up as far as its limit. This is done by setting the WDTCNTCL bit in WDTCTL. The watchdog timer sets
the WDTIFG flag in the special function register IFG1. This is cleared by a power-on reset but its
value is preserved during a PUC. Thus a program can check this bit to find out whether a reset arose
from the watchdog.
BASIC TIMER.
Basic Timer1 is present in all MSP430xF4xx devices. It provides the clock for the LCD module and
generates periodic interrupts. A simplified block diagram of basic timer is shown in figure below.
Newer devices contain a real-time clock driven by a signal at 1Hz from Basic Timer1. The register
BTCTL controls most of the functions of Basic Timer1 but there are also bits in the special function
registers IFG2 and IE2 for interrupts.
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REAL TIME CLOCK.

ADC10 SAR PERIPHERAL MODULE
Figure below shows a simplified block diagram of the ADC10 in the F20x2; there are more inputs in
larger devices.

The ADC10 module of the MSP430F2274 supports fast 10 bit analogue-to-digital conversions;
The module contains:
10-bit SAR core; The ADC10ON bit enables the core and a flag ADC10BUSY is set while
sampling and conversion is in progress. The result is written to ADC10MEM in a choice
of two formats, selected with the ADC10DF bit.
Clock; This can be taken from MCLK, SMCLK, ACLK, or the modules internal oscillator
ADC10OSC, selected with the ADC10SSELx bits.
Sample-and-Hold Unit: This is shown separately in the block diagram. The time is
chosen with the ADC10SHTx bits, which allow 4, 8, 16, or 64 cycles of ADC10CLK.
Input Selection: A multiplexer selects the input from eight external pins A0A7 (more
in larger MSP430s) and four internal connections.
Conversion Trigger; A conversion can be triggered in two ways provided that the ENC
bit is set. The first is by setting the ADC10SC bit from software (it clears again
automatically).
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DIGITAL I/O PORTS

There are 10 to 80 input/output pins on different devices in the current portfolio of
MSP430s; the F20xx has one complete 8-pin port and 2 pins on a second port, while the
largest devices have ten full ports. Almost all pins can be used either for digital input/output
or for other functions and their operation must be configured when the device starts up.
Up to eight registers are associated with the digital input/output functions for each pin. Here
are the registers for port P1 on a MSP430F2xx, which has the maximum number. Each pin
can be configured and controlled individually; thus some pins can be digital inputs, some
outputs, some used for analog functions, and so on.

Port P1 input, P1IN: reading returns the logical values on the inputs if they are
configured for digital input/output. This register is read-only and volatile. It does not
need to be initialized because its contents are determined by the external signals.
Port P1 output, P1OUT: writing sends the value to be driven to each pin if it is
configured as a digital output. If the pin is not currently an output, the value is stored in
a buffer and appears on the pin if it is later switched to be an output. This register is not
initialized and you should therefore write to P1OUT before configuring the pin for
output.
Port P1 direction, P1DIR: clearing a bit to 0 configures a pin as an input, which is the
default in most cases. Writing a 1 switches the pin to become an output. This is for
digital input and output; the register works differently if other functions are selected
using P1SEL.
Port P1 resistor enable, P1REN: setting a bit to 1 activates a pull-up or pull-down
resistor on a pin. Pull-ups are often used to connect a switch to an input as in the section
Read Input from a Switch on page 80. The resistors are inactive by default (0). When
the resistor is enabled (1), the corresponding bit of the P1OUT register selects whether
the resistor pulls the input up to VCC (1) or down to VSS (0).
Port P1 selection, P1SEL: selects either digital input/output (0, default) or an
alternative function (1). Further registers may be needed to choose the particular
function.
Port P1 interrupt enable, P1IE: enables interrupts when the value on an input pin
changes. This feature is activated by setting appropriate bits of P1IE to 1. Interrupts are
off (0) by default. The whole port shares a single interrupt vector although pins can be
enabled individually.
Port P1 interrupt edge select, P1IES: can generate interrupts either on a positive edge
(0), when the input goes from low to high, or on a negative edge from high to low (1). It
is not possible to select interrupts on both edges simultaneously but this is not a
problem because the direction can be reversed after each transition. Care is needed if
the direction is changed while interrupts are enabled because a spurious interrupt may
be generated. This register is not initialized and should therefore be set up before
interrupts are enabled.
Port P1 interrupt flag, P1IFG: a bit is set when the selected transition has been
detected on the input. In addition, an interrupt is requested if it has been enabled. These
bits can also be set by software, which provides a mechanism for generating a software
interrupt (SWI).

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Additional Questions:
1. Explain the following instructions.
a) DADD: DECIMAL ADD source and carry to the destination.
(Destination) = (carry) + (source) + (destination)
b) BIC: BIC(.b or .w) src, dst: not src and dst to dst.
c) CMP: CMP(.b or .w) src, dst: compare source and destination.
d) SXT dst. Extend bit 7 to bit 8-bit15 (sign extended destination.)
e) CALL (.b or .w) dst: SP-2 > SP, PC+2 > @SP, dst > PC (subroutine call to destination)
Missing 8255 Notes
Eg: interface 8255A with 8051 microcontroller such that the control register is selected for the
address 1003H. find the address of port A,B and C
Solution
The control register is selected for the address 1003H. Address lines A15 to A0 for ports and control register
is as follows.
A15
0
0
0
0

A14
0
0
0
0

A13
0
0
0
0

A12
1
1
1
1

A11
0
0
0
0

A10
0
0
0
0

A9
0
0
0
0

A8
0
0
0
0

A7
0
0
0
0

A6
0
0
0
0

A5
0
0
0
0

A4
0
0
0
0

A3
0
0
0
0

A2
0
0
0
0

A1
0
0
1
1

A0
0
1
0
1

PORT A
PORT B
PORT C
CR

Address of Port A is 1000h, Port B is 1001h, port C is 1002h and control word is 1003h. RD and WR pins of
8051 is connected to RD and WR pins of 8255 as shown in fig. A0 and A1 from 8255 are directly connected to
address lines of 8051. Remaining address lines are connected to the decoder 74LS138 and the output of the
decoder is connected to the CS pin of 8255. Data pins of 8255 is directly connected to the data bus of 8051
microcontroller.

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