Scribd
Upload
377 views2 pages

HW 3

This document outlines the submission rules and problems for Assignment-5 for the EECS 112 & CSE 132 courses at UC Irvine. It specifies that submissions must be a single PDF file uploaded to the correct dropbox by the due date, and that typed or LaTeX files will receive bonus points. It then provides two problems: the first asks to analyze memory address references in direct mapped caches of different sizes, and the second examines parameters of a virtual memory system and asks questions about page table organization and address translation.

Uploaded by

Shanka Udugampola
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
377 views2 pages

HW 3

This document outlines the submission rules and problems for Assignment-5 for the EECS 112 & CSE 132 courses at UC Irvine. It specifies that submissions must be a single PDF file uploaded to the correct dropbox by the due date, and that typed or LaTeX files will receive bonus points. It then provides two problems: the first asks to analyze memory address references in direct mapped caches of different sizes, and the second examines parameters of a virtual memory system and asks questions about page table organization and address translation.

Uploaded by

Shanka Udugampola
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Assignment-5 (EECS 112 & CSE 132)

University of California Irvine Fall 2014

Submission rules

You are supposed to upload your assignment through the drop box.
o You can easily find it by logging into eee.uci.edu/myeee/ website.
o Make sure to submit the assignment to the corresponding dropbox for this course.
You are only supposed to submit a PDF file.
No late submission are acceptable
The submitted file should have the minimum quality
o If the submitted file is not readable for your grader you will lose grade.
o If you want to take a picture or scan your handwriting make sure the electronic
version is readable.
You will get extra 5 points if the submitted file is typed by word, or latex applications.
(Dont forget to upload the only PDF file.)

20 points
1. Below is a list of 32-bit memory address references, given as word addresses
a.
b.

1, 134, 212, 1,135, 213, 162, 161, 2, 44, 41, 221


6, 214, 175, 214, 6, 84, 65, 174, 64, 105, 85, 215

1.1. For each of these references, identify the binary address, the tag, and the index given a
direct mapped cache with 16 one-word blocks. Also list if each reference is a hit or a
miss, assuming the cache is initially empty.
1.2. For each of these references, identify the binary address, the tag, and the index given a
direct mapped cache with two-word blocks and a total size of eight blocks. Also list if
each reference is a hit or a miss, assuming the cache is initially empty.

30 points
2. For a direct-mapped cache design with 32-bit address, the following bits of the address are
listed to access the cache. Discuss each of following questions. There is no point if you only
provide the final answer.

a.
b.

Tag
31-10
31-12

Index
9-4
11-5

2.1. What is the cache line size (in words)?


1

Offset
3-0
4-0

Assignment-5 (EECS 112 & CSE 132)


University of California Irvine Fall 2014
2.2. How many entries does the cache have?
2.3. What is the ratio between total bits required for such a cache implementation over the
data storage bits?
Starting from power on, the following byte-addressed cache references are recorded
Address
0 4 16 132
232
160
1024
30
140
3100
180
2180
2.4. How many blocks are replaced?
2.5. What is the hit ratio?
2.6. List the final state of the cache, with each valid entry represented as a record of <index,
tag, data>.

30 points
3. The following table shows parameters of a virtual memory system.

a.
b.

Virtual address
(bits)
32
64

Physical DRAM
installed
4 GB
16GB

Page size

PTE size (bytes)

8 KB
4 KB

4
8

3.1. For a single-level page table, how many page table entries are needed? How much
physical memory is needed for storing the page table?
3.2. Using a multilevel page table can reduce the physical memory consumption of page
tables by only keeping active PTEs in physical memory. How many levels of page table
will be needed in this case? How many memory references are needed for address
translation is missing in TLB?
3.3. An inverted page table can be used to further optimize space and time. How many PTEs
are needed to store the page table? Assuming a hash table implementation, what are the
common case and worst case numbers of memory references needed for servicing a TLB
miss?

You might also like