Scribd
Upload
41 views4 pages

Mid-Semester Test Solutions: EE668 System Design

The document provides solutions to exam problems related to modeling electrical components in integrated circuits. It calculates resistances, inductances, and capacitances of supply networks. It also analyzes how signal propagation is affected by wire length and capacitive coupling between wires as technology scales down. Simply scaling down layout between technology nodes without adjusting for changes in electrical parameters would cause failures due to increased delays and noise.

Uploaded by

Alisa Lawrence
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
41 views4 pages

Mid-Semester Test Solutions: EE668 System Design

The document provides solutions to exam problems related to modeling electrical components in integrated circuits. It calculates resistances, inductances, and capacitances of supply networks. It also analyzes how signal propagation is affected by wire length and capacitive coupling between wires as technology scales down. Simply scaling down layout between technology nodes without adjusting for changes in electrical parameters would cause failures due to increased delays and noise.

Uploaded by

Alisa Lawrence
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Mid-semester test solutions: EE668 System

Design

You are given that the permittivity of free space is 0 = 8.85 1012 F/m
and the permeability of free space is 0 = 4 107 H/m. The conditivity of
copper is 5.8 107 S/m.
1. Consider a system with a single VDD pin and a single VSS pin (assume
that pin inductance is 0). The system is supplied power from an ideal 1V
source, through a coaxial cable of length X with the following parameters.
The inner conductor is made of copper and has a diameter of 1mm, the
outer annular conductor (also made of copper) has thickness 1mm, and the
radial distance between the outer surface of the inner conductor and the
inner surface of the outer conductor is 1mm. The material between the
two conductors has permittivity 40 and has magnetic permeability 0 .
Find the per-unit length R, L, C for the supply network (make suitable
approximations if you feel they are necessary). (10)
Assume that current is distributed uniformly across the conductor
cross-section. The cross-section area of the outer conductor is
(2.5mm2 1.5mm2 ), so that the per-unit length resistance of the
outer conductor is 0.0137m/m. Similarly, the per-unit length resistance of the inner conductor is 0.219m/m, so that the total per-unit
length resistance of the supply network is 0.233m/m.
The electric field in the region between the conductors is radial and
symmetric around the annular region. The capacitance per-unit
length can then be easily calculated as 80 / ln 3, which works out
to 202.46pF/m.
The per-unit length inductance and the per-unit length capacitance
are related by L0 C0 = . Thus, the per-unit length inductance is
54.9nH/m.
2. The system in problem 1 operates at a frequency of f , and the internal
transition time of signals in the system is required to be 0.1/f . The total
capacitance being switched inside the system is 1 nF . During operation,
the average supply-voltage across the system is to be at least 0.95V and

the minimum instantaneous supply voltage across the system is to be at


least 0.9V . Let fmax (X) be the maximum frequency at which the system
will operate correctly (subject to the requirements outlined above). Plot
fmax (X) versus X as X varies from 0 to 10m. You may ignore issues
related to the initialization of the system. (10)
The average current demand from the system is
Iavge = f (X) 1nF 1V = 109 f (X) A.
The peak current demand is
Ipeak = 2 (1nF 1V )/(0.1/f (X)) = 2 108 f (X) A.
and the peak demanded rate of change of current is
(dI/dt)peak = 4(1nF 1V )/(0.1/f (X))2 = 4107 f (X)2 A/s.
To maintain the average curent with the desired drop across the
supply, we must have
109 f (X) 0.233X 0.05V
or f (X) (215/X)M Hz. To limit the transients at the terminals to
100mV , we must have
(2108 f (X)0.233X) + (4107 f (X)2 54.5nHX) 0.1V
For values of X upto 10m, the f 2 term dominates, and we find that
6.7
f (X) M Hz.
X
Thus, we find that

f (X) = Minimum(215/X, 6.7/ X)M Hz.


3. Repeat problem 2, but this time, assume that a decoupling capacitance of
1F is placed across the system supply terminals? (10)
In this case, only the average drop condition is necessary. Thus
f (X) = 215/XM Hz.
4. Consider a 1m long RC line. Assume that the wire width is a variable W
and the per-unit length wire resistance has the form R0 = (2/W )/cm and
the per-unit length wire capacitance has the form C0 = (1 + W/2)pF/cm.
The minimum allowed width of the wire is 4 units. You are allowed to use
buffers with driving resistance 1000 and input capacitance 0.1pF . The
wire is to be terminated by a buffer.
2

(a) Using the Elmore approximation, find the best possible delay (that
can be obtained by using additional buffers) from the input of the
first buffer driving the line to the input of the terminating buffer in
the line (as a function of W ). (5)
The best possible delay is

100 (2 wire g + 1k (1 + W/2)pF + 2/W 0.1pF )


where wire = (W + 2)/2W ps/cm2 and g = 100ps.
(b) What is the best possible value of W and the corresponding value of
the delay? (5)
The W dependent term dominates, and hence the best possible
value for W is the minimum value 4 (you can check that the
derivative with respect to W is positive for W 4). The delay
can then be calculated to be 301.7ns.
5. Consider a victim wire driven by a driver with resistance 1k and driving
a total load of 1pF . Assume that the victim is coupled to an aggressor through a coupling capacitance of 0.1pF and that the aggressor line
switches with a rise time of 1ns.
(a) What is the peak coupling noise observed in the victim line due to
the switching of the aggressor? (5)
It is easy to see that KC = 0.1/1.1 = 0.091. The peak coupling
will work out to 0.63 KC = 57mV .

(b) What are the minimum and maximum values of the delay in the
victim buffer (use the Elmore approximation)? (5)

The nominal delay is 1.1ns ln 2 = 0.76ns. The minimum is


1ns ln 2 = 0.69ns, and the maximum is 1.2ns ln 2 = 0.83ns.
6. As technology scales from one generation to the next (by a scale factor S,
using constant field scaling), how do the following quantities scale?
(a) The peak current demand per unit area: 1/S.
(b) The average current demand per unit area: 1/S.
(c) The delay of a typical gate: S.
(d) The per-unit length capacitance of a wire in dense layout: 1/S.
(e) The delay from the input of a gate driving a short wire to the input
of the gate in which the short wire is terminated: between S and 1.
(f) The delay from the input of a gate driving a fixed length (long) wire
to the input of the gate in which the wire is terminated: 1/S 2 .
(g) The longest unbuffered segment of wire in a well designed circuit:
S 3/2 .
(h) The per-unit length inductance of a wire in dense layout: S.
3

(i) The leakage current per unit area: e(1S) .


(j) The maximum throughput (bits per second) that can be communicated between two points at a fixed distance from each other: 1/S.
7. You are given a VLSI system built in 180nm technology which operated at
100M Hz, and are asked to transfer the system to the 130nm technology
node so that it would now work at 140M Hz, and be half the size it was.
You decide to take a short cut and scale the original circuits layout down
to the 130nm node. However the circuit does not function correctly and
you get into big trouble. Can you list the probable reasons why the scaled
circuit did not function as expected? (10)
Wire delays will not scale; hence path delays will not scale by S.

Capacitive coupling will increase, potentially causing noise margin


violations if the frequency is scaled.
Gate delay variation will increase due to increased capacitive coupling, hence path delays may not scale.
Note that contact resistance scales up (because the cross-section area
of the contact scales down by S 2 ). Thus, the resistance of the power
supply network may increase (resistance of the wires will stay the
same, however). But current demands will scale by S. Thus relative
supply induced noise is likely increase, leading to potentially higher
gate delays and degraded noise margins.

You might also like