ALTERA - In-System Programmability Guidelines
ALTERA - In-System Programmability Guidelines
ALTERA - In-System Programmability Guidelines
2014.09.22
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In-system programming (ISP) allows you to program ISP-capable Altera devices through the IEEE Std.
1149.1 JTAG interface. This interface allows you to program devices and functionally test the PCB in a
single manufacturing step, saving testing time and assembly costs.
As time-to-market pressure increases, design engineers require advanced system-level products to ensure
problem-free development and manufacturing. Programmable logic devices (PLDs) with ISP can help
accelerate development time, facilitate in-field upgrades, simplify the manufacturing flow, lower
inventory costs, and improve PCB testing capabilities.
Operating Conditions
User Flash Memory Operations During In-System Programming
Interrupting In-System Programming
MultiVolt Devices and Power-Up Sequences
I/O Pins Tri-Stated During In-System Programming
Pull-Up and Pull-Down of JTAG Pins During In-System Programming
Operating Conditions
Each Altera device has several parametric ratings (operating conditions) required for proper operation.
When in user mode, Altera devices can exceed these conditions and still operate correctly; however,
Altera device must not exceed these conditions during in-system programming. Violating any of the
operating conditions during in-system programming can result in programming failures or incorrectly
programmed devices.
Table 1: Power-up Requirements for ISP Functions for Altera devices
Device
Power-up Requirements
2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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ISP Voltage
Device
Power-up Requirements
ISP Voltage
Altera devices have different ISP voltage requirements depending on the device family. You have to be
comply all requirements to ensure the device are programmed correctly.
MAX 10 Devices
For MAX 10 devices, you must maintain the VCC/VCC_ONE level, VCCA level, and VCCIO level on the
VCC/VCC_ONE, VCCA, and VCCIO pins during in-system programming to ensure the flash cells of the
device are correctly programmed. The VCC/VCC_ONE, VCCA and VCCIO specification applies for both
commercial- and industrial-temperature grade devices.
MAX II and V Devices
For MAX II and MAX V devices, you must maintain the VCCINT level and VCCIO level on the VCCINT and
VCCIO pins during in-system programming to ensure the flash cells of the device are correctly
programmed. The VCCINT and VCCIO specification applies for both commercial- and industrial-tempera
ture grade devices.
MAX 3000, MAX 7000, and MAX 9000 Devices
MAX 3000, MAX 7000, and MAX 9000 devices have specified ISP voltage known as VCCISP. You must
maintain the VCCISP level on the VCCINT pins (for example, VCCINT equals to VCCISP) during ISP to ensure
that the EEPROM cells of the device are programmed correctly. The VCCISP specification applies for both
commercial- and industrial- temperature- grade devices.
You have to adjust your in-system programming setup to maintain correct voltage levels if power
consumption during ISP exceeds the power consumption when in user mode. Altera recommends that
you test the VCCISP levels on the devices VCCINT pins with an oscilloscope. First, test the VCCISP levels
with the oscilloscopes trigger level set to the recommended minimum VCC level. Measure the voltage
between VCCINT and ground, probed at the pins of the device. Then, repeat this test with the oscilloscopes
trigger level set to the recommended maximum VCC level. If the oscilloscope is triggered at either voltage
level, you must adjust your programming setup.
The recommended voltage levels are specified in the Recommended Operating Conditions section of the
appropriate Device Family Datasheet. Refer to the related information.
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Input Voltages
Input Voltages
Every Altera device family has a range for safe device operation. You need to ensure that all pins that
transition during in-system programming do not have a ground or VCC overshoot. Overshoot problems
typically occur on free-running clocks or data buses that can toggle during in-system programming. Pins
that have an overshoot greater than 1.0 V must have series termination.
Each Device Family Datasheet lists the device input voltage specification in the Absolute Maximum
Ratings and the Recommended Operating Conditions tables. The input voltages in the Absolute
Maximum Rating table refers to the maximum voltage that the device can tolerate before risking
permanent damage.
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If you cannot ensure that any erase or write operation of the UFM is complete before attempting an ISP
operation to the MAX II, MAX V or MAX 10 device, you must enable the real-time ISP feature. If used
properly, this feature can help guard against any UFM or ISP operation contention. If you enable realtime ISP feature, the programming algorithm from the Quartus II software, or Jam Standard Test and
Programming Language (STAPL) Format (.jam) file/Jam Byte-Code (.jbc) file waits for 500 ms before it
begins any operation, the same amount of time it takes to erase one UFM sector (that is, the real-time ISP
programming algorithm waits for a previously started UFM erase operation to complete).
However, if you are using a real-time ISP feature, no other UFM operations are allowed after that time (no
address shifting, no data shifting, and no read, write, or erase operations). You can control the UFM
operations by monitoring the RTP_BUSY signal on the ALTUFM_NONE megafunction. If you are
performing a real-time ISP operation, the RTP_BUSY output signal on the UFM block goes high. You can
monitor the RTP_BUSY signal and ensure that all UFM operations from the logic array cease until real-time
ISP is complete. This user-generated control logic is only necessary for the ALTUFM_NONE megafunc
tion, which provides no auto-generated logic. The other parameter editors for the ALTUFM megafunc
tion (ALTUFM_PARALLEL, ALTUFM_SPI, and ALTUFM_I2C) contain control logic that automatically
monitors the RTP_BUSY signal and ceases UFM operations if you are performing the real-time ISP
operation.
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Figure 1: External Pull-Up and Pull-Down Resistors for TMS and TCK of a JTAG Chain in Altera Devices
Figure shows the external pull-up and pull-down for the TMS and TCK pins of the JTAG chain in Altera
devices. The TDO pin does not have internal pull-up or pull-down resistors, and does not require external
pull-up or pull-down resistors.
10-Pin Male Header
(Top View)
VCC
VCC
10 k
Altera Device
TDI
TMS
TDO
TCK
Other ISP-Capable
Device
Other ISP-Capable
Device
TDI
TDI
TMS
TDO
TCK
TMS
TDO
TCK
GND
1k
The TMS signal is pulled high so that the test access port (TAP) controller remains in the TEST_LOGIC or
RESET state even if there is input from TCK signal. During power up, you must pull the TCK signal low to
prevent the TCK signal from pulsing high. Pulling the TCK signal high is not recommended because the
increase in power supply to the pull-up resistor causes the TCK signal to pulse high; therefore, it is possible
for the TAP controller to reach an unintended state.
Related Information
TCK Signal
A noisy TCK signal causes most in-system programming failures. Noisy transitions on rising or falling
edges can cause incorrect clocking of the IEEE Std. 1149.1 TAP controller. Incorrect clocking can cause
the state machine to transition to an unknown state, leading to in-system programming failures.
Because the TCK signal must drive all IEEE Std. 1149.1 devices in the chain in parallel, the signal may have
a high fan-out. Like any other high fan-out user-mode clock, you must manage a clock tree to maintain
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signal integrity. Typical errors that result from clock integrity problems are invalid ID messages, blankcheck errors, or verification errors.
Altera recommends pulling the TCK signal low through the internal weak pull-down resistor or an external
1-k resistor.
Fast TCK edges combined with board inductance can cause overshoot problems. When this combination
occurs, you must either reduce inductance on the trace or reduce the switching rate by selecting a
transistor-to-transistor logic (TTL) driver chip with a slower slew rate. You must not use resistor and
capacitor networks to slow down edge rates, because resistor and capacitor networks can violate the input
specifications of the device. Use a driver chip to prevent the edge rate from being too slow. Altera
recommends using driver chips that do not glitch after power up.
Max 10
Permanently Disabled
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Device
Permanently Disabled
MAX II
Either:
MAX V
Pull the TMS signal high and the TCK signal low
MAX 9000
or
MAX 9000A
Pull the TMS signal high before pulling the TCK signal high
MAX 7000S
MAX 7000B
MAX 7000A
MAX 7000AE
Either:
Turn off the Enable JTAG BST
Support option in the Quartus II
software.
MAX 3000A
JTAG Permanently Disabled (MAX 7000S, MAX 7000B, MAX 7000A, MAX 7000AE and MAX 3000A
Devices)
You can use MAX 7000S, MAX 7000B, MAX 7000A, MAX 7000AE, and MAX 3000A device JTAG pins
as either JTAG ports or I/O pins. You must specify how the pins will be used before compiling your
design in the Quartus II software by turning the Enable JTAG BST Support option on or off. When you
turn on this option, the pins act as JTAG ports for in-system programming and boundary-scan testing;
when you turn off this option, the pins act as I/O pins and you cannot perform in-system programming
or boundary-scan testing.
JTAG Permanently Disabled (MAX 10, MAX V, MAX II, MAX 9000 and MAX 9000A Devices)
By default, the JTAG circuitry is always enabled in MAX 10, MAX V, MAX II, MAX 9000, and MAX
9000A devices after power-up. You must enable the JTAG circuitry during ISP and boundary-scan
testing, but must be disabled at all times. Therefore, if you do not plan to use the ISP and BST circuitry,
you can disable the circuitry through the JTAG pins. To disable JTAG, the JTAG specification instructs
you to pull the TMS signal high but does not explain what to do with the TCK signal. Altera recommends
pulling the TMS signal high and the TCK signal low. Pulling the TCK signal low ensures that a rising edge
does not occur on the TCK signal during the power-up sequence.
You can pull the TCK signal high, but only after you pull the TMS signal high. Pulling the TMS signal high
first ensures that the rising edges on the TCK signal do not cause the JTAG state machine to leave the testlogic-reset state.
JTAG Enabled for ISP or BST and Disabled in User Mode
For Altera ISP-capable devices that use JTAG for either in-system programming or boundary-scan
testing, you must enable the JTAG circuitry during ISP and BST but must be disabled at all other times.
You control JTAG operation through the JTAG pins. To disable the JTAG circuitry on MAX 10, MAX V,
MAX II, MAX 9000, and MAX 9000A devices permanently, either pull the TMS signal high and the TCK
signal low, or pull the TMS signal high before pulling the TCK signal high.
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Sequential Programming
Sequential programming is the process of programming multiple devices in a chain, one device at a time.
After the process of programming the first device in the chain is complete, the next device is programmed.
This sequence continues until all specified devices in the JTAG chain are programmed. After a device is
successfully programmed, the device is in bypass mode that allows passing of data to the subsequent
devices in the chain. The devices in the chain do not go into user mode until all the devices are
programmed.
Concurrent Programming
Use concurrent programming to program devices from the same device family in parallel. The program
ming time is longer than the time required to program the largest device in the chain, resulting in
considerably faster programming times than sequential programming (where programming time is equal
to the sum of individual programming times for all devices). Higher clock rates for shifting data result in
even greater time savings.
To perform concurrent programming of devices with Serial Vector Format File (.svf), .jam files, or .jbc files
created from the Quartus II software, follow these steps:
1.
2.
3.
4.
5.
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You can perform sequential programming with a .jam or .svf if you create individual files for each device.
In this scheme, FLEX and APEX devices do not begin configuration until you click the Configure button
in the MAX+PLUS II Programmer.
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Software Issues
Failures during in-system programming may occasionally be related to the Quartus II software or the
MAX+Plus II software.
Software-related issues are documented in the Knowledge Center section under the Support Center on the
Altera website. Search the database for information relating to software issues that interfere with insystem programming.
Related Information
Knowledge Center
AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
Provides more information about how to estimate the maximum amount of RAM and ROM required by
the Jam Player.
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'# Example: This example reads the IDCODE of a single device JTAG chain
'# and compares it to an EPM9480 IDCODE:
'#
'# C:\> jam -dCOMP_IDCODE_9480=1 -p378 IDCODE.jam
'############################################################################
#
Example 2: Sample 2
' ######################### Initialization ########################
BOOLEAN read_data[32];
BOOLEAN I_IDCODE[10] = BIN 1001101000;
BOOLEAN I_ONES[10] = BIN 1111111111;
BOOLEAN ONES_DATA[32]= HEX FFFFFFFF;
BOOLEAN ID_9320[32] = BIN 10111011000000000100110010010000;
BOOLEAN ID_9400[32] = BIN 10111011000000000000001010010000;
BOOLEAN ID_9480[32] = BIN 10111011000000000001001010010000;
BOOLEAN ID_9560[32] = BIN 10111011000000000110101010010000;
BOOLEAN ID_7032S[32] = BIN 10111011000001001100000011100000;
BOOLEAN ID_7064S[32] = BIN 10111011000000100110000011100000;
BOOLEAN ID_7128S[32] = BIN 10111011000000010100100011100000;
BOOLEAN ID_7128A[32] = BIN 10111011000000010100100011100000;
BOOLEAN ID_7160S[32] = BIN 10111011000000000110100011100000;
BOOLEAN ID_7192S[32] = BIN 10111011000001001001100011100000;
BOOLEAN ID_7256S[32] = BIN 10111011000001101010010011100000;
BOOLEAN ID_7256A[32] = BIN 10111011000001101010010011100000;
BOOLEAN COMP_9320_IDCODE = 0;
BOOLEAN COMP_9400_IDCODE = 0;
BOOLEAN COMP_9480_IDCODE = 0;
BOOLEAN COMP_9560_IDCODE = 0;
BOOLEAN COMP_7032S_IDCODE = 0;
BOOLEAN COMP_7064S_IDCODE = 0;
BOOLEAN COMP_7096S_IDCODE = 0;
BOOLEAN COMP_7128S_IDCODE = 0;
BOOLEAN COMP_7128A_IDCODE = 0;
BOOLEAN COMP_7160S_IDCODE = 0;
BOOLEAN COMP_7192S_IDCODE = 0;
BOOLEAN COMP_7256S_IDCODE = 0;
BOOLEAN COMP_7256A_IDCODE = 0;
BOOLEAN COMP_7032AE_IDCODE = 0;
BOOLEAN COMP_7064AE_IDCODE = 0;
BOOLEAN COMP_7128AE_IDCODE = 0;
BOOLEAN COMP_7256AE_IDCODE = 0;
BOOLEAN COMP_7512AE_IDCODE = 0;
INTEGER PRE_IR = 0;
INTEGER PRE_DR = 0;
INTEGER POST_IR = 0;
INTEGER POST_DR = 0;
BOOLEAN SET_ID_EXPECTED[32];
BOOLEAN COMPARE_FLAG1 = 0;
BOOLEAN COMPARE_FLAG2 = 0;
BOOLEAN COMPARE_FLAG = 0;
' This information is what is expected to be shifted out of the instruction
' register
BOOLEAN expected_data[10] = BIN 0101010101;
BOOLEAN ir_data[10];
Example 3: Sample 3
' These values default to 0, so if you have a single device JTAG chain, you
do
In-System Programmability Guidelines
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Example 4: Sample 4
' ######################### Actual Loading ########################
IRSTOP IRPAUSE;
STATE RESET;
IRSCAN 10, I_IDCODE[0..9], CAPTURE ir_data[0..9];
STATE IDLE;
DRSCAN 32, ONES_DATA[0..31], CAPTURE read_data[0..31];
' ######################### Printing ########################
PRINT "EXPECTED IRSCAN : 1010101010";
PRINT "ACTUAL IRSCAN: ",ir_data[0], ir_data[1], ir_data[2], ir_data[3],
ir_data[4], ir_data[5], ir_data[6], ir_data[7], ir_data[8], ir_data[9];
PRINT "";PRINT "EXPECTED IDCODE : ", SET_ID_EXPECTED[0], SET_ID_EXPECTED[1],
SET_ID_EXPECTED[2], SET_ID_EXPECTED[3], SET_ID_EXPECTED[4],
SET_ID_EXPECTED[5], SET_ID_EXPECTED[6], SET_ID_EXPECTED[7],
SET_ID_EXPECTED[8], SET_ID_EXPECTED[9], SET_ID_EXPECTED[10],
SET_ID_EXPECTED[11], SET_ID_EXPECTED[12], SET_ID_EXPECTED[13],
SET_ID_EXPECTED[14], SET_ID_EXPECTED[15], SET_ID_EXPECTED[16],
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AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
Provides more information about using Agilents 3070 in-circuit tester to in-system program MAX II and
MAX V devices.
September 2014
Version
2014.09.22
Changes
December 2010
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4.0