A Low-Voltage, Bulk-Driven MOSFET Current Mirror for CMOS Technology

Benjamin J. Blalock and Phillip E. Allen

School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, GA 30332-0250, USA
[email protected],
pallen @ee.gatech.edu

11. BULK-DRIVEN MOSFETS

Abstract-A bulk-driven, MOSFET current mirror is described
which is capable of operating at power supplies down to 1V
using standard CMOS technologies with threshold voltages in
the range of +0.8Y. The bulk-driven MOSFET configuration
removes the requirement that the input voltage of the current
mirror equal VGS > VT, At V ~ f l sof ~+0.75 VI-0.75 V,
measurements on simple current mirrors using this new
technique require only about 0.1 V across the input device of the
current mirror circuit and exhibit saturation voltages on the
output device of the current mirror comparable to that of
standard simple current mirrors. The operation and first-order
models for the bulk-driven MOSFET are presented in this paper
along with the operation and experimental results of a simple,
bulk-driven mirror.

I. INTRODUCTION
IC technology trends suggest that future implementation
of mixed analog digital circuits using standard CMOS will
have power supplies of 1.5V or less [l-21. Furthermore, it is
conjectured that the threshold voltages will not significantly
decrease below what is available today [3]. The fundamental
iimitation to lower voltage analog circuits using existing
design techniques is shown in Eq. (1). This equation states
that the power supply must be at least equal to the sum of the
magnitudes of the p-type and n-type threshold voltages [4].
IVDD - V s s l 2 Vw + Wtpl

(1)

There are three possible approaches to achieving highperformance analog circuits in CMOS technology at low
power supply voltages. One is to multiply the lower voltage
dc to larger values. Another is to modify existing CMOS
technologies to accommodate low-voltage analog circuits. A
third is to develop new circuit techniques that achieve this
objective with existing technology.
This paper illustrates the application of the third approach.
The advantages are that it is efficient and can be used without
the need for costly process development (which may in fact
be disadvantageous to digital circuits). Among the many
possibilities for implementing the third approach [SI, the
bulk-driven MOSFET offers the potential for avoiding the
limit of Eq. (1). The bulk-driven operation of the MOSFET
will be described in Section 11. The use of bulk-driven
MOSFETs to achieve a current mirror having input voltage of
0.1-0.3V and saturation output voltages similar to gate-driven
MOSFET mirrors will be illustrated in Section 111. Finally,
the experimental results will be compared with theory in
Section IV.

0-7803-2570-2/95 $4.00 01995 IEEE

Bulk-driven techniques can only be applied to the

MOSFET that can be fabricated in its own separate well. A
cross-section of a p-type MOSFET in a n-well is shown in
Fig. 1. The parasitic lateral (QP) and vertical (QV) bipolar
junction transistors are also shown. The operation of the
bulk-driven MOSFET is much like a JFET. The inversion
layer forming the conduction channel beneath the gate is
established by connecting the gate terminal to a fixed voltage
of sufficient magnitude to form a channel. The conduction
channel of the JFET is the MOSFETs inversion layer beneath
the gate structure. The thickness of the depletion layer
beneath the source, inversion layer, and drain of the
MOSFET is determined by the bulk potential. By varying the
bulk-source voltage, this depletion layer thickness changes,
and the inversion layer through which the drain current is
flowing is modulated. The channel current can be modulated
with very small dc values of the bulk-source potential
resulting in a device that is extremely useful for low voltage
applications.
The iD vs. VB characteristics of a 100p/2p p-channel
MOSFET fabricated by MOSIS in a 2pm n-well process are
shown in Figure 2. These curves are representative of a fourchip sample. The data indicates that for forward-bias sourcebulk junction potentials less than about 0.75 V, the drain
current varies with source-gate voltage as expected for a
MOSFET with constant source-drain voltage applied. Note
that for VSB greater than -0.3 V the substrate current is less
100 pA while the bulk current is less than 1 PA, below the
instrumentation's measurement resolution. This weakly
forward-biased source-bulk junction condition with the
MOSFET operating in strong inversion saturation is the
premise of the bulk-driven technique presented in this paper.
The performance of the bulk-driven MOSFET is
equivalent to the gate-driven MOSFET. The only exceptions
are related to the physical size of the bulk which can be
minimized through unique layout techniques. Normal current
flow in the bulk terminal is in the picoampere range and is
insignificant in most applications where VBS 10.3 V. The l/f
noise of the bulk-driven MOSFET is approximately equal to
that of a gate-driven MOSFXT. A slight increase in thermal
noise occurs due to the resistance of the bulk. Modification
of normal layout practice may allow the bulk resistance and
input capacitance to be reduced.
First-order theory [6] gives the dependence of the drain
current, iD, as

1972

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10-6

vso = 1.2 v
vSO= 1.ov
vso=aav

10.8

VSO = 0.6V

1OA

ij

ID@

10-10

vSO=a4v

10-12

- 1.so

-0.50

-1.00

0.00

VSB

Figure 2 - Traiisconductance characteristics of a PMOS bulkdriven MOSFET.

Figure 1 - Cross-section of a PMOS transistor and terminal

voltages for bulk-source operation.

better correlation between experimental and theoretical

results.

(2)

and

111. THE BULK-DRIVEN SKMPLE CURRENT MIRROR

and
vDS(sat) =

VGS - VT'

The parameters in Ey. (4) are identical with standard SPICE

parameters for MBSFETs. However, i n bulk-source
operation, the gate-source voltage becomes a constant amd we
re-express Eqs. (2) and (33 as

respectively. The small signal transconductance in saturaticn

is given by

where g, is the top-gate transconductancc. With the sourccbulk junction forward-biased, VBS in the above expression is
negative thereby reducing the magnitude of the denominator.
For VBS greater than zero, Eq. (3) shows how the bulk-driven
(bottom-gate) transconductance can be equal or larger than
gm. These equations have been used for the theoretical
predictions of the bulk-driven MOSFET but preliminary
indications suggest that they need to re-examined to permit

A new current mirror for low-voltage CMOS analog

signal processing circuits has been developed. Resent day
c~rrcntmirrors contain gate-drain, or diode connections. The
voltage drop across this connection is greater than l V ~ for
l the
strong-inversion saturation operation. The bulk-driven
current mirror presented in this paper instead utilizes a bulkdrain connection to avoid the large voltage-drop penalty. As
a result, these current mirrors are well suited for low power
supply voltage applications.
A NMOS version of the bulk-driven current mirror is
shown in Figure 3. Note that instead of the gate-drain diode
connection used in the standard simple current mirror, this
:iew current mirror has a bulk-drain connection. Also, the
bulks of M1 and M2 are tied together rather than the gates.
Instead, the gates of M1 and M2 for the NMOS version go to
the most positive fixed voltage available, VDD. The voltage
potential between the each gate and source muse be greater
than or equal to l V ~ lin order to form an inversion layer
beneath the gate. The NMOS bulk-driven current mirror can
be implementcd in CMOS p-well technology.
To derive an expression for the output current for the
simple current mirror shown in Figure 3, first consider the
mode of operation for each device. M1, the input device, is
operated in its linear region. This is condition is imposed by
MI'Sbulkdrain connection, forcing V ~ s =l V B S ~ Note
.
that
VBSl is positive and that VBSl = vBS2. M l and M2 reside
in the same well and both have source-bulk junctions only
slightly forward-biased, provided of course that aspect ratios
have been chosen appropriately for strong inversion
operation. Previously discussed in Section 11, it desirable to
only slightly forward-bias the source-bulk junction as this
insures that the bulk current remains negligible. If this were
not the case, some input current to the mirror circuit would be
lost to the bulk. For Ihe bulk-driven current mirror then M1
1s operated linearly since VDsl will be less than V D S , ~ ~ ~ .
Note however that M2's drain-source voltage is allowed to

exceed V D S , ~thereby
~ ~ , permitting saturation operation.
Because VBSl = V B S ~
in Fig. 3, then

1973

Figure 3 - NMOS simple, bulk-driven current mirror.

By solving equation (2) for (VGS1 - VT) and substituting into

equation (3), the output current expression becomes

where I3 = K ' W L
The input impedance of the bulk-driven current mirror is
described by

As was mentioned in the previous section, the VBS term is

positive thereby reducing the argument of the numerator's
radical.
The output impedance for the low voltage current mirror
can be approximated just as i t is for the standard simple
current mirror [61,

rout =

1
IDSsat.

IV. SIMPLE CURRENT MIRROR PERFORMANCE

Figure 4 - (a.) PMOS gate-driven current mirror. (b.) PMOS

bulk-driven current mirror.
mirror's output current follows its input current much more
closely than the bulk-driven mirror. This is to be expected
since M2's aspect ratio was chosen to match that of M1. Eq.
(10) reveals that careful selection of unequal device aspect
ratios will result in Iout values closer in magnitude to Ii,.
Note also that the bulk-driven mirror's Iout curves are spaced
closer together than those of the gate-driven mirror. This is
attributed to M2's drain current now being modulated via its
bulk-source voltage rather than gate-source voltage. Also
note that the spacing between the bulk-driven mirror's output
current curves increases as Iin increases. The Ih2 term in Eq.
(10) predicts such behavior. For a specific value of Iout and
M2 aspect ratio, VDS2,sat would be approximately equal for
both current mirrors. In Table 1 the measurement data is
compared to the theoretical predictions calculated using Eq.
(10). MOSIS fabrication parameters were used in these
calculations. Eq. (10) provides rout predictions with less than
19% error.
The slope of the Iout curves is greater for the bulk-driven.
current mirror compared to the gate-driven current mirror. In
the bulk-driven case, the maximum possible VSG is applied.
Since rds for a MOSFET is inversely proportional to gatesource voltage, the bulk-driven current mirror's rout is
expected to be less than that of the gate-driven mirror as it
was operated here. The same techniques which improve
current mirror output impedance for the gate-driven case
should also apply to the bulk-driven current mirror. For

The devices in both PMOS simple current mirrors shown

in Figure 4 were fabricated through MOSIS in a 2pm ii-well
run. Identical aspect ratios of 2OOpl2p were chosen. M1 and
M2 are shown connected as a standard s i m p l e current mirror

theory

in Figure 4(a). The PMOS bulk-driven current mirror circuit

I to measured

507wA

is shown in Figure 4(b). For both circuits VDD and Vss were
k 0.75 V, respectively.
Output current measurements for both of the current
mirrors shown in Figure 4 are given i n Figure 5. In each
case, the output node was voltage swept from rail-to-rail for a
given input current. Iin values of 100 PA, 200 PA, 300 PA,
40OpA, and SO0 pA were used to generate thc five curvcs
shown in each of Figure 5's graphs. The gate-driven current

11.72

Table 1. Bulk-driven simple current mirror measured

pcrl'orniniicc and thcorctical prcdictioiis for V S D =
~ 0.75 V.

1974

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0.80
,_

0.60

1.50

~...~
..................?

.................................................................................................. .'.;

1.

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,
,

B 0.40

.
.

.
.

4
0.00
100

-0.50

-0.25

0.00
Vout (V)
(a1

0.25

0.50

.,
,

./

I
.

A,

,........I.>......,..

-0.75

.
,
i
! k
,
,.
.,. + .
I.
,i
i
j
.
.......................... ....,........ ..................>.......................

)j Bulk-:lrivencurrent+rrur
.
:

.
.'

.......... j.......... i........... j...........a ..........i..........;.......... .i........-..,,,

150

200

250

300 350
Iin @A)

400

450

.ux)

Figure 6 - Comparison of the required voltage across the

input transistor of the current mirrors in Fig. 4.

0.75

voltage analog IC design have been demonstrated in a simple

current mirror circuit. This current mirror exhibited input
device voltage drops between 0.1 V and 0.4 V, one volt less
than its gate-driven counterpart. With predicted power
supply voltage of 1.5 V, voltage head-room becomes a
crucial design issue. A high performance low-voltage current
mirror is presently being investigated by applying the bulkdriven technique to a cascode current mirror.
VI. ACKNOWLEDGMENT
-0.75

-0.50

-0.25

0.00

0.25

0.50

0.75

Vout (V)
(b)

Figure 5 - Experimental results for the current mirrors of Fig.

4.: (a) gate-driven and (b) bulk-driven.
example, simulations of the bulk-driven current using Metasoftware's HSpice and the MOSIS BSIM model predict that
doubling the gate-length approximately doubles the current
mirror's output impedance, as is the case of course with the
standard gate-driven simple current mirror.
The voltage required across the input device i s shown in
Fig. 6. Across the entire input current range, the input
device's voltage drop, VSDl, varied from about 1.1 V to 1.4
V for the gate-driven simple current mirror and about 0.1 V
to less than 0.4 V for the bulk-driven simple current mirror.
The curves are nearly parallel and spaced at least one volt
apart. For VDD/VSS = k 0.75 V and Ii, = 500 PA, the gate driven mirror requires more than 90% of the total power
supply voltage across its input device whereas the bulkdriven mirror needs less than 25% of the total power supply
voltage. Using the bulk-driven current mirror rather than the
gate-driven simple current mirror, 65% of the total supply
voltage is made available for other circuitry. This is the
primary benefit bulk-driven current mirrors bring to lowvoltage analog IC design in CMOS technology.
V. CONCLUSIONS

The authors would like to thank Craig Petrie and Gabriel

Rincoii for their technical insights and contributions.
Gratitude is extended to the Georgia Tech Analog
Consortium for supporting this research, AT&T Bell
Laboratories for their instrumentation donations, and MOSIS
for the integrated circuit fabrication.
VII. REFERENCES

1. A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, "LowPower CMOS Digital Design," IEEE JSSC, Vol. 27, No.
4, pp. 473-484, April 1992.
2. M. Nagata, "Limitations, Innovations, and Challenges of
Circuits and Devices into a Half Micrometer and Beyond,"
IEEE JSSC, Vol. 21, No. 4, pp. 465-412, April 1992.
3. Chenming Hu, "Future CMOS Scaling and Reliability",
Proceedings of the IEEE, Vol. 81, No. 5, pp. 682-652,
May 1993.
4. A. L. Coban and P. E. Allen, "A 1.75V rail-to-rail CMOS
op amp," Proc. ISCAS, 1994, pp. 497-500, May 1994.
5. P. E. Allen, B. J. Blalock, and G, A. Rincon, "A IV
CMOS Op Amp Using Bulk-Driven MOSFETs," Proc.
ISSCC, 1995.
6. K. R. Laker and W. M.C. Sansen, Design of Analog
Integrated Circuits ancl Systems, McGraw-Hill, Inc., NY,
pp. 20-22, 1994.

The bulk-driven technique has been presentcd. Wilh this

technique the bulk-source junction is only slightly forward
biased keeping bulk and substrate currents negligible and
maintaining the bulk terminal as a high impedance node.
Some of the incentives the bulk-driven technique offers low-

1975