Scribd
Upload
31 views

User Defined Primitives:: Primitives Are Declared Outside The Module

User Defined Primitives (UDPs) allow modeling of complex sequential and combinational logic in Verilog. UDPs are declared outside modules using the primitive keyword followed by port lists. UDP ports follow rules like a maximum of 10 ports with the output port first. UDP functionality is defined using tables with special symbols representing logic states and transitions. Combinational UDPs map inputs directly to outputs while sequential UDPs can store a current state and be level or edge sensitive. Examples show different types of UDPs including positive and negative D latches.

Uploaded by

LakshmiDevi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
31 views

User Defined Primitives:: Primitives Are Declared Outside The Module

User Defined Primitives (UDPs) allow modeling of complex sequential and combinational logic in Verilog. UDPs are declared outside modules using the primitive keyword followed by port lists. UDP ports follow rules like a maximum of 10 ports with the output port first. UDP functionality is defined using tables with special symbols representing logic states and transitions. Combinational UDPs map inputs directly to outputs while sequential UDPs can store a current state and be level or edge sensitive. Examples show different types of UDPs including positive and negative D latches.

Uploaded by

LakshmiDevi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 9

User Defined Primitives:

Verilog has built in primitives like gates, transmission gates and switches.
If we want to go for complex primitives then Verilog provides UDP.
UDP are used to model sequential and combinational logic

Syntax:
Primitive <name_of_primitive> (Output_port, input_port 1, input_port 2. input_port 10)
Output <port_name>
Input <port_name>
//UDP Function
..
..
Endprimitive
PS:
Primitives are declared outside the module
UDP Port rules:

One output and Inputs up to 10


First port in the declaration must be output followed by input
All UDP ports are scalar
No bidirectional ports
Sequential UDP: Output port must be declared as reg.
Combinational UDP: Output must not be reg type.

UDP Function:

The Function of the UDP starts by Verilog keywords table and ends with keyword endtable.
The functionality of the primitive must be defined in table.
Syntax:
table
//Functionality of the table

endtable

Example1:
Output:

Testbench:

Initial Statement:

Initial statement is used for initialization of sequential UDP.


If we use want to use initial statement, output must be declared as reg.
Initial statement is used to assign a value initially.
Syntax:
Initial <name_of_output_port> = <initial value>

Symbols used in UDP:

In the table we can use special symbols like rising edge, falling edge . To represent the functionality of the
table.
Symbol
Interpretation
Explanation
0
0
Logic 0 on input or output
1
1
Logic 1 on input or output
x or X
x or X
Logic x or X on input or output
No change on output (Used in sequential UDP)
?
0 or 1 or x(X)
? can be 0 or 1 or x(X)
b or B
0 or 1
B or B can be 0 or 1 (X not included)
(vw)
(01), (10), (0X), (X0),
Input transition from logic v to logic w
(1,X), (X,1)
r or R
(01)
Rising input transition (rising edge on input)
f or F
(10)
Falling input transition (falling edge on input)
p or P
(01), (0X), (X1)
Positive input transition (Include x and z)
n or N
(10), (X0), (1X)
Negative input transition (Include x and z)
*
(??)
Any possible input transition

Combinational UDP:

In combinational UDP output is a function of input.


If there is a change in the input then UDP is evaluated and output depend on the inputs from the state table.
Combinational UDP has 2 fields. One for input and other for output separated by colon (:) and terminated by
semicolon (;)
Syntax:
primitive <name_of_primitive> (port list);
<port declaration>
..
.
//UDP functionality
table
0
0
0
:
0
;
0
0
1
:
1
;

endtable
endprimitive

Note:
The port order is very important in UDP.
The order of inputs in the table must corresponds to order of inputs in the port list of UDP in UDP header not
the port (Input) declaration.
Explicit declaration of ports cant be used in combinational UDP.

Example 2: (Port declaration)


Output:

Sequential UDP:
Level sensitive:

The level sensitive sequential UDP is represented same as combinational UDP except the Output declaration.
Output in a sequential UDP is represented as reg
The output declared as reg means thats there is an internal state. Output of UDP is always same as internal
state
In level sensitive sequential UDP an extra field is inserted between input and output. The additional field
represents current state of UDP and considered equivalent to current output value.

Example 3:
Negative D latch
Output:

//when clock is 1 and d is anything then output follow the previous


output

Positive D latch:
Output:

Different input

Edge sensitive:

Edge sensitive behaviour is similar to level sensitive behaviour except that raising or falling edge must be
specified on one of the input
It is illegal to specify more than one edge per line in table

Positive edge:
Output:

Negative edge:

Output:

Short hand notation for above representation:


Positive edge:

Output:

Errors:

You might also like