Max 9271

EVALUATION KIT AVAILABLE
MAX9271
16-Bit GMSL Serializer with Coax or
STP Cable Drive
General Description
Benefits and Features
The MAX9271 compact serializer is designed to drive

50I coax or 100I shielded twisted-pair (STP) cable. The
device pairs with the MAX9272 deserializer.
S Ideal for Camera Applications

Drives Low-Cost 50I Coax Cable and FAKRA
Connectors or 100I STP

Error Detection/Correction

9.6kbps to 1Mbps Control Channel in I2C-to-I2C
Mode with Clock Stretch Capability

Best-in-Class Supply Current: 75mA (max)

Double-Rate Clock for Megapixel Cameras

Serializer Pre/Deemphasis Allows 15m Cable at
Full Speed

32-Pin (5mm x 5mm) TQFN Package with 0.5mm
Lead Pitch
The parallel input is programmable for single or double

input. Double input allows higher pixel clock input frequency by registering two pixels of typical image-sensor
video data before serializing. This doubles the maximum
pixel clock frequency compared to single input.
The device features an embedded control channel that
operates at 9.6kbps to 1Mbps in UART and mixed UART/
I2C modes, and up to 400kbps in I2C mode. Using the
control channel, a microcontroller (FC) is capable of programming serializer, deserializer, and camera (or any
peripheral) registers at any time, independent of video
timing. There is one dedicated GPIO, four optional
GPIOs, and a GPO output, allowing remote power-up of
a camera module, camera frame synchronization, and
other uses. Error-detection and correction coding are
programmable.
For driving longer cables, the device has programmable
pre/deemphasis. Programmable spread spectrum is
available on the serial output. The serial output meets
ISO 10605 and IEC 61000-4-2 ESD standards. The core
supply range is 1.7V to 1.9V and the I/O supply range is
1.7V to 3.6V. The device is available in a 32-pin (5mm
x 5mm) TQFN-EP package with 0.5mm lead pitch and
operates over the -40NC to +105NC temperature range.
Applications
Automotive Camera Systems
Ordering Information and Typical Application Circuit appear

at end of data sheet.
S High-Speed Data Serialization for Megapixel

Cameras
Up to 1.5Gbps Serial-Bit Rate with Single or
Double Input: 6.25MHz to 100MHz Clock
S Multiple Control-Channel Modes for System
Flexibility
9.6kbps to 1Mbps Control Channel in UART-to UART or UART-to-I2C Modes
S Reduces EMI and Shielding Requirements

Output Programmable for 100mV to 500mV
Single-Ended or 100mV to 400mV Differential

Programmable Spread Spectrum on the Serial
Output Reduces EMI

Bypassable Input PLL for Parallel Clock Jitter
Attenuation

Tracks Spread Spectrum on Parallel Input
S Peripheral Features for Camera Power-Up and
Verification

Built-In PRBS Generator for BER Testing of the
Serial Link

Up to Five GPIO Ports

Dedicated Up/Down GPO for Camera Frame
Sync Trigger and Other Uses

Remote/Local Wake-Up from Sleep Mode
S Meets Rigorous Automotive and Industrial
Requirements

-40NC to +105NC Operating Temperature

10kV Contact and 15kV IEC 61000-4-2 ESD
Protection

10kV Contact and 30kV Air ISO 10605 ESD
Protection
For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX9271.related.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxims website at www.maximintegrated.com.
19-6385; Rev 1; 11/12
MAX9271
STP Cable Drive
TABLE OF CONTENTS
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Benefits and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Serial Link Signaling and Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reverse Control Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Data-Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Control Channel and Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Interfacing Command-Byte-Only I2C Devices with UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
UART Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Format for Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Communication with Remote-Side Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C Broadcast Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
GPO/GPI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pre/Deemphasis Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Manual Programming of the Spread-Spectrum Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Additional Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Cyclic Redundancy Check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Maxim Integrated
MAX9271
STP Cable Drive
TABLE OF CONTENTS (continued)
Hamming Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
HS/VS Encoding and/or Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Coax-Mode Splitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Configuration Inputs (CONF1, CONF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuration Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Link Startup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PRBS Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Error Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Dual C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Jitter-Filtering PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PCLKIN Spread Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Changing the Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Providing a Frame Sync (Camera Applications) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Software Programming of the Device Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Three-Level Configuration Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Configuration Blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Compatibility with Other GMSL Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Local Control-Channel Enable (LCCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Internal Input Pulldowns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Choosing I2C/UART Pullup Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC-Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Selection of AC-Coupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Supply Circuits and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power-Supply Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Cables and Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Maxim Integrated
MAX9271
STP Cable Drive
LIST OF FIGURES
Figure 1. Serial-Output Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Output Waveforms at OUT+, OUT- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. Single-Ended Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4. Worst-Case Pattern Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. Parallel Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. I2C Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Differential Output Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Input Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. GPI-to-GPO Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Serializer Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Link Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Power-Up Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 14. Single-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Double-Input Function Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 17. Serial-Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18. GMSL UART Protocol for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19. GMSL UART Data Format for Base Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20. SYNC Byte (0x79) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 21. ACK Byte (0xC3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0) . . . . . . . . . 26
Figure 23. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1) . . . . . . . . . 27
Figure 24. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 25. Bit Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 26. Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 27. Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 28. Format for I2C Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 29. Format for Write to Multiple Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 30. Format for I2C Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 32. Coax-Mode Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. State Diagram, All Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 34. Human Body Model ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Maxim Integrated
MAX9271
STP Cable Drive
LIST OF TABLES
Table 1. Power-Up Default Register Map (see Table 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3. Data-Rate Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4. I2C Bit-Rate Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. TP/Coax Drive Current (CMLLVL = 1000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 6. Serial Output Spread . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 7. Spread Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8. Modulation Coefficients and Maximum SDIV Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 9. Configuration Input Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Startup Procedure for Video-Display Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. Startup Procedure for Image-Sensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 12. MAX9271 Feature Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 13. Double-Function Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 14. Typical Power-Supply Currents (Using Worst-Case Input Pattern) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15. Suggested Connectors and Cables for GMSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16. Register Table (see Table 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Maxim Integrated
MAX9271
STP Cable Drive
ABSOLUTE MAXIMUM RATINGS *
AVDD to EP...........................................................-0.5V to +1.9V
DVDD to EP...........................................................-0.5V to +1.9V
IOVDD to EP..........................................................-0.5V to +3.9V
OUT+, OUT- to EP................................................-0.5V to +1.9V
All other pins to EP............................... -0.5V to (VIOVDD + 0.5V)
OUT+, OUT- short circuit to ground or supply .........Continuous
Continuous Power Dissipation (TA = +70NC)

TQFN (derate 34.5mW/NC above +70NC)...............2758.6mW
Junction Temperature......................................................+150NC
Operating Temperature Range......................... -40NC to +105NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
*EP connected to PCB ground.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)

TQFN
Junction-to-Ambient Thermal Resistance (qJA)...........29C/W
Junction-to-Case Thermal Resistance (qJC)...................1.7C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL= 100I Q1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (LCCEN, DIN_, PCLKIN, HS, VS, MS/HVEN, PWDN)

High-Level Input Voltage
VIH1
Low-Level Input Voltage
VIL1
Input Current
IIN1
0.65 x
VIOVDD
VIN = 0V to VIOVDD
-10
0.35 x
VIOVDD
20
FA
THREE-LEVEL LOGIC INPUTS (CONF0, CONF1)

VIH
VIL
Midlevel Input Current
IINM
Input Current
0.7 x
VIOVDD
(Note 2)
IIN
V
0.3 x
VIOVDD
-10
+10
FA
-150
+150
FA
SINGLE-ENDED OUTPUT (GPO)

High-Level Output Voltage
VOH1
IOUT = -2mA
Low-Level Output Voltage
VOL1
IOUT = 2mA
Output Short-Circuit Current
Maxim Integrated
IOS
VO = 0V
VIOVDD
- 0.2
V
0.2
VIOVDD = 3.0V to 3.6V
16
35
64
12
21
V
mA
MAX9271
STP Cable Drive
DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL= 100I Q1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OPEN-DRAIN INPUTS/OUTPUTS (RX/SDA/EDC, TX/SCL/DBL, GPIO_)

VIH2
VIL2
Input Current
Low-Level Output Voltage
IIN2
VOL2
0.7 x
VIOVDD
V
0.3 x
VIOVDD
(Note 3)
IOUT = 3mA
RX/SDA, TX/SCL
-110
+1
GPIO_
-80
+1
EDC, DBL, BWS
-10
+20
0.4
0.3
FA
DIFFERENTIAL SERIAL OUTPUTS (OUT+, OUT-)

Differential Output Voltage
Change in VOD Between
Complementary Output States
Output Offset Voltage,
(VOUT+ + VOUT-)/2 = VOS
Change in VOS between
Complementary Output States
VOD
300
350
400
610
3.3dB deemphasis setting (Figure 2)
240
425
DVOD
VOS
Preemphasis off
1.1
1.4
DVOS
IOS
Magnitude of Differential
IOSD
Output Termination Resistance

(Internal)
Preemphasis off (Figure 1)

3.3dB preemphasis setting (Figure 2)
RO
VOUT+ or VOUT- = 0V
VOUT+ or VOUT- = 1.9V
mV
25
mV
1.56
25
mV
-62
25
VOD = 0V
From VOUT+, VOUT- to VAVDD
500
mA
25
mA
I
45
54
63
Preemphasis off, high drive (Figure 3)
375
500
625
3.3dB preemphasis setting, high drive

(Figure 2)
435
765
3.3dB deemphasis setting, high drive

(Figure 2)
300
535
VOUT+ or VOUT- = 0V
-69
SINGLE-ENDED SERIAL OUTPUTS (OUT+, OUT-)
Single-Ended Output Voltage
VOUT
IOS
Output Termination Resistance

(Internal)
RO
Maxim Integrated
VOUT+ or VOUT- = 1.9V

From VOUT+, VOUT- to VAVDD
32
45
54
63
mV
mA
I
MAX9271
STP Cable Drive
DC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL= 100I Q1% (differential), EP connected to PCB ground (GND), TA =
-40NC to +105NC, unless otherwise noted. Typical values are at VAVDD = VDVDD = VIOVDD = 1.8V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
27
mV
REVERSE CONTROL-CHANNEL RECEIVER OUTPUTS (OUT+, OUT-)

High Switching Threshold
VCHR
Low Switching Threshold
VCLR
-27
mV
POWER SUPPLY
Worst-Case Supply Current
(Figure 4)
IWCS
Single input,
BWS = 0
fPCLKIN = 25MHz
44
65
fPCLKIN = 50MHz
46
75
Double input,
BWS = 0
fPCLKIN = 50MHz
45
65
fPCLKIN = 100MHz
56
75
mA
Sleep Mode Supply Current
ICCS
Single wake-up receiver enabled
40
100
FA
Power-Down Supply Current
ICCZ
PWDN = EP
70
FA
ESD PROTECTION
Human Body Model, RD = 1.5kI,
CS = 100pF
OUT+, OUT- (Note 4)
All Other Pins (Note 5)
VESD
VESD
IEC 61000-4-2,
RD = 330I,
CS = 150pF
Contact discharge
10
Air discharge
15
ISO 10605,
RD = 2kI,
CS = 330pF
Contact discharge
10
Air discharge
30
Human Body Model, RD = 1.5kI,

CS = 100pF
kV
kV
AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100IQ1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CLOCK INPUT (PCLKIN)
Clock Frequency
Clock Duty Cycle

Clock Transition Time
Clock Jitter
Maxim Integrated
fPCLKIN
DC_
tR, tF_
tJ
BWS = 1, DRS = 1
6.25
12.5
BWS = 0, DRS = 1
8.33
16.66
BWS = 1, DRS = 0
12.5
37.5
BWS = 0, DRS = 0
16.66
50
BWS = 1, DRS = 0, 15-bit double input
25
75
BWS = 0, DRS = 0, 11-bit double input
33.33
100
tHIGH/tT or tLOW/tT (Figure 5, Note 6)

(Figure 5, Note 6)
1.5Gbps bit rate, 300kHz sinusoidal jitter
35
50
MHz
65
ns
800
ps
(pk-pk)
8
MAX9271
STP Cable Drive
AC ELECTRICAL CHARACTERISTICS (continued)
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I Q1% (differential), EP connected to PCB ground (GND),
TA = -40NC to +105NC, unless otherwise noted. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, TA = +25NC)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
9.6
1000
kbps
I2C/UART AND GPIO PORT TIMING

I2C/UART Bit Rate
Output Rise Time
tR
30% to 70%, CL = 10pF to 100pF,

1kI pullup to IOVDD
20
120
ns
Output Fall Time
tF
70% to 30%, CL = 10pF to 100pF,

1kI pullup to IOVDD.
20
120
ns
Input Setup Time
tSET
I2C only (Figure 6, Note 6)
100
ns
ns
Input Hold Time
tHOLD
I2C
only (Figure 6, Note 6)
SWITCHING CHARACTERISTICS (Note 6)

Differential Output Rise/Fall
Time
tR, tF
20% to 80%, VOD R 400Mv, RL = 100I,

serial-bit rate = 1.5Gbps
250
ps
Total Serial Output Jitter

(Differential Output)
tTSOJ1
1.5Gbps PRBS signal, measured at

VOD = 0V differential, preemphasis
disabled (Figure 7)
0.25
UI
Deterministic Serial Output Jitter

(Differential Output)
tDSOJ2
1.5Gbps PRBS signal, measured at

VOD = 0V differential, preemphasis
disabled (Figure 7)
0.15
UI
Total Serial Output Jitter

(Single-Ended Output)
tTSOJ1
1.5Gbps PRBS signal, measured at VO/2,

preemphasis disabled (Figure 3)
0.25
UI
Deterministic Serial Output Jitter

(Single-Ended Output)
tDSOJ2
1.5Gbps PRBS signal, measured at VO/2,

preemphasis disabled (Figure 3)
0.15
UI
Parallel Data Input Setup Time
tSET
(Figure 8)
ns
Parallel Data Input Hold Time
tHOLD
(Figure 8)
ns
GPI-to-GPO Delay
tGPIO
Deserializer GPI to serializer GPO

(Figure 9)
Serializer Delay (Note 7)
350
Spread spectrum enabled
6880
Spread spectrum disabled
3040
Fs
tSD
(Figure 10)
Bits
Link Start Time
tLOCK
(Figure 11)
ms
Power-Up Time
tPU
(Figure 12)
ms
Note 2: To provide a midlevel, leave the input open, or, if driven, put driver in high impedance. High-impedance leakage current
must be less than Q10A.
Note 3: IIN min due to voltage drop across the internal pullup resistor.
Note 4: Specified pin to ground.
Note 5: Specified pin to all supply/ground.
Note 6: Guaranteed by design and not production tested.
Note 7: Measured in serial link bit times. Bit time = 1/(30 x fPCLKIN) for BWS = 0. Bit time = 1/(40 x fPCLKIN) for BWS = 1.
Maxim Integrated
MAX9271
STP Cable Drive
Typical Operating Characteristics
(VAVDD = VDVDD = VIOVDD = 1.8V, DBL = low, TA = +25NC, unless otherwise noted.)
50
45
PREEMPHASIS =
0x01 TO 0x04
10
15
20
25
55
50
45
PREEMPHASIS =
0x01 TO 0x04
35
40
45
50
10
15
20
fPCLKIN = 20MHz
-10
0% SPREAD
-20
-40
-50
-60
-70
1% SPREAD
-80
4% SPREAD
2% SPREAD
-100
25
30
35
0.5% SPREAD
-30
-90
PREEMPHASIS = 0x00
35
30
60
40
PREEMPHASIS = 0x00
35
PREEMPHASIS =
0x0B TO 0x0F
OUTPUT POWER SPECTRUM (dBm)
55
PRBS ON,
COAX MODE
65
SUPPLY CURRENT (mA)
60
40
40
18.5
19.0
19.5
20.0
20.5
21.0
21.5
PCLKIN FREQUENCY (MHz)
OUTPUT POWER SPECTRUM vs. PCLKIN

FREQUENCY (VARIOUS SPREAD)
SERIAL LINK SWITCHING PATTERN

WITH 6dB PREEMPHASIS
(PARALLEL BIT RATE = 50MHz, 10m STP CABLE)
SERIAL LINK SWITCHING PATTERN

WITH 6dB PREEMPHASIS
(PARALLEL BIT RATE = 50MHz, 20m COAX CABLE)
0
OUTPUT POWER SPECTRUM (dBm)
70
fPCLKIN = 50MHz
-10
0% SPREAD
-20
0.5% SPREAD
MAX9271 toc05
MAX9271 toc06
MAX9271 toc04
SUPPLY CURRENT (mA)
65
PREEMPHASIS =
0x0B TO 0x0F
OUTPUT POWER SPECTRUM vs. PCLKIN

FREQUENCY (VARIOUS SPREAD)
MAX9271 toc02
PRBS ON,
COAX MODE
MAX9271 toc01
70
SUPPLY CURRENT vs.

PCLKIN FREQUENCY (BWS = 1)
MAX9271 toc03
SUPPLY CURRENT vs.

PCLKIN FREQUENCY (BWS = 0)
-30
-40
-50
-60
-70
1% SPREAD
-80
4% SPREAD
-90
2% SPREAD
-100
47
48
49
50
51
52
50mV/div
53
200ps/div
1.5Gbps
50mV/div
200ps/div
1.5Gbps
6dB PE, EQ OFF

NO PE, 10.7dB EQ
NO PE, EQ OFF
BER CAN BE AS LOW AS 10-12 FOR CABLE
LENGTHS LESS THAN 10m
0
0
10
15
STP CABLE LENGTH (m)
Maxim Integrated
60
MAX9271 toc08
40
6dB PE, EQ OFF

NO PE, 10.7dB EQ
NO PE, EQ OFF
20
10
15
COAX CABLE LENGTH (m)
20
10m STP CABLE OPTIMUM PE/EQ SETTINGS
50
6dB PE, EQ OFF
40
30
NO PE, 10.7dB EQ
NO PE, EQ OFF
20
10
BER CAN BE AS LOW AS 10-12 FOR CABLE

LENGTHS LESS THAN 10m
0
20
MAXIMUM PCLKIN FREQUENCY vs.

ADDITIONAL DIFFERENTIAL CL (BER < 10-10)
40
20
60
MAX9271 toc07
OPTIMUM PE/EQ SETTINGS
60

COAX CABLE LENGTH (BER 10-10)
BER CAN BE AS LOW AS 10-12 FOR CL < 4pF

FOR OPTIMUM PE/EQ SETTINGS
0
25
MAX9271 toc09

STP CABLE LENGTH (BER 10-10)
10
ADDITIONAL DIFFERENTIAL LOAD CAPACITANCE (pF)
10
MAX9271
STP Cable Drive
RX/SDA/EDC
AVDD
OUT+
OUT-
CONF1
CONF0
LCCEN
TOP VIEW
TX/SCL/DBL
Pin Configuration
24
23
22
21
20
19
18
17
PCLKIN 25
16
PWDN
DIN0 26
15
MS/HVEN
DIN1 27
14
GPIO1/BWS
13
GPO
12
IOVDD
11
DIN15/VS
10
DIN14/HS
DIN13/GPIO5
DIN2 28
MAX9271
DVDD 29
DIN3 30
DIN4 31
EP*
+
4
DIN9
DIN10/GPIO2
DIN11/GPIO3
DIN12/GPIO4
AVDD
DIN8
DIN6
DIN7
DIN5 32
TQFN
(5mm x 5mm x 0.75mm)
*CONNECT EP TO GROUND PLANE
Pin Description
PIN
NAME
14, 26, 27, 28,

30, 31, 32
DIN0DIN9
5, 22
AVDD
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller capacitor closest to AVDD.
69
DIN10/
GPIO2DIN13/
GPIO5
Parallel Data Inputs/GPIO. Defaults to parallel data input on power-up.

Parallel data input has internal pulldown to EP.
GPIO_ has an open-drain output with internal 60kI pullup to IOVDD. See Table 1 for
programming details.
10
DIN14/HS
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP. Defaults to parallel data
input on power-up.
Horizontal sync input when VS/HS encoding is enabled (Table 2).
11
DIN15/VS
Parallel Data Input/Vertical Sync with Internal Pulldown to EP. Defaults to parallel data
input on power-up.
Vertical sync input when VS/HS encoding is enabled (Table 2).
12
IOVDD
Maxim Integrated
FUNCTION
Parallel Data Inputs with Internal Pulldown to EP
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with
0.1FF and 0.001FF capacitors as close as possible to the device with the smallest value
capacitor closest to IOVDD.
11
MAX9271
STP Cable Drive
Pin Description (continued)
PIN
NAME
13
GPO
FUNCTION
General-Purpose Output. GPO follows the GMSL deserializer GPI (or INT) input.
GPO = low upon power-up and when PWDN = low.
GPIO1/BWS
GPIO/Bus Width Select Input. Function is determined by the state of LCCEN (Table 13).
GPIO1 (LCCEN = high): Open-drain, general-purpose input/output with internal 60kI
pullup to IOVDD.
BWS (LCCEN = low): Input with internal pulldown to EP. Set BWS = low for 22-bit input
latch. Set BWS = high for 30-bit input latch.
15
MS/HVEN
Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is
determined by the state of LCCEN (Table 13).
MS (LCCEN = high): Set MS = low to select base mode. Set MS = high to select the
bypass mode.
HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DIN14/HS and
DIN15/VS. Set HVEN = low to use DIN14/HS and DIN15/VS as parallel data inputs.
16
PWDN
Active-Low, Power-Down Input with Internal Pulldown to EP. Set PWDN low to enter
power-down mode to reduce power consumption.
17
LCCEN
Local Control-Channel Enable Input with Internal Pulldown to EP. LCCEN = high enables
the control-channel interface pins. LCCEN = low disables the control-channel interface
pins and selects an alternate function on the indicated pins (Table 13).
18
CONF0
Configuration 0. Three-level configuration input (Table 9).
19
CONF1
Configuration 1. Three-level configuration input (Table 9).
14
20
OUT-
Inverting Coax/Twisted-Pair Serial Output
21
OUT+
Noninverting Coax/Twisted-Pair Serial Output
RX/SDA/EDC
Receive/Serial Data/Error-Detection/Correction. Function is determined by the state of

LCCEN (Table 13).
RX/SDA (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART
mode, RX/SDA is the Rx input of the serializers UART. In I2C mode, RX/SDA is the
SDA input/output of the serializers I2C master/slave. .RX/SDA has an open-drain driver
and requires a pullup resistor.
EDC (LCCEN = low): Input with internal pulldown to EP. Set EDC = high to enable
error-detection correction. Set EDC = low to disable error-detection correction.
24
TX/SCL/DBL
Transmit/Serial Clock/Double Mode. Function is determined by the state of LCCEN

(Table 13).
TX/SCL (LCCEN = high): Input/output with internal 30kI pullup to IOVDD. In UART
mode, TX/SCL is the Tx output of the serializers UART. In the I2C mode, TX/SCL is
the SCL input/output of the serializers I2C master/slave. .TX/SCL has an open-drain
driver and requires a pullup resistor.
DBL (LCCEN = low): Input with internal pulldown to EP. Set DBL = high to use doubleinput mode. Set DBL = low to use single-input mode.
25
PCLKIN
29
DVDD
EP
23
Maxim Integrated
Parallel Clock Input with Internal Pulldown to EP. Latches parallel data inputs and
provides the PLL reference clock.
1.8V Digital Power Supply. Bypass DVDD to EP with 0.1FF and 0.001FF capacitors as
close as possible to the device with the smaller value capacitor closest to DVDD.
Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB
ground plane through an array of vias for proper thermal and electrical performance.
12
MAX9271
STP Cable Drive
Functional Diagram
PCLKIN
SSPLL
FILTER
PLL
MAX9271
CLKDIV
DIN0DIN9
OUT+
DIN10/GPIO2
PARALLEL
TO SERIAL
DIN11/GPIO3
DIN12/GPIO4
DIN13/GPIO5
SINGLE-/
DOUBLEINPUT
LATCH
GPO
CML TX
SCRAMBLE/
CRC/
HAMMING/
8b/10b
ENCODE
FIFO
GPIO1/BWS
FCC
OUT-
RX
REVERSE
CONTROL
CHANNEL
GPIO
DIN14/HS
DIN15/VS
UART/I2C
TX/SCL/ RX/SDA/
DBL
EDC
Maxim Integrated
13
MAX9271
STP Cable Drive
RL/2
OUT+
VOD
VOS
OUT-
RL/2
GND
((OUT+) + (OUT-))/2
OUTVOS(+)
VOS(-)
VOS(-)
OUT+
DVOS = |VOS(+) - VOS(-)|
VOD(+)
VOD = 0V
VOD(-)
VOD(-)
DVOD = |VOD(+) - VOD(-)|
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
OUT+
VOD(P)
VOS
VOD(D)
OUT+
OR
OUT-
VO/2
VO
VO/2
VO
OUT-
Figure 3. Single-Ended Output Template

SERIAL-BIT
TIME
PCLKIN
Figure 2. Output Waveforms at OUT+, OUT-
DIN_
NOTE: PCLKIN PROGRAMMED FOR RISING LATCH EDGE.
Figure 4. Worst-Case Pattern Input
Maxim Integrated
14
MAX9271
STP Cable Drive
tT
VIH MIN
tHIGH
PCLKIN
VIL MAX
tR
tF
tLOW
Figure 5. Parallel Clock Input Requirements
START
CONDITION
(S)
PROTOCOL
BIT 7
MSB
(A7)
tSU;STA
tLOW
BIT 6
(A6)
tHIGH
BIT 0
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
1/fSCL
SCL
tSP
tBUF
tr
tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
Figure 6. I2C Timing Parameters
800mVP-P
tTSOJ1
2
tTSOJ1
2
Figure 7. Differential Output Template

Maxim Integrated
15
MAX9271
STP Cable Drive
VIH MIN
PCLKIN
VIL MAX
tSET
tHOLD
VIH MIN
VIH MIN
VIL MAX
VIL MAX
DIN_
NOTE: PCLKIN PROGRAMMED FOR RISING LATCHING EDGE.
Figure 8. Input Setup and Hold Times
VIH_MIN
DESERIALIZER
GPI
VIL_MAX
tGPIO
SERIALIZER
GPO
tGPIO
VOH_MIN
VOL_MAX
Figure 9. GPI-to-GPO Delay
Maxim Integrated
16
MAX9271
STP Cable Drive
EXPANDED TIME SCALE
DIN_
N+1
N+3
N+2
N+4
PCLKIN
N-1
OUT+/tSD
FIRST BIT
LAST BIT
Figure 10. Serializer Delay
PCLKIN
tLOCK
350Fs
SERIAL LINK INACTIVE
REVERSE CONTROL CHANNEL

DISABLED
SERIAL LINK ACTIVE
CHANNEL
DISABLED
REVERSE CONTROL CHANNEL

AVAILABLE
PWDN MUST BE HIGH
Figure 11. Link Startup Time
Maxim Integrated
17
MAX9271
STP Cable Drive
PCLKIN
PWDN
VIH1
tPU
POWERED DOWN
POWERED UP,
SERIAL LINK INACTIVE
POWERED UP, SERIAL LINK ACTIVE

350s
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
REVERSE CONTROL
CHANNEL DISABLED
REVERSE CONTROL
CHANNEL ENABLED
Figure 12. Power-Up Delay
Detailed Description
The MAX9271 serializer, when paired with the MAX9272
deserializer, provides the full set of operating features,
but offers basic functionality when paired with any GMSL
deserializer.
The serializer has a maximum serial-bit rate of 1.5Gbps
for 15m or more of cable and operates up to a maximum
input clock of 50MHz in 16-bit, single-input mode, or
75MHz/100MHz in 15-bit/11-bit, double-input mode,
respectively. Pre/deemphasis, along with the GMSL
deserializer channel equalizer, extends the link length
and enhances link reliability.
The control channel enables a FC to program serializer and deserializer registers and program registers
on peripherals. The FC can be located at either end of
the link or at both ends. Two modes of control-channel
operation are available with associated protocols and
data formats. Base mode uses either I2C or GMSL UART
protocol, while bypass mode uses a user-defined UART
protocol.
Spread spectrum is available to reduce EMI on the serial
output. The serial output complies with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
Maxim Integrated
Register Mapping
Registers set the operating conditions of the serializer

and are programmed using the control channel in base
mode. The serializer holds its device address and the
device address of the deserializer it is driving. Similarly,
the driven deserializer holds its device address and the
address of the serializer by which it is driven. Whenever a
device address is changed, the new address should be
written to both devices. The default device address of the
MAX9271 serializer (or any GMSL serializer) is 0x80 and
the default device address of any GMSL deserializer is
0x90 (Table 1). Registers 0x00 and 0x01 in both devices
hold the device addresses.
Input Bit Map
The parallel input functioning and width depends on

settings of the double-/single-input mode (DBL), HS/VS
encoding (HVEN), error correction (EDC), and bus width
(BWS) pins. DINA is the input latched by the pixel clock
in single-input mode, or the inputs latched on the first
pixel clock in double-input mode. DINB are the inputs
latched on the second pixel clock in double-input mode.
Table 2 lists the bit map for the control pin settings.
18
MAX9271
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 16)
REGISTER
ADDRESS (hex)
POWER-UP
DEFAULT (hex)
0x00
0x80
SERID = 1000000, serializer device address

CFGBLOCK = 0, registers 0x00 to 0x1F are read/write
0x01
0x90
DESID = 1001000, deserializer device address

RESERVED = 0
0x02
0x1F
SS = 000 no spread spectrum

RESERVED = 1
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
0x03
0x00
AUTOFM = 00, calibrate spread-modulation rate only once after locking

SDIV = 000000, autocalibrate sawtooth divider
0x87
SEREN = 1, serial link enabled

CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
SLEEP = 0, sleep mode disabled (see the Link Startup Procedure section)
INTTYPE = 01, local control channel uses UART
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
0x05
0x00
I2CMETHOD = 0, I2C packets include register address

ENJITFILT = 0, jitter filter disabled
PRBSLEN = 00, continuous PRBS length
RESERVED = 00
ENWAKEN = 0, OUT- wake-up receiver disabled
ENWAKEP = 1, OUT+ wake-up receiver enabled
0x06
0x80, 0xA0
CMLLVL = 1000 or 1010, output level determined by the state of CONF1 and CONF0
at power-up
PREEMP = 0000, preemphasis disabled
0x07
0xXX
DBL = 0 or 1, single-/double-input mode setting determined by the state of LCCEN

and TX/SCL/DBL at startup
DRS = 0, high data-rate mode
BWS = 0 or 1, bit width setting determined by the state of LCCEN and GPIO1/BWS
at startup
ES = 0 or 1, edge-select input setting determined by the state of LCCEN and
TX/SCL/ES at startup
RESERVED = 0
HVEN = 0 or 1, HS/VS tracking encoding setting determined by the state of LCCEN
and MS/HVEN at startup
EDC = 00 or 10, error-detection/correction setting determined by the state of LCCEN
and RX/SDA/EDC at startup
0x08
0x00
INVVS = 0, serializer does not invert VSYNC

INVHS = 0, serializer does not invert HSYNC
RESERVED = 000000
0x04
Maxim Integrated
POWER-UP DEFAULT SETTINGS

(MSB FIRST)
19
MAX9271
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER
ADDRESS (hex)
POWER-UP
DEFAULT (hex)
0x09
0x00
I2CSRCA = 0000000, I2C address translator source A is 0x00

RESERVED = 0
0x0A
0x00
I2CDSTA = 0000000, I2C address translator destination A is 0x00

RESERVED = 0
0x0B
0x00
I2CSRCB = 0000000, I2C address translator source B is 0x00

RESERVED = 0
0x0C
0x00
I2CDSTB = 0000000, I2C address translator destination B is 0x00

RESERVED = 0
0xB6
I2CLOCACK = 1, acknowledge generated when forward channel is not available

I2CSLVSH = 01, 469ns/234ns I2C setup/hold time
I2CMSTBT = 101, 339kbps (typ) I2C-to-I2C master bit-rate setting
I2CSLVTO = 10, 1024Fs (typ) I2C-to-I2C slave remote timeout
0x42
DIS_REV_P = 0, OUT+ reverse channel receiver enabled

DIS_REV_N = 1, OUT- reverse channel receiver disabled
GPIO5EN = 0, GPIO5 disabled
GPIO1EN = 1, GPIO1 enabled
RESERVED = 0
0xFE
RESERVED = 11
GPIO5OUT = 1, GPIO5 set
SETGPO = 0, GPO set low
0x3E
RESERVED = 00
GPIO5IN = 1, GPIO5 is input
GPO_L = 0, GPO is set low
0x00
ERRGRATE = 00, generate an error every 2560 bits

ERRGTYPE = 0, generate single-bit errors
ERRGCNT = 00, continuously generate errors
ERRGPER = 0, disable periodic error generation
ERRGEN = 0, disable error generation
0x0D
0x0E
0x0F
0x10
0x11
Maxim Integrated

(MSB FIRST)
high
high
high
high
high
high
high
high
high
high
20
MAX9271
STP Cable Drive
Table 1. Power-Up Default Register Map (see Table 16) (continued)
REGISTER
ADDRESS (hex)
POWER-UP
DEFAULT (hex)

(MSB FIRST)
0x12
0x40
RESERVED = 01000000
0x13
0x22
RESERVED = 00100010
0x14
0xXX
RESERVED = XXXXXXXX
0x15
0x00
CXTP = 0, CXTP is low

I2CSEL = 0, input is low
LCCEN = 0, local control channel disabled
RESERVED = 000
OUTPUTEN = 0, output disabled
PCLKDET = 0, no valid PCLKIN detected
0x16
0xXX
(read only)
RESERVED = XXXXXXXX
0x17
0xXX
(read only)
RESERVED = XXXXXXXX
0x1E
0x09
(read only)
ID = 00001001, device ID is 0x09
0x1F
0x0X
(read only)
RESERVED = 000
CAPS = 0, serializer is not HDCP capable
REVISION = XXXX, revision number
X = Dont care.
Table 2. Input Map

EDC
BWS
DBL
HVEN
DINA
DINB*
SERIAL LINK WORD BITS
0:15
0:15
0:13, HS, VS
0:13
0:10
0:10
0:21
0:10, HS, VS
0:10, HS, VS
0:21
0:15
0:15
0:13, HS, VS
0:13
0:14
0:14
0:29
0:13, HS, VS
0:13, HS, VS
0:13, 15:28
0:15
0:15
0:13, HS, VS
0:13
0:7
0:7
0:15
0:7, HS, VS
0:7, HS, VS
0:13
0:15
0:15
0:13, HS, VS
0:13
0:11
0:11
0:23
0:11, HS, VS
0:11, HS, VS
0:23
*In double-input mode (DBL = 1), DINA is latched on the first cycle of PCLKIN and DINB is latched on the second cycle of PCLKIN.
Maxim Integrated
21
MAX9271
STP Cable Drive
The parallel input has two input modes: single- and
double-rate input. In single-input mode, LATCH A stores
data from DIN_ every PCLKIN cycle (Figure 13). Parallel
data from LATCH A is then sent to the scrambler for
serialization (Figure 14). The device accepts pixel clocks
from 6.25MHz to 50MHz.
In double-input mode, LATCH B stores two input words

(Figure 15). Data from LATCH B is sent to the scrambler
as a combined word. The MAX9272 deserializer outputs
the combined word (single-output mode) or two half-sized
words (double-output mode). The serializer/deserializer
use pixel clock rates from 33.3MHz to 100MHz for 11-bit,
double-input mode and 25MHz to 75MHz for 15-bit,
double-input mode. See Figure 16 for timing details.
PCLKIN
DIN0DIN15
LATCH A
FIRST WORD
SECOND WORD
FIRST WORD
THIRD WORD
SECOND WORD
FOURTH WORD
THIRD WORD
FOURTH WORD
Figure 13. Single-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
MAX9271
DIN0DIN14
OR
DIN0DIN10
DIN0DIN15
INPUT
LATCH A
INPUT
LATCH B
INPUT
LATCH A
MAX9271
2
PCLKIN
Figure 14. Single-Input Function Block
Maxim Integrated
PCLKIN
Figure 15. Double-Input Function Block
22
MAX9271
STP Cable Drive
PCLKIN
DIN0DIN14
OR
DIN0DIN10
FIRST WORD
LATCH A
SECOND WORD
THIRD WORD
FOURTH WORD
FIRST WORD
LATCH B
THIRD WORD
FIRST AND SECOND WORD
THIRD AND FOURTH WORD
Figure 16. Double-Input Waveform (Latch on Rising Edge of PCLKIN Selected)
Serial Link Signaling and Data Format
The serializer uses differential CML signaling to drive

twisted-pair cable and single-ended CML to drive coax
cable. The output amplitude is programmable.
Input data is scrambled and then 8b/10b coded. The

deserializer recovers the embedded serial clock, then
samples, decodes, and descrambles the data. In 24-bit
or 32-bit mode, 22 or 30 bits contain the video data
and/or error-correction bits, if used. The 23rd or 31st bit
carries the forward control-channel data. The last bit is
the parity bit of the previous 23 or 31 bits. (Figure 17).
Reverse Control Channel
The serializer uses the reverse control channel to receive

I2C/UART and GPO signals from the deserializer in the
opposite direction of the video stream. The reverse
control channel and forward video data coexist on the
same serial cable, forming a bidirectional link. The
reverse control channel operates independently from the
forward control channel. The reverse control channel is
available 2ms after power-up. The serializer temporarily
disables the reverse control channel for 350Fs after starting/stopping the forward serial link.
Data-Rate Selection
The serializer/deserializer use DRS, DBL, and BWS to set

the PCLKIN frequency range (Table 3). Set DRS = 1 for
a PCLKIN frequency range of 6.25MHz to 12.5MHz (32bit, single-input mode) or 8.33MHz to 16.66MHz (24-bit,
single-input mode). Set DRS = 0 for normal operation.
It is not recommended to use double-input mode when
DRS = 1.
Maxim Integrated
Control Channel and Register

Programming
The control channel is available for the FC to send and

receive control data over the serial link simultaneously
with the high-speed data. The FC controls the link from
either the serializer or the deserializer side. The control
channel between the FC and serializer or deserializer
runs in base mode or bypass mode, according to the
mode selection (MS/HVEN) input of the device connected
to the FC. Base mode is a half-duplex control channel and
bypass mode is a full-duplex control channel.
UART Interface
In base mode, the FC is the host and can access the

registers of both the serializer and deserializer from
either side of the link using the GMSL UART protocol.
The FC can also program the peripherals on the remote
side by sending the UART packets to the serializer or
deserializer, with the UART packets converted to I2C
by the device on the remote side of the link. The FC
communicates with a UART peripheral in base mode
(through INTTYPE register settings), using the half-duplex
default GMSL UART protocol of the serializer/deserializer. The device addresses of the serializer/deserializer in
base mode are programmable. The default value is 0x80
for the serializer and 0x90 for the deserializer.
When the peripheral interface is I2C, the serializer/
deserializer convert UART packets to I2C that have
device addresses different from those of the serializer or
deserializer. The converted I2C bit rate is the same as the
original UART bit rate.
23
MAX9271
STP Cable Drive
24 BITS
D0
D1
VIDEO AND ERRORCORRECTION DATA
32 BITS
D21
FCC
PCB
D0
D1
D29
FORWARD
CONTROLCHANNEL BIT
VIDEO AND ERRORCORRECTION DATA
FCC
PCB
FORWARD
CONTROLCHANNEL BIT
PACKET
PARITY
CHECK BIT
PACKET
PARITY
CHECK BIT
NOTE: SERIAL DATA SHOWN BEFORE SCRAMBLING AND 8b/10b ENCODING
Figure 17. Serial-Data Format
Table 3. Data-Rate Selection Table

DRS SETTING
DBL SETTING
BWS SETTING
PCLKIN RANGE (MHz)
0
0
0 (single input)
0 (24-bit mode)
16.66 to 50
1 (32-bit mode)
12.5 to 35
1 (double input)
33.3 to 100
25 to 75
8.33 to 16.66
6.25 to 12.5
Do not use
Do not use
The deserializer uses differential line coding to send

signals over the reverse channel to the serializer. The
bit rate of the control channel is 9.6kbps to 1Mbps in
both directions. The serializer/deserializer automatically
detect the control-channel bit rate in base mode. Packet
bit-rate changes can be made in steps of up to 3.5
times higher or lower than the previous bit rate. See the
Changing the Clock Frequency section for more information on changing the control-channel bit rate.
Figure 18 shows the UART protocol for writing and reading in base mode between the FC and the serializer/
deserializer.
Figure 19 shows the UART data format. Figure 20 and
Figure 21 detail the formats of the SYNC byte (0x79)
and the ACK byte (0xC3). The FC and the connected
slave chip generate the SYNC byte and ACK byte,
respectively. Events such as device wake-up and GPI
Maxim Integrated
generate transitions on the control channel that can be

ignored by the FC. Data written to the serializer/deserializer registers do not take effect until after the ACK byte
is sent. This allows the FC to verify that write commands
are received without error, even if the result of the write
command directly affects the serial link. The slave uses
the SYNC byte to synchronize with the host UARTs data
rate. If the GPI or MS/HVEN inputs of the deserializer toggle while there is control-channel communication, or if a
line fault occurs, the control-channel communication is
corrupted. In the event of a missed or delayed acknowledge (~1ms due to control-channel timeout), the FC
should assume there was an error in the packet when the
slave device received it, or that an error occurred during
the response from the slave device. In base mode, the
FC must keep the UART Tx/Rx lines high for 16 bit times
before starting to send a new packet.
24
MAX9271
STP Cable Drive
WRITE DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
BYTE 1
BYTE N
ACK
MASTER WRITES TO SLAVE
MASTER READS FROM SLAVE

READ DATA FORMAT
SYNC
DEV ADDR + R/W
REG ADDR
NUMBER OF BYTES
MASTER WRITES TO SLAVE
ACK
BYTE 1
BYTE N
MASTER READS FROM SLAVE
Figure 18. GMSL UART Protocol for Base Mode
1 UART FRAME
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY
FRAME 2
FRAME 1
STOP
STOP
FRAME 3
START
STOP
START
Figure 19. GMSL UART Data Format for Base Mode
START
D0
D1
D2
D3
D4
D5
D6
D7
Figure 20. SYNC Byte (0x79)
Maxim Integrated
PARITY STOP
START
D0
D1
D2
D3
D4
D5
D6
D7
PARITY STOP
Figure 21. ACK Byte (0xC3)
25
MAX9271
STP Cable Drive
As shown in Figure 22, the remote-side device converts
packets going to or coming from the peripherals from
UART format to I2C format and vice versa. The remote
device removes the byte number count and adds or
receives the ACK between the data bytes of I2C. The I2C
bit rate is the same as the UART bit rate.
Interfacing Command-Byte-Only I2C
Devices with UART
The serializer/deserializer UART-to-I2C conversion can
interface with devices that do not require register addresses, such as the MAX7324 GPIO expander. In this mode,
the I2C master ignores the register address byte and
directly reads/writes the subsequent data bytes (Figure
23). Change the communication method of the I2C master using the I2CMETHOD bit. I2CMETHOD = 1 sets
command-byte-only mode, while I2CMETHOD = 0 sets
normal mode where the first byte in the data stream is
the register address.
UART Bypass Mode

In bypass mode, the serializer/deserializer ignore UART
commands from the FC and the FC communicates with
the peripherals directly using its own defined UART protocol. The FC cannot access the serializer/deserializer
registers in this mode. Peripherals accessed through the
forward control channel using the UART interface need
to handle at least one PCLKIN period Q10ns of jitter due
to the asynchronous sampling of the UART signal by
PCLKIN. Set MS/HVEN = high to put the control channel
into bypass mode. For applications with the FC connected to the deserializer, there is a 1ms wait time between
setting MS/HVEN high and the bypass control channel
being active. There is no delay time when switching to
bypass mode when the FC is connected to the serializer. Do not send a logic-low value longer than 100Fs to
ensure proper GPO functionality. Bypass mode accepts
bit rates down to 10kbps in either direction. See the GPO/
GPI Control section for GPO functionality limitations. The
control-channel data pattern should not be held low
longer than 100Fs if GPO control is used.
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)

FC
SERIALIZER/DESERIALIZER
11
11
SYNC FRAME
DEVICE ID + WR
11
REGISTER ADDRESS
PERIPHERAL
1
S
7
DEV ID
1 1
W A
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)

FC
11
11
11
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS
PERIPHERAL
1
S
7
DEV ID
1 1
W A
: MASTER TO SLAVE
11
NUMBER OF BYTES
8
REG ADDR
11
DATA 0
1
A
8
DATA 0
11
NUMBER OF BYTES
8
REG ADDR
11
DATA N
1 1
A S
: SLAVE TO MASTER
11
ACK FRAME
7
DEV ID
S: START
1 1
R A
8
DATA 0
P: STOP
1
A
11
ACK FRAME
1
A
8
DATA N
11
DATA 0
8
DATA N
1 1
A P
11
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 22. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
Maxim Integrated
26
MAX9271
STP Cable Drive
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)
FC
11
SYNC FRAME
11
11
DEVICE ID + WR
REGISTER ADDRESS
FC
PERIPHERAL
1
7
S DEV ID
11
NUMBER OF BYTES
11
DATA 0
1 1
W A
8
DATA 0
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)

11
11
11
11
SYNC FRAME
DEVICE ID + RD
REGISTER ADDRESS NUMBER OF BYTES
PERIPHERAL
1
S
: MASTER TO SLAVE
11
DATA N
: SLAVE TO MASTER
11
ACK FRAME
7
DEV ID
S: START
1 1
R A
8
DATA 0
P: STOP
11
ACK FRAME
1
A
8
DATA N
11
DATA 0
1
A
8
DATA N
1 1
A P
11
DATA N
1 1
A P
A: ACKNOWLEDGE
Figure 23. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 1)
I2C Interface
In I2C-to-I2C mode the serializers control-channel interface sends and receives data through an I2C-compatible
2-wire interface. The interface uses a serial-data line
(SDA) and a serial-clock line (SCL) to achieve bidirectional communication between master and slave(s). A
FC master initiates all data transfers to and from the
device and generates the SCL clock that synchronizes
the data transfer. When an I2C transaction starts on the
local-side devices control-channel port, the remote-side
devices control-channel port becomes an I2C master
that interfaces with remote-side I2C perhipherals. The I2C
master must accept clock stretching, which is imposed
by the serializer (holding SCL low). The SDA and SCL
lines operate as both an input and an open-drain output.
Pullup resistors are required on SDA and SCL. Each
transmission consists of a START condition (Figure 6)
sent by a master, followed by the devices 7-bit slave
address plus a R/W bit, a register address byte, one or
more data bytes, and finally a STOP condition.
START and STOP Conditions
Both SCL and SDA remain high when the interface is not
busy. A master signals the beginning of a transmission
with a START (S) condition by transitioning SDA from
high to low while SCL is high (see Figure 24). When the
Maxim Integrated
master has finished communicating with the slave, it

issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission.
Bit Transfer
One data bit is transferred during each clock pulse
(Figure 25). The data on SDA must remain stable while
SCL is high.
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to handshake receipt of each byte of data (Figure 26).
Thus, each byte transferred effectively requires 9 bits.
The master generates the 9th clock pulse, and the recipient pulls down SDA during the acknowledge clock pulse.
The SDA line is stable low during the high period of the
clock pulse. When the master is transmitting to the slave
device, the slave device generates the acknowledge bit
because the slave device is the recipient. When the slave
device is transmitting to the master, the master generates
the acknowledge bit because the master is the recipient.
The device generates an acknowledge even when the
forward control channel is not active (not locked). To prevent acknowledge generation when the forward control
channel is not active, set the I2CLOCACK.
27
MAX9271
STP Cable Drive
SDA
SCL
S
START
CONDITION
STOP
CONDITION
Figure 24. START and STOP Conditions
SDA
SCL
DATA LINE STABLE;

DATA VALID
CHANGE OF DATA
ALLOWED
Figure 25. Bit Transfer
START
CONDITION
CLOCK PULSE FOR

ACKNOWLEDGE
SCL
SDA
BY
TRANSMITTER
SDA
BY
RECEIVER
S
Figure 26. Acknowledge
Maxim Integrated
28
MAX9271
STP Cable Drive
followed by at least one byte of information. The first
byte of information is the register address or command
byte. The register address determines which register of
the device is to be written by the next byte, if received.
If a STOP (P) condition is detected after the register
address is received, the device takes no further action
beyond storing the register address (Figure 28). Any
bytes received after the register address are data bytes.
The first data byte goes into the register selected by the
register address, and subsequent data bytes go into
subsequent registers (Figure 29). If multiple data bytes
are transmitted before a STOP condition, these bytes
are stored in subsequent registers because the register
addresses autoincrement.
Slave Address
The serializer/deserializer have a 7-bit-long slave address.
The bit following a 7-bit slave address is the R/W bit,
which is low for a write command and high for a read
command. The slave address is 10000001 for read commands and 10000000 for write commands. See Figure 27.
Bus Reset
The device resets the bus with the I2C START condition
for reads. When the R/W bit is set to 1, the serializer/
deserializer transmit data to the master, thus the master
is reading from the device.
Format for Writing
A write to the serializer/deserializer comprises the transmission of the slave address with the R/W bit set to zero,
SDA
R/W
MSB
ACK
LSB
SCL
Figure 27. Slave Address
0 = WRITE
ADDRESS = 0x80
REGISTER ADDRESS = 0x00
REGISTER 0x00 WRITE DATA
D7
D6
D5
D4
D3
D2
D1
D0
S = START BIT
P = STOP BIT
A = ACK
D_ = DATA BIT
Figure 28. Format for I2C Write
0 = WRITE
ADDRESS = 0x80
D7
D6
D5
D4
D3
D2
D1
D0
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
D1
D0
D7
D6
D5
D4
D3
D2
Figure 29. Format for Write to Multiple Registers

Maxim Integrated
29
MAX9271
STP Cable Drive
bit rate different than 400kbps, local- and remote-side
I2C setup and hold times should be adjusted by setting
the SLV_SH register settings on both sides.
Format for Reading

The serializer/deserializer are read using the internally
stored register address as an address pointer, the same
way the stored register address is used as an address
pointer for a write. The pointer autoincrements after each
data byte is read using the same rules as for a write. Thus,
a read is initiated by first configuring the register address
by performing a write (Figure 30). The master can now
read consecutive bytes from the device, with the first data
byte being read from the register address pointed by
the previously written register address. Once the master
sends a NACK, the device stops sending valid data.
I2C Address Translation
The serializer supports I2C address translation for up to

two device addresses. Use address translation to assign
unique device addresses to peripherals with limited
I2C addresses. Source addresses (address to translate
from) are stored in registers 0x09 and 0x0B. Destination
addresses (address to translate to) are stored in registers
0x0A and 0x0C.
I2C Broadcast Mode
I2C Communication with Remote-Side Devices

The serializer supports I2C communication with a peripheral on the remote side of the communication link using
SCL clock stretching. While multiple masters can reside
on either side of the communication link, arbitration is
not provided. The connected masters need to support
SCL clock stretching and provide contention detection.
The remote side I2C bit-rate range must be set according to the local-side I2C bit rate. Supported remote-side
bit rates can be found in Table 4. Set the I2CMSTBT
(register 0x0D) to set the remote I2C bit rate. If using a
The serializer supports broadcast commands to control

multiple peripheral devices. Select an unused device
address to use as a broadcast device address. Program
the remote-side GMSL device to translate the broadcast
device address (source address stored in registers 0x09,
0x0B) to the peripheral device address (destination
address stored in registers 0x0A, 0x0C). Any commands
sent to the broadcast address are sent to all designated
peripherals, while commands sent to a peripherals unique
device address are sent to that particular device only.
0 = WRITE
ADDRESS = 0x80
A
S = START BIT
P = STOP BIT
A = ACK
N = NACK
D_ = DATA BIT
1 = READ
ADDRESS = 0x81
REPEATED START
REGISTER 0x00 READ DATA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 30. Format for I2C Read
Table 4. I2C Bit-Rate Ranges

LOCAL BIT RATE
REMOTE BIT-RATE RANGE
f > 50kbps
Up to 1Mbps
Any
20kbps > f > 50kbps
Up to 400kbps
Up to 110
f < 20kbps
Up to 10kbps
000
Maxim Integrated
I2CMSTBT SETTING
30
MAX9271
STP Cable Drive
GPO/GPI Control
GPO on the serializer follows GPI transitions on the deserializer. This GPO/GPI function can be used to transmit
signals such as frame sync in a surround-view camera
system. The GPI-to-GPO delay is 0.35ms (max). Keep
the time between GPI transitions to a minimum 0.35ms.
This includes transitions from the other deserializer in the
coax-mode splitter. Bit D4 of register 0x0E in the deserializer stores the GPI input state. GPO is low after power-up.
The FC can set GPO by writing to the SET_GPO register
bit. Do not send a logic-low value on the deserializer RX/
SDA input (UART mode) longer than 100Fs in either base
or bypass mode to ensure proper GPO/GPI functionality.
Pre/Deemphasis Driver
The serial line driver employs current-mode logic (CML)

signaling. The driver is differential when programmed
for twisted-pair (TP). When programmed for coax, one
side of the CML driver is used. The line driver has programmable pre/deemphasis that modifies the output to
compensate for cable length. There are 13 preemphasis
settings, as shown in Table 5. Negative preemphasis
levels are deemphasis levels in which the preemphasized swing level is the same as normal swing, but the
no-transition data (e.g., a 1 followed by a 1) is deemphasized. Program the preemphasis levels through register
0x06 D[3:0] of the serializer. This preemphasis function
compensates the high-frequency loss of the cable and

enables reliable transmission over longer link distances.
Current drive for both TP and coax modes is programmable. CMLLVL bits (0x06, D[7:4]) program drive current
in TP and coax modes for a single-ended voltage swing
from 100mV to 500mV.
Spread Spectrum
To reduce the EMI generated by the transitions on the

serial link, the serializer output is programmable for
spread spectrum. If the deserializer driven by the serializer has programmable spread spectrum, do not enable
spread for both at the same time or their interaction will
cancel benefits. The deserializer tracks the serializers
spread and passes the spread to the deserializer output.
The programmable spread-spectrum amplitudes are
Q0.5%, Q1%, Q1.5%, Q2%, Q3%, and Q4% (Table 6).
Some spread-spectrum amplitudes can only be used at
lower PCLKIN frequencies (Table 7). There is no PCLKIN
frequency limit for the Q0.5% spread rate.
When the spread spectrum is turned on or off, the serial
link stops for several microseconds and then restarts in
order for the deserializer to lose and relock to the new
serial-data stream.
The serializer includes a sawtooth divider to control the
spread-modulation rate. Autodetection of the PCLKIN
Table 5. TP/Coax Drive Current (CMLLVL = 1000)

SINGLE-ENDED VOLTAGE SWING
PREEMPHASIS
LEVEL (dB)*
PREEMP SETTING
(0x06, D[3:0])
ICML
(mA)
IPRE
(mA)
MAX (mV)
MIN (mV)
-6.0
0100
12
400
200
-4.1
0011
13
400
250
-2.5
0010
14
400
300
-1.2
0001
15
400
350
0
(power-on default)
0000
16
400
400
1.1
1000
16
425
375
2.2
1001
16
450
350
3.3
1010
16
475
325
4.4
1011
16
500
300
6.0
1100
15
500
250
8.0
1101
14
500
200
10.5
1110
13
500
150
14.0
1111
12
500
100
*Negative preemphasis levels denote deemphasis.

Maxim Integrated
31
MAX9271
STP Cable Drive
Table 6. Serial Output Spread
SS
SPREAD (%)
000
No spread spectrum. Power-up default.
001
0.5% spread spectrum.
010
011
2% spread spectrum.
100
No spread spectrum.
101
1% spread spectrum.
110
3% spread spectrum.
111
4% spread spectrum.
Table 7. Spread Limitations

BWS = 0 MODE, PCLKIN
FREQUENCY (MHz)
BWS = 1 MODE, PCLKIN

FREQUENCY (MHz)
< 33.3
(DBL = 0)
< 25
(DBL = 0)
< 66.6
(DBL = 1)
< 50
(DBL = 1)
33.3 to 50
(DBL = 0)
25 to 37.5
(DBL = 0)
66.6 to 100
(DBL = 1)
50 to 75
(DBL = 1)
operation range guarantees a spread-spectrum modulation frequency within 20kHz to 40kHz. Additionally,
manual configuration of the sawtooth divider (SDIV: 0x03,
D[5:0]) allows the user to set a modulation frequency
according to the PCLKIN frequency. When ranges are
manually selected, program the SDIV value for a fixed
modulation frequency around 20kHz.
Manual Programming of the

Spread-Spectrum Divider
The modulation rate relates to the PCLKIN frequency as

follows:
f
fM= (1 + DRS) PCLKIN
MOD x SDIV
where:
fM = Modulation frequency
DRS = DRS value (0 or 1)
fPCLKIN = PCLKIN frequency
MOD = Modulation coefficient given in Table 8
SDIV = 6-bit SDIV setting, manually programmed by the FC
To program the SDIV setting, first look up the modulation coefficient according to the desired bus-width and
Maxim Integrated
SERIAL LINK BIT

RATE (Mbps)
AVAILABLE
SPREAD RATES
< 1000
All rates available
R 1000
1.5%, 1.0%, 0.5%
spread-spectrum settings. Solve the above equation for

SDIV using the desired pixel clock and modulation frequencies. If the calculated SDIV value is larger than the
maximum allowed SDIV value in Table 8, set SDIV to the
maximum value.
Additional Error Detection and Correction
In default mode (additional error detection and correction disabled), data encoding/decoding is the same as in
previous GMSL serializers/deserializers (parity only). At
the serializer, the parallel input word is scrambled and a
parity bit is added. The scrambled word is divided into
3 or 4 bytes (depending on the BWS setting), 8b/10b
encoded, and then transmitted serially. At the deserializer, the same operations are performed in reverse order.
The parity bit is used by the deserializer to find the word
boundary and for error detection. Errors are counted in
an error counter register and an error pin indicates errors.
The serializer can use one of two additional errordetection/correction methods (selectable by register
setting):
1) 6-bit cyclic redundancy check
2) 6-bit hamming code with 16-word interleaving
32
MAX9271
STP Cable Drive
Table 8. Modulation Coefficients and
Maximum SDIV Settings
BWS
SPREADSPECTRUM
SETTING (%)
MODULATION
COEFFICIENT
(dec)
SDIV UPPER
LIMIT (dec)
104
40
0.5
104
63
152
27
1.5
152
54
204
15
204
30
80
52
0.5
80
63
112
37
1.5
112
63
152
21
152
42
Cyclic Redundancy Check (CRC)

When CRC is enabled, the serializer adds 6 bits of CRC
to the input data. This reduces the available bits in the
input data word by 6, compared to the non-CRC case
(see Table 2 for details). For example, 16 bits are available for input data instead of 22 bits when BWS = 0, and
24 bits instead of 30 bits when BWS = 1.
The CRC generator polynomial is x6 + x + 1 (as used in
the ITU-T G704 telecommunication standard).
The parity bit is still added when CRC is enabled,
because it is used for word-boundary detection. When
CRC is enabled, each data word is scrambled and then
the 6-bit CRC and 1-bit parity are added before the
8b/10b encoding.
At the deserializer, the CRC code is recalculated. If the
recalculated CRC code does not match the received
CRC code, an error is flagged. This CRC error is reported
to the error counter.
Hamming Code
Hamming code is a simple and effective error-correction
code to detect and/or correct errors. The MAX9271 serializer (when used with the MAX9272 GMSL deserializer)
uses a single-error correction, double-error detection per
pixel hamming-code scheme.
Maxim Integrated
The serializer uses data interleaving for burst error tolerance. Burst errors up to 11 consecutive bits on the serial
link are corrected, and burst errors up to 31 consecutive
bits are detected.
Hamming code adds overhead similar to CRC. See Table 2
for details regarding the available input word size.
HS/VS Encoding and/or Tracking
HS/VS encoding by a GMSL serializer allows horizontal

and vertical synchronization signals to be transmitted
while conserving pixel data bandwidth. With HS/VS
encoding enabled, 10-bit pixel data with a clock up to
100MHz can be transmitted using one video pixel of
data per HS/VS transition, versus 8-bit data with a clock
up to 100MHz without HS/VS encoding. The deserializer
performs HS/VS decoding, tracks the period of the HS/
VS signals, and uses voting to filter HS/VS bit errors.
When using HS/VS encoding, use a minimum HS/VS lowpulse duration of two PCLKIN cycles when DBL = 0 on
the MAX9271/MAX9273. When DBL = 1, use a minimum
low-pulse duration of five PCLKIN cycles and a minimum
high-pulse duration of two PCLKIN cycles. When using
hamming code with HS/VS encoding, do not send more
than two transitions every 16 PCLKIN cycles.
When the serializer uses double-input mode (DBL = 1)
the active duration, plus the blanking duration of HS or
VS signals, should be an even number of PCLKIN cycles.
If HS/VS tracking is used without HS/VS encoding, use
DIN0 for HSYNC and DIN1 for VSYNC. In this case, if
DBL values on the serializer and the deserializer are different, set the deserializers UNEQDBL register bit to 1.
If the serializer and deserializer have unequal DBL settings and HVEN = 0, then HS/VS inversion should only
be used on the side that has DBL = 1. HS/VS encoding
sends packets when HSYNC or VSYNC is low, use H/V
inversion register bits if input HSYNC and VSYNC signals
use an active-low convention to send data packets during the inactive pixel clock periods.
Serial Output
The driver output is programmable for two types of cable:

100I twisted pair and 50I coax (contact the factory for
serializers with 75I cable drive).
33
MAX9271
STP Cable Drive
Coax-Mode Splitter
In coax mode, OUT+ and OUT- are active. This enables

use as a 1:2 splitter (Figure 31). In coax mode, connect
OUT+ to IN+ of the deserializer. Connect OUT- to IN- of
the second deserializer. Control-channel data is broadcast from the serializer to both deserializers and their
attached peripherals. Assign a unique device address to
send control data to one deserializer. Leave all unused
IN_ pins unconnected, or connect them to ground
through 50I and a capacitor for increased power-supply
rejection. If OUT- is not used, connect OUT- to AVDD
through a 50I resistor (Figure 32). When there are FCs
at the serializer, and at each deserializer, only one FC
can communicate at a time. Disable one splitter controlchannel link to prevent contention. Use the DIS_REV_P or
DIS_REV_N register bits to disable a control-channel link.
GMSL
DESERIALIZER
MAX9271
OUT+
IN+
OUT-
IN-
Configuration Inputs (CONF1, CONF0)
CONF1 and CONF0 determine the power-up values

of the serial output type, the input data latch, and the
control-channel interface type (Table 9). These functions
can be changed after power-up by writing to the appropriate register bits.
Sleep Mode
The serializer includes a sleep mode to reduce power

consumption. The device enters or exits sleep mode by
a command from a local FC or a remote FC using the
control channel. Set the SLEEP bit to 1 to initiate sleep
mode. The serializer sleeps immediately after setting
its SLEEP = 1. The OUT+ and OUT- serial outputs each
have a wake-up receiver to accept wake-up commands
from the attached deserializers. On power-up, the OUT+
GMSL
DESERIALIZER
MAX9271
OUT+
OUT-
IN+
IN-
AVDD
GMSL
DESERIALIZER
50I
IN+
IN-
Figure 31. 2:1 Coax-Mode Splitter Connection Diagram
Figure 32. Coax-Mode Connection Diagram
Table 9. Configuration Input Map

CONF1
CONF0
CXTP
(OUT+/OUT- OUTPUT TYPE)
ES
(PCLKIN LATCH EDGE)
I2CSEL
(CONTROL-CHANNEL TYPE)
Low
Low
1 (coax)
1 (falling)
1 (I2C-to-I2C)
Low
Mid
1 (coax)
1 (falling)
0 (UART-to-I2C/UART)
Low
High
1 (coax)
0 (rising)
1 (I2C-to-I2C)
Mid
Low
1 (coax)
0 (rising)
Mid
Mid
0 (STP)
1 (falling)
1 (I2C-to-I2C)
Mid
High
0 (STP)
1 (falling)
High
Low
0 (STP)
0 (rising)
1 (I2C-to-I2C)
High
Mid
0 (STP)
0 (rising)
High
High
Do not use
Do not use
Do not use
Maxim Integrated
34
MAX9271
STP Cable Drive
wake-up receiver is enabled and the OUT- wake-up
receiver is disabled. Disable the wake-up receivers
(through ENWAKEP or ENWAKEN) if the devices are
disconnected or wake-up is not used in order to reduce
sleep mode current. If both wake-up receivers are disabled, the device can only be woken up from the local
control channel. To wake up the device, send an arbitrary
control-channel command to the serializer. Wait 5ms for
the chip to power up and then write 0 to the SLEEP register bit to make the wake-up permanent.
Configuration Link
The control channel can operate in a low-speed mode

called configuration link in the absence of a clock input.
This allows a microprocessor to program configuration
registers before starting the video link. An internal oscillator provides the clock for the configuration link. Set
CLINKEN = 1 on the serializer to enable the configuration
link. The configuration link is active until the video link is
enabled. The video link overrides the configuration link
and attempts to lock when SEREN = 1.
Power-Down Mode
The serializer has a power-down mode that further

reduces power consumption compared to sleep mode.
Set PWDN low to enter power-down mode. In powerdown mode, the serial outputs are in high impedance.
Entering power-down resets the devices registers.
Upon exiting power-down, the state of the GPIO1/BWS,
MS/HVEN, LCCEN, CONF0, CONF1, RX/SDA/EDC, and
TX/SCL/DBL pins are latched.
Link Startup Procedure

Table 10 lists the startup procedure for video-display
applications. Table 11 lists the startup procedure for
image-sensing applications. The control channel is available after the video link or the configuration link is established. If the deserializer powers up after the serializer,
the control channel becomes unavailable until 2ms after
power-up.
Table 10. Startup Procedure for Video-Display Applications

NO.
SERIALIZER
DESERIALIZER
FC connected to serializer.
Sets all configuration inputs. If any

configuration inputs are available
on one end of the link but not on
the other, always connects that
configuration input low.
Powers up.
Powers up and loads default settings.
Enables configuration link by

setting CLINKEN = 1 (if not enabled
automatically) and gets an acknowledge.
Waits for link to be established (~3ms).
Establishes configuration link.
Locks to configuration link signal.
Writes one link configuration bit (DRS,

BWS, or EDC) in the deserializer and
gets an acknowledge.
Configuration changed from default

settings (loss-of-lock occurs if BWS or
EDC changes).
Writes corresponding serializer

link configuration bit and gets an
acknowledge.

settings.
Relocks to configuration link signal.
Waits for link to be established (~3ms)

and then repeats steps 3 through 4 until
all serial link bits are configured.
Writes remaining configuration bits in

the serializer/deserializer and gets an
acknowledge.

settings.

settings.
Enables video link by setting SEREN = 1

and gets an acknowledge. Waits for link
to be established (~3ms).
Begins serializing data.
Locks to serial link signal and begins

deserializing data.
Maxim Integrated

35
MAX9271
STP Cable Drive
Table 11. Startup Procedure for Image-Sensing Applications
NO.
SERIALIZER
DESERIALIZER
FC connected to deserializer.


Powers up.

Establishes serial link.

Locks to serial link signal.
Writes deserializer configuration bits

and gets an acknowledge.

settings (loss-of-lock occurs if BWS or
EDC changes).
Writes serializer configuration bits.

Does not get an acknowledge (or
gets a dummy acknowledge) if lossof-lock occurred.

settings.
Relocks to serial link signal.
Enables video link by setting SEREN

= 1 (if not enabled automatically).
Cannot get an acknowledge (or gets
a dummy acknowledge) if loss-oflock occurred. Waits for link to be
established (~3ms).
Begins serializing data.
Locks to serial link signal and begins

deserializing data.
CLINKEN = 0 OR
SEREN = 1
SLEEP
CLINKEN = 0 OR
SEREN = 1
SLEEP = 1
FOR > 8ms
WAKE-UP
WAKE-UP SIGNAL
SLEEP = 0,
SEREN = 1
SLEEP = 1
SLEEP = 0,
SEREN = 0
POWER-ON
IDLE
SEREN = 1,
PCLKIN RUNNING
CLINKEN = 1
PWDN = LOW OR
POWER-OFF
POWER-DOWN
OR
POWER-OFF
PWDN = HIGH,
POWER-ON
VIDEO
LINK LOCKING
CONFIG LINK
UNLOCKED
CONFIG LINK
LOCKED
CONFIG LINK
OPERATING
PROGRAM
REGISTERS
SEREN = 0 OR
NO PCLKIN
SEREN = 0 OR
NO PCLKIN
ALL STATES
CONFIG
LINK STARTED
VIDEO LINK
LOCKED
PRBSEN = 0
VIDEO LINK
OPERATING
PRBSEN = 1
VIDEO LINK
PRBS TEST
VIDEO LINK
UNLOCKED
Figure 33. State Diagram, All Applications
Maxim Integrated
36
MAX9271
STP Cable Drive
Applications Information
PRBS Test
The serializer includes a PRBS pattern generator that

works with bit-error verification in the deserializer. To run
the PRBS test, set PRBSEN = 1 (0x04, D5) in the deserializer and then in the serializer. To exit the PRBS test, set
PRBSEN = 0 (0x04, D5) in the serializer.
Error Generator
The serializer contains an error generator that enables

repeatable testing of the error-detection/correction features of the GMSL link. Register 0x11 stores the configuration bits for the error generator. A FC sets the errorgeneration rate, type of errors, and the total number of
errors. The error generator is off by default.
Dual C Control
Usually systems have one FC to run the control channel,

located on the serializer side for video-display applications or on the deserializer side for image-sensing
applications. However, a FC can reside on each side
simultaneously and trade off running the control channel.
In this case, each FC can communicate with the serializer
and deserializer and any peripheral devices.
Contention occurs if both FC s attempt to use the control
channel at the same time. It is up to the user to prevent
this contention by implementing a higher-level protocol.
In addition, the control channel does not provide arbitration between I2C masters on both sides of the link. An
acknowledge frame is not generated when communication fails due to contention. If communication across the
serial link is not required, the FC s can disable the forward and reverse control channel using the FWDCCEN
and REVCCEN bits (0x04, D[1:0]) in the serializer/deserializer. Communication across the serial link is stopped
and contention between FC s cannot occur.
As an example of dual FC use in an image-sensing application, the serializer can be in sleep mode, waiting for
wake-up by the FC on the deserializer side. After wakeup, the serializer-side FC assumes master control of the
serializers registers.
Jitter-Filtering PLL
In some applications, the clock input (PCLKIN) includes

noise, which reduces link reliability. The clock input has a
programmable narrowband jitter-filter PLL that attenuates
frequencies higher than 100kHz (typ). Enable the jitter
filter by setting ENJITFILT = 1 (0x05, D6).
Maxim Integrated
PCLKIN Spread Tracking
The serializer can operate with a spread PCLKIN

signal. When using a spread PCLKIN signal, disable the
jitter filter by setting ENJITFILT = 0 (0x05, D6). Do not
exceed the spread limitations listed in Table 7 and keep
modulation less than 40kHz. In addition, turn off spread
spectrum in the serializer/deserializer. The serializer/
deserializer track the spread on PCLKIN.
Changing the Clock Frequency
It is recommended that the serial link be enabled after

the video clock (fPCLKIN) and the control-channel clock
(fUART/fI2C) are stable. When changing clock frequency,
stop the video clock for 5Fs, apply the clock at the new
frequency, then restart the serial link or toggle SEREN.
On-the-fly changes in clock frequency are possible if
the new frequency is immediately stable and without
glitches. The reverse control channel remains unavailable for 350Fs after serial link start or stop. When using
the UART interface, limit on-the-fly changes in fUART to
factors of less than 3.5 at a time to ensure that the device
recognizes the UART sync pattern. For example, when
lowering the UART frequency from 1Mbps to 100kbps,
first send data at 333kbps, then at 100kbps for reduction
ratios of 3 and 3.333, respectively.
Providing a Frame Sync

(Camera Applications)
The GPI and GPO provide a simple solution for camera

applications that require a frame sync signal from the
ECU (e.g., surround-view systems). Connect the ECU
frame sync signal to the GPI input and connect the GPO
output to the camera frame sync input. GPI/GPO have
a typical delay of 275Fs. Skew between multiple GPI/
GPO channels is 115Fs (max). If a lower skew signal is
required, connect the cameras frame sync input to one
of the serializers GPIOs and use an I2C broadcast write
command to change the GPIO output state. This has a
maximum skew of 1.5Fs, independent from the used I2C
bit rate.
Software Programming of the

Device Addresses
The serializer and deserializer have programmable device

addresses. This allows multiple GMSL devices, along with
I2C peripherals, to coexist on the same control channel.
The serializer device address is in register 0x00 of each
device, while the deserializer device address is in register
0x01 of each device. To change a device address, first
37
MAX9271
STP Cable Drive
write to the device whose address changes (register 0x00
of the serializer for serializer device address change, or
register 0x01 of the deserializer for deserializer device
address change). Then write the same address into the
corresponding register on the other device (register 0x00
of the deserializer for serializer device address change,
or register 0x01 of the serializer for deserializer device
address change).
Three-Level Configuration Inputs
CONF1 and CONF0 are three-level inputs that control

the serial interface configuration and power-up defaults.
Connect CONF1or CONF0 through a pullup resistor to
IOVDD to set a high level, a pulldown resistor to GND to
set a low level, or IOVDD/2 or open to set a midlevel. For
digital control, use three-state logic to drive the threelevel logic inputs.
Configuration Blocking
The serializer can block changes to registers. Set

CFGBLOCK to make all registers read only. Once set, the
registers remain blocked until the supplies are removed
or until PWDN is low.
Compatibility with Other GMSL Devices
The MAX9271 serializer is designed to pair with the

MAX9272 deserializer, but interoperates with any GMSL
deserializer. See Table 12 for operating limitations.
GPIOs
The serializer has five open-drain GPIOs available when

not used as data or configuration inputs. Setting the
GPIO enable bits (register 0x0E) to 1 enables the GPIOs
and internally connects the respective data or configuration input low. Setting the GPIO output bits to 0 pulls the
output low, while setting the bits to 1 leaves the output
undriven, and pulled high through internal/external pullup
resistors. The GPIO input buffers are enabled when the
GPIO is enabled. The input states are stored in register
0x10 (read only). Set GPIO_OUT to 1 when using a GPIO_
as an input.
Local Control-Channel Enable (LCCEN)
The serializer provides inputs for limited configuration of

the device when a FC is not connected. Connect LCCEN
= low upon power-up to disable the local control channel, and enable the double-function configuration inputs
(Table 13). All input configuration states are latched at
power-up.
Table 12. MAX9271 Feature Compatibility

MAX9271 FEATURE
GMSL Deserializer
HSYNC/VSYNC encoding
If feature not supported in the deserializer, must be turned off in the serializer.
Hamming-code error correction
I2C-to-I2C
If feature not supported in the deserializer, must use UART-to-I2C or UART-to-UART.
CRC error detection
Double input
If feature not supported in the deserializer, data is output as a single word at half the
input frequency.
Coax
If feature not supported in the deserializer, Must connect unused serial input through 200nF
and 50I in series to AVDD, and set the reverse control-channel amplitude to 100mV.
I2S encoding
If supported in the deserializer, disable I2S in the deserializer.
Table 13. Double-Function Configuration

LCCEN
GPIO1/BWS
FUNCTION
MS/HVEN FUNCTION
RX/SDA/EDC FUNCTION
TX/SCL/DBL FUNCTION
High
Functions as GPIO
MS input
(low = base mode
high = bypass mode)
UART/I2C input/output
UART/I2C input/output
Low
BWS input
(low = 24-bit mode,
high = 32-bit mode)
HVEN input
(low = HS/VS encoding
disabled, high = HS/VS
encoding enabled)
EDC input
(low = error detection/correction
disabled, high = error detection/
correction enabled
DBL input
(low = single input,
high = double input)
Maxim Integrated
38
MAX9271
STP Cable Drive
Internal Input Pulldowns
The control and configuration inputs (except three-level

inputs) include a pulldown resistor to GND. External pulldown resistors are not needed.
Choosing I2C/UART Pullup Resistors
I2C
The
and UART open-drain lines require a pullup
resistor to provide a logic-high level. There are tradeoffs
between power dissipation and speed, and a compromise may be required when choosing pullup resistor
values. Every device connected to the bus introduces
some capacitance even when the device is not in operation. I2C specifies 300ns rise times (30% to 70%) for fast
mode, which is defined for data rates up to 400kbps (see
the I2C specifications in the AC Electrical Characteristics
table for details). To meet the fast-mode rise-time requirement, choose the pullup resistors so that rise time tR =
0.85 x RPULLUP x CBUS < 300ns. The waveforms are not
recognized if the transition time becomes too slow. The
serializer supports I2C/UART rates up to 1Mbps (UARTto-I2C mode) and 400kbps (I2C-to-I2C mode).
AC-Coupling
AC-coupling isolates the receiver from DC voltages up to

the voltage rating of the capacitor. Capacitors at the serializer output and at the deserializer input are needed for
proper link operation and to provide protection if either
end of the cable is shorted to a battery. AC-coupling
blocks low-frequency ground shifts and low-frequency
common-mode noise.
Table 14. Typical Power-Supply Currents

(Using Worst-Case Input Pattern)
PCLK
(MHz)
AVDD
(mA)
DVDD
(mA)
IOVDD
(mA)
25
50
36.8
9.0
0.32
42.1
13.7
0.34
Selection of AC-Coupling Capacitors
Voltage droop and the digital sum variation (DSV) of transmitted symbols cause signal transitions to start from different voltage levels. Because the transition time is fixed,
starting the signal transition from different voltage levels
causes timing jitter. The time constant for an AC-coupled
link needs to be chosen to reduce droop and jitter to an
acceptable level. The RC network for an AC-coupled link
consists of the CML/coax receiver termination resistor
(RTR), the CML/coax driver termination resistor (RTD),
and the series AC-coupling capacitors (C). The RC time
constant for four equal-value series capacitors is (C x
(RTD + RTR))/4. RTD and RTR are required to match the
transmission line impedance (usually 100I differential,
50I single-ended). This leaves the capacitor selection
to change the system time constant. Use 0.2FF or larger
high-frequency surface-mount ceramic capacitors, with
sufficient voltage rating to withstand a short to battery, to
pass the lower speed reverse control-channel signal. Use
capacitors with a case size less than 3.2mm x 1.6mm to
have lower parasitic effects to the high-speed signal.
Power-Supply Circuits and Bypassing
The serializer uses an AVDD and DVDD of 1.7V to 1.9V.

All inputs and outputs, except for the serial output, derive
power from an IOVDD of 1.7V to 3.6V that scales with
IOVDD. Proper voltage-supply bypassing is essential for
high-frequency circuit stability.
Power-Supply Table
Power-supply currents shown in the Electrical

Characteristics table are the sum of the currents from
AVDD, DVDD, and IOVDD. Typical currents from the
individual power supplies are shown in Table 14.
Cables and Connectors
Interconnect for CML typically has a differential impedance of 100I. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities. Coax cables typically have a characteristic impedance of 50I contact the factory for 75I operation). Table 15 lists the suggested cables and connectors
used in the GMSL link.
Table 15. Suggested Connectors and Cables for GMSL

SUPPLIER
Rosenberger
CONNECTOR
CABLE
TYPE
59S2AX-400A5-Y
RG174
Coax
JAE
MX38-FF
A-BW-Lxxxxx
STP
Nissei
GT11L-2S
F-2WME AWG28
STP
D4S10A-40ML5-Z
Dacar 538
STP
Rosenberger
Maxim Integrated
39
MAX9271
STP Cable Drive
Board Layout
Separate the LVCMOS logic signals and CML/coax highspeed signals to prevent crosstalk. Use a four-layer PCB
with separate layers for power, ground, CML/coax, and
LVCMOS logic signals. Layout PCB traces close to each
other for a 100I differential characteristic impedance.
The trace dimensions depend on the type of trace used
(microstrip or stripline). Note that two 50I PCB traces
1MI
HIGHVOLTAGE
DC
SOURCE
CHARGE-CURRENTLIMIT RESISTOR
CS
100pF
Route the PCB traces for differential CML in parallel to

maintain the differential characteristic impedance. Avoid
vias. Keep PCB traces that make up a differential pair
equal in length to avoid skew within the differential pair.
ESD Protection
RD
1.5kI
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
do not have 100I differential impedance when brought

close togetherthe impedance goes down when the
traces are brought closer. Use a 50I trace for the singleended output when driving coax.
DEVICE
UNDER
TEST
Figure 34. Human Body Model ESD Test Circuit
ESD tolerance is rated for Human Body Model, IEC

61000-4-2, and ISO 10605. The ISO 10605 and IEC
61000-4-2 standards specify ESD tolerance for electronic
systems. The serial outputs are rated for ISO 10605 ESD
protection and IEC 61000-4-2 ESD protection. All pins
are tested for the Human Body Model. The Human Body
Model discharge components are CS = 100pF and RD =
1.5kI (Figure 34). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330I (Figure 35). The
ISO 10605 discharge components are CS = 330pF and
RD = 2kI (Figure 36).
RD
330I
HIGHVOLTAGE
DC
SOURCE
CS
150pF
RD
2kI
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 35. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Maxim Integrated
HIGHVOLTAGE
DC
SOURCE
CS
330pF
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 36. ISO 10605 Contact Discharge ESD Test Circuit
40
MAX9271
STP Cable Drive
Table 16. Register Table (see Table 1)
REGISTER
ADDRESS
0x00
0x01
BITS
NAME
VALUE
D[7:1]
SERID
XXXXXXX
0x02
Registers 0x00 to 0x1F are read only.
D[7:1]
DESID
XXXXXXX
D0
D4
D[3:2]
D[1:0]
D[7:6]
PRNG
SRNG
D[5:0]
SDIV
Deserializer device address.

Reserved.
000
No spread spectrum.
001
010
011
2% spread spectrum.
100
No spread spectrum.
101
1% spread spectrum.
110
3% spread spectrum.
111
4% spread spectrum.
Reserved.
00
12.5MHz to 25MHz pixel clock.
01
25MHz to 50MHz pixel clock.
10
Automatically detect the pixel clock range.
11
Automatically detect the pixel clock range.
00
0.5 to 1Gbps serial-bit rate.
01
1 to 2Gps serial-bit rate.
10
Automatically detect serial-bit rate.
11
Automatically detect serial-bit rate.
00
Calibrate spread-modulation rate only once

after locking.
01
Calibrate spread-modulation rate every 2ms

after locking.
10

after locking.
11

after locking.
AUTOFM
0x03
Maxim Integrated
Normal operation.
CFGBLOCK
SS
Serializer device address.
D0
D[7:5]
FUNCTION
000000
Autocalibrate sawtooth divider.
XXXXXX
Manual SDIV setting. See the Manual Programming

of the Spread-Spectrum Divider section.
DEFAULT
VALUE
1000000
0
1001000
0
000
11
11
00
000000
41
MAX9271
STP Cable Drive
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS
D7
0x04
NAME
CLINKEN
D5
PRBSEN
D4
SLEEP
INTTYPE
Disable serial link. Reverse control-channel

communication remains unavailable for 350Fs after
the serializer starts/stops the serial link.
Enable serial link. Reverse control-channel

communication remains unavailable for 350Fs after
the serializer starts/stops the serial link.
Disable configuration link.
Enable configuration link.
Disable PRBS test.
Enable PRBS test.
Normal mode.
Activate sleep mode.
00
Local control channel uses I2C when I2CSEL = 0.
01
Local control channel uses UART when I2CSEL = 0.
10, 11
D1
D0
D7
D6
0x05
Maxim Integrated
Enable reverse control channel from deserializer

(receiving).
Disable forward control channel to deserializer

(sending).
Enable forward control channel to deserializer

(sending).
I2C conversion sends the register address when

converting UART to I2C.
Disable sending of I2C register address when

converting UART to I2C (command-byte-only mode).
Jitter filter disabled.
Jitter filter active.
00
Continuous PRBS length.
01
9.83Mbit PRBS length.
10
11
00
Reserved.
I2CMETHOD
D[5:4]
PRBSLEN
D[3:2]
D1
ENWAKEN
D0
Disable reverse control channel from deserializer

(receiving).
FWDCCEN
ENWAKEP
DEFAULT
VALUE
0
0
0
01
Local control channel disabled.
0
REVCCEN
ENJITFILT
FUNCTION
0
SEREN
D6
D[3:2]
VALUE
Disable wake-up receiver.
Enable OUT- wake-up receiver during

sleep mode.
Disable wake-up receiver.
Enable OUT- wake-up receiver during

sleep mode.
00
00
0
42
MAX9271
STP Cable Drive
REGISTER
ADDRESS
BITS
D[7:4]
NAME
CMLLVL
0x06
D[3:0]
Maxim Integrated
PREEMP
VALUE
FUNCTION
0000
Do not use.
0001
Do not use.
0010
100mV output level.
0011
150mV output level.
0100
200mV output level.
0101
250mV output level.
0110
300mV output level.
0111
350mV output level.
1000
400mV output level. Power-up default when

twisted-pair output is selected (Table 9).
1001
450mV output level.
1010
500mV output level. Power-up default when coax

output is selected (Table 9).
1011
Do not use.
1100
Do not use.
1101
Do not use.
1110
Do not use.
1111
Do not use.
0000
Preemphasis off.
0001
-1.2dB preemphasis.
0010
-2.5dB preemphasis.
0011
-4.1dB preemphasis.
0100
-6.0dB preemphasis.
0101
Do not use.
0110
Do not use.
0111
Do not use.
1000
1.1dB preemphasis.
1001
2.2dB preemphasis.
1010
3.3dB preemphasis.
1011
4.4dB preemphasis.
1100
6.0dB preemphasis.
1101
8.0dB preemphasis.
1110
10.5dB preemphasis.
1111
14.0dB preemphasis.
DEFAULT
VALUE
1000, 1010
0000
43
MAX9271
STP Cable Drive
REGISTER
ADDRESS
BITS
D7
D6
D5
D4
NAME
DRS
D2
D[1:0]
D7
Double-input mode. Power-up default when

LCCEN = low and TX/SCL/DBL = high.
High data-rate mode.
Low data-rate mode.
24-bit mode. Power-up default when

LCCEN = high or GPIO1/BWS = low.
32-bit mode. Power-up default when

LCCEN = low and GPIO1/BWS = high.
Input data latched on rising edge of PCLKIN.

Power-up default determined by CONF1 and
CONF0 (Table 9). Do not change this value while the
pixel clock is running.
Input data latched on falling edge of PCLKIN.

Power-up default determined by CONF1 and
CONF0 (Table 9). Do not change this value while the
pixel clock is running.
Reserved.
HS/VS encoding disabled. Power-up default when

LCCEN = high or MS/HVEN = low.
HS/VS encoding enabled. Power-up default when

LCCEN = low and MS/HVEN = high.
00
1-bit parity error detection (GMSL compatible).

Power-up default when LCCEN = high or
RX/SDA/EDC = low.
01
6-bit CRC error detection.
10
6-bit hamming code (single-bit error correct,

double-bit error detect) and 16 word interleaving.
Power-up default when LCCEN = low and
RX/SDA/EDC = high.
11
Do not use.
No VS or DIN0 inversion.
Invert VS when HVEN = 1.

Invert DIN0 when HVEN = 0.
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
No HS or DIN1 inversion.
Invert HS when HVEN = 1.

Invert DIN1 when HVEN = 0.
Do not use if DBL = 0 in the serializer and
DBL = 1 in the deserializer.
ES
HVEN
EDC
INVVS
0x08
Maxim Integrated
Single-input mode. Power-up default when

LCCEN = high or TX/SCL/DBL = low.
BWS
D6
INVHS
D[5:0]
FUNCTION
0
DBL
0x07
D3
VALUE
000000
Reserved.
DEFAULT
VALUE
0, 1
0, 1
0, 1
0
0, 1
00, 10
000000
44
MAX9271
STP Cable Drive
REGISTER
ADDRESS
0x09
0x0A
0x0B
0x0C
BITS
NAME
VALUE
D[7:1]
I2CSRCA
XXXXXXX
D0
D[7:1]
I2CDSTA
XXXXXXX
D0
D[7:1]
I2CSRCB
XXXXXXX
I2C address translator source A.

Reserved.
I2C address translator destination A.
Reserved.
I2C address translator source B.
D0
D[7:1]
I2CDSTB
XXXXXXX
D0
Reserved.
Acknowledge not generated when forward channel

is not available.
I2C-to-I2C slave generates local acknowledge when

forward channel is not available.
00
352ns/117ns I2C setup/hold time.
D7
D[6:5]
I2CLOCACK
I2CSLVSH
0x0D
D[4:2]
D[1:0]
Maxim Integrated
FUNCTION
I2CMSTBT
I2CSLVTO
Reserved.
I2C address translator destination B.
01
10
11
000
8.47kbps (typ) I2C-to-I2C master bit-rate setting.
001
010
011
105kbps (typ) I2C-to-I2C master bit-rate setting.
100
101
110
111
00
64Fs (typ) I2C-to-I2C slave remote timeout.
01
10
11
No I2C-to-I2C slave remote timeout.
DEFAULT
VALUE
0000000
0
0000000
0
0000000
0
0000000
0
01
101
10
45
MAX9271
STP Cable Drive
REGISTER
ADDRESS
0x0E
0x0F
0x10
Maxim Integrated
BITS
NAME
D7
DIS_REV_P
D6
DIS_REV_N
D5
GPIO5EN
D4
GPIO4EN
D3
GPIO3EN
D2
GPIO2EN
D1
GPIO1EN
D0
D[7:6]
D5
GPIO5OUT
D4
GPIO4OUT
D3
GPIO3OUT
D2
GPIO2OUT
D1
GPIO1OUT
D0
SETGPO
D[7:6]
D5
GPIO5IN
D4
GPIO4IN
D3
GPIO3IN
D2
GPIO2IN
D1
GPIO1IN
D0
GPO_L
VALUE
FUNCTION
OUT+ reverse channel receiver enabled.
OUT+ reverse channel receiver disabled.
OUT- reverse channel receiver enabled.
OUT- reverse channel receiver disabled.
Disable GPIO5.
Enable GPIO5.
Disable GPIO4.
Enable GPIO4.
Disable GPIO3.
Enable GPIO3.
Disable GPIO2.
Enable GPIO2.
Disable GPIO1.
Enable GPIO1.
0
11
0
1
0
1
0
1
0
1
0
1
0
1
00
0
1
0
1
0
1
0
1
0
1
0
1
Reserved.
Reserved.
Set GPIO5 low.
Set GPIO5 high.
Set GPIO4 low.
Set GPIO4 high.
Set GPIO3 low.
Set GPIO3 high.
Set GPIO2 low.
Set GPIO2 high.
Set GPIO1 low.
Set GPIO1 high.
Set GPO low.
Set GPO high.
Reserved.
GPIO5 is low
GPIO5 is high.
GPIO4 is low.
GPIO4 is high.
GPIO3 is low.
GPIO3 is high.
GPIO2 is low.
GPIO2 is high.
GPIO1 is low.
GPIO1 is high.
GPO is set low.
GPO is set high.
DEFAULT
VALUE
0
1
0
0
0
0
1
0
11
1
1
1
1
1
0
00
1
(read only)
1
(read only)
1
(read only)
1
(read only)
1
(read only)
0
(read only)
46
MAX9271
STP Cable Drive
REGISTER
ADDRESS
BITS
NAME
VALUE
FUNCTION
DEFAULT
VALUE
D[7:6]
ERRGRATE
D[5:4]
ERRGTYPE
D[3:2]
ERRGCNT
D1
ERRGPER
D0
ERRGEN
0x12
D[7:0]
00
01
10
11
00
01
10
11
00
01
10
11
0
1
0
1
01000000
0x13
D[7:0]
00100010
Reserved.
00100010
0x14
D[7:0]
XXXXXXXX
Reserved.
00000000
(read only)
D7
CXTP
D6
I2CSEL
D5
LCCEN
D[4:2]
0x11
0x15
Generate an error every 2560 bits.

Generate an error every 40,960 bits.
Generate an error every 655,360 bits.
Generate an error every 10,485,760 bits.
Generate single-bit errors.
Generate 2 (8b/10b) symbol errors.
Continuously generate errors.
16 generated errors.
Disable periodic error generation.
Enable periodic error generation.
Disable error generator.
Enable error generator.
Reserved.
01000000
CXTP is low.
CXTP is high.
Input is high.
Input is low.
Input is high.
Input is low.
000
Reserved.
Output disabled.
Output enabled.
Valid PCLKIN detected.
Valid PCLKIN not detected.
00
00
00
0
0
0
(read only)
0
(read only)
0
(read only)
000 (read only)
0
(read only)
D1
OUTPUTEN
D0
PCLKDET
0x16
D[7:0]
XXXXXXXX
Reserved.
00000000
(read only)
0x17
D[7:0]
XXXXXXXX
Reserved.
00000000
(read only)
0x1E
D[7:0]
ID
00001001
Device identifier (MAX9271 = 0x09).
00001001
(read only)
D[7:5]
000
Reserved.
000
(read only)
D4
CAPS
D[3:0]
REVISION
0x1F
Maxim Integrated
0
(read only)
Not HDCP capable.
HDCP capable.
0
(read only)
XXXX
Device revision.
(read only)
47
MAX9271
STP Cable Drive
Typical Application Circuit
CAMERA APPLICATION
PCLK
RGBHV
SHDN
CAMERA
PCLKOUT
PCLKIN
PCLK
DOUT0DOUT15
DIN0DIN15
RGBHV
GPO
CONF1
GPU
CONF0
MAX9271
MAX9272
RX/SDA/EDC
TX
TX/SCL/ES
RX
UART
TO PERIPHERALS
RX/SDA/EDC
TX/SCL/DBL
OUT+
OUT-
GPI
IN+
LOCK
IN-
CX/TP
LCCEN
ECU
NOTE: NOT ALL PULLUP/PULLDOWN RESISTORS ARE SHOWN. SEE PIN DESCRIPTION FOR DETAILS.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9271GTJ+
-40NC to +105NC
32 TQFN-EP*
MAX9271GTJ/V+**
-40NC to +105NC
32 TQFN-EP*
/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future productcontact factory for availability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
+, #, or - in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
32 TQFN-EP
T3255+5
21-0140
90-0013
Chip Information
PROCESS: CMOS
Maxim Integrated
48
MAX9271
STP Cable Drive
Revision History
REVISION
NUMBER
REVISION
DATE
6/12
Initial release
11/12
Added nonautomotive package to Ordering Information.
48
DESCRIPTION
PAGES
CHANGED
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
2012
Maxim Integrated
49
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

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EVALUATION KIT AVAILABLE

Benefits and Features

The MAX9271 compact serializer is designed to drive

S Ideal for Camera Applications

The parallel input is programmable for single or double

Ordering Information and Typical Application Circuit appear

S High-Speed Data Serialization for Megapixel

19-6385; Rev 1; 11/12

Continuous Power Dissipation (TA = +70NC)

*EP connected to PCB ground.

PACKAGE THERMAL CHARACTERISTICS (Note 1)

Junction-to-Case Thermal Resistance (qJC)...................1.7C/W

SINGLE-ENDED INPUTS (LCCEN, DIN_, PCLKIN, HS, VS, MS/HVEN, PWDN)

Low-Level Input Voltage

THREE-LEVEL LOGIC INPUTS (CONF0, CONF1)

Low-Level Input Voltage

Midlevel Input Current

SINGLE-ENDED OUTPUT (GPO)

Low-Level Output Voltage

Output Short-Circuit Current

VIOVDD = 3.0V to 3.6V

VIOVDD = 1.7V to 1.9V

OPEN-DRAIN INPUTS/OUTPUTS (RX/SDA/EDC, TX/SCL/DBL, GPIO_)

Low-Level Input Voltage

Low-Level Output Voltage

EDC, DBL, BWS

VIOVDD = 1.7V to 1.9V

VIOVDD = 3.0V to 3.6V

DIFFERENTIAL SERIAL OUTPUTS (OUT+, OUT-)

3.3dB deemphasis setting (Figure 2)

Output Short-Circuit Current

Output Termination Resistance

Preemphasis off (Figure 1)

Preemphasis off, high drive (Figure 3)

3.3dB preemphasis setting, high drive

3.3dB deemphasis setting, high drive

SINGLE-ENDED SERIAL OUTPUTS (OUT+, OUT-)

Single-Ended Output Voltage

Output Short-Circuit Current

Output Termination Resistance

VOUT+ or VOUT- = 1.9V

REVERSE CONTROL-CHANNEL RECEIVER OUTPUTS (OUT+, OUT-)

Low Switching Threshold

Sleep Mode Supply Current

Single wake-up receiver enabled

Power-Down Supply Current

All Other Pins (Note 5)

Human Body Model, RD = 1.5kI,

CLOCK INPUT (PCLKIN)

Clock Duty Cycle

BWS = 1, DRS = 0, 15-bit double input

BWS = 0, DRS = 0, 11-bit double input

tHIGH/tT or tLOW/tT (Figure 5, Note 6)

I2C/UART AND GPIO PORT TIMING

30% to 70%, CL = 10pF to 100pF,

Output Fall Time

70% to 30%, CL = 10pF to 100pF,

Input Setup Time

I2C only (Figure 6, Note 6)

Input Hold Time