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VOLUME 3, ISSUE 9(2), SEPTEMBER 2014

DESIGN OF AN OPTIMISED LOW POWER FULL ADDER

USING DOUBLE GATED MOSFET AT 45nm TECHNOLOGY

T Nithyoosha

M.Rajeswara Rao

P.G Student
VLSI, Department of E.C.E, SIETK
Tirupati

Assistant Professor
Department of E.C.E, SIETK
Tirupati

1. INTRODUCTION
In very large scale integration (VLSI) systems, full adder circuit is used
in arithmetic operations for addition, multipliers and Arithmetic Logic
Unit (ALU). It is a building block of the application of VLSI, digital
signal processing, image processing and microprocessors. Most of full
adder systems are considered performance of circuits, number of
transistor, speed of circuit, chip area, threshold loss and full swing
output and the most important is power consumption. In the future,
portable devices such as cell phone, laptop computer, tablet etc. need
low power and high speed full adders.
The power consumption for CMOS circuit is given by the following
equation:
Pavg = Pdynamic + Pleak + Pshort-circuit
=CLVddVFclk + IleakVdd +IscVdd

(1)

Lowering the supply voltage would significantly lower the power

consumption of the circuit. This basic concept of would be used to
improve the performance of adder circuit.
2. FULL ADDER
Full adder circuit is designed for addition binary logics. Sum signal
(SUM) and carry out signal (Cout) are the output of I-bit full adder. Both
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of them are generated by input A, B and CIN, following Boolean

equation as:
SUM = A B Cin

(2)

Cout = AB + A B Cin

(3)

Cin

Cout

Fig.1. Block Diagram of basic full adder circuit

2.1 DOUBLE GATE 14T FULL ADDER CIRCUIT
Double gate MOSFET will be constructed by connecting two transistors
in parallel as a way that their supply and drain are connected together.
Double gate MOSFET can be classified in two types, based on biasing of
gate. Once the front and back gate area unit connected along, initial
kind is achieved and it is referred as three terminal devices. This device
is used for direct replacement of single gate transistor. Second kind is
achieved by independent gate control.
In this section single bit full adder circuit is designed by using double
gate MOSFET for improve the performance of adder in terms of power
and leakage using 14 transistors.

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Fig.2. Schematic of 4T XOR

This cell is constructed by using the 4T XOR gate. In the 14T full adder
cell two 4T XOR gate are used. Fig3 shows the double gate 14T full adder
circuit .Here 4T XOR is used gate to increase circuit density using this
XOR gate, reduction in size of full adder is achieved and overall leakage
is also reduced. Output waveform of 14T full adder is shown in fig.4

Fig.3. Double gate 14T full adder

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Fig.4. Output waveform of double gate 14T full adder

2.2 DOUBLE GATE 10T FULL ADDER CIRUIT
In this section one bit full adder circuit is presented by using double gate
transistors for improve the performance of adder in terms of power and
leakage. Fig5 shows the double gate 10T full adder circuit. This cell is
made by using the 4T XOR gate. It is the essential component of full
adder cell and generates the essential addition operation of adder cell. It
behaves like a single half adder cell.
Here 4T XOR gate is used to increase circuit density. Fig.2 shows the
4T XOR gate. Using this XOR gate, reduction in size of full adder is
achieved and overall leakage is also reduced. The schematic of full adder
is shown in fig.5 and output waveform is shown in fig.6.10T double gate
full adder achieves 31.25% reduction in active power and 95% reduction
in leakage current as compared to 14T double gate full adder.

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Cout

Sum

C
Fig.5. Double gate 10T full adder

Fig.6. Output waveform of double gate 10T full adder

1. DOUBLE GATE MOSFET
The MOS transistor model from COMSOL as a template is used to model
the double gate MOSFET. Double gate transistors are developed to
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resolve short channel effect problems in actual MOSFET structures. So

that such architectures are directly related to the constant Reduction of
the feature size in microelectronic technology. At the present time, it
seems that double gate devices- going to non-planar transistor.
Architectures- could be a solution for sub-32nm Nodes. In addition, new
design flexibility is allowed when gates are not interconnected. However,
appropriate models must be developed. Threshold voltage (Vth) modeling
of double gate (DG) MOSFETs was performed, for the first time, by
considering barrier lowering in the short channel devices. As the gate
length of DG MOSFETs scales down, the overlapped charge-sharing
length (xh) in the channel which is related to the barrier lowering
becomes very important. A fitting parameter w was introduced
semiempirically with the fin body width and body doping concentration
for higher accuracy. The Vth model predicted well the Vth behavior with
fin body thickness, body doping concentration, and gate length.
Recently, bulk FinFETs have been considering very promising candidate
for next generation memory cell transistors to be applicable to dynamic
random access memory (DRAM) and flash memory. As the gate length of
bulk FinFETs scales down, barrier lowering occurs in spite of low drain
bias (VDS =0.05V) because the depleted charge-sharing length (xh) by
source and drain in short channel is overlapped. To apply the devices to
integrated circuits, it is strongly required to model threshold voltage
(Vth) considering the barrier lowering in short channel. However, the Vth
model has not been developed since the xh modeling in short channel
devices is very complicated with device geometry and doping
concentration. For Vth modeling of the devices, double-gate (DG) nature
is key point and needs to be understood well. In this paper, we propose
Vth model of DG MOSFETs based on the correction of xh considering
barrier lowering, and verify the Vth model by comparing with device
simulation in terms of gate length (Lg), fin width (Wfin) and body

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doping (Nb). Threshold voltages were extracted by using gm,max for a

given VDS of 0.05 V in this paper.
4. SIMULATION AND RESULT
A single bit full adder circuit based on double gate MOSFET technique is
proposed. It is used for measurement of leakage, power consumption and
delay of the proposed circuit at 45nm technology with different supply
voltage from 0.7v to 1.0v.
4.1. LEAKAGE CURRENT
Leakage current is the current that flows through the protective ground
conductor to ground. In the absence of a grounding connection, it is the
current that could flow from any conductive part or the surface of
non-conductive parts to ground if a conductive path was available (such
as a human body). There are always extraneous currents flowing in the
safety ground conductor. Tunnelling leakage can also occur across
junctions between heavily doped p-type and n-type. The basic equation
of leakage current is shown in Eq.4
Ileak = Isub + Iox

(4)

Where, Isub = sub-threshold leakage current, Iox = gate-oxide leakage

current.

Where, K1 and n are experimentally derived, W = gate width, Vth =

threshold voltage, n = slope shape factor, V = thermal voltage.

Where, K2 and are derived experimentally, Tox = oxide thickness.

Table 1 shows the leakage current of 10T and 14T full adder cell using
double gate MOSFET at different supply voltage. Fig 7 and fig 8 shows
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the leakage current waveform of double gate 14T and 10T full adder cell
at 0.7V.
Voltage 10T Full Adder (pA) 14T Full Adder (pA)
0.7
3.646
58.2
0.8
3.915
84.6
0.9
5.165
144
1.0
5.401
220
Table 1. Leakage current at difference voltages of 10t
and 14t full adder

Fig.7. Leakage Current Waveform of Double Gate 14T Full

Adder at 0.7V
There are two types of leakage current: ac leakage and dc leakage. Dc
leakage current usually applies only to end-product equipment, not to
power supplies. Ac leakage current is caused by a parallel combination of
capacitance and dc resistance between a voltage source (ac line) and the
grounded conductive parts of the equipment. The leakage caused by the
dc resistance usually is insignificant compared to the ac impedance of
various parallel capacitances.

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Fig.8. Leakage Current Waveform of Double Gate 10T Full

Adder at 0.7V
4.2 ACTIVE POWER
At the time of operating the power is dissipated by the circuit is known
as active power. Active power includes both static power and dynamic
power of the circuit. The basic equation of active power is shown in Eq.
(7)
Pactive = Pdyanamic + Pstatic

(7)

=Pswitching + Pshort-circuit + Pleakage

Where,
Cl = load capacitance,
fclk = clock frequency,
= switching activity,
Isc = short circuit current,
Ileakage = leakage current,
Vdd = supply voltage

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Table 2. Active power at difference voltages of 14t full

adder
10T Full
Voltage Adder(W)
0.7
9.34
0.8
15.21
0.9
21.95
1
29.61

14T Full Adder

(W)
13.7
23.56
39.69
61.52

Fig.9. Active Power Waveform of Double Gate 14T Full Adder

at 0.7V

Fig.10. Active Power Waveform of Double Gate 10T Full Adder

at 0.7V
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Table 2 shows the active power of 10T and 14T full adder cell using
double gate MOSFET at different supply voltage. Fig 9 and fig 10 shows
the active power waveform of double gate 14T and 10T full adder cell at
0.7V.
4.3 DELAY
Propagation delay is required by a digital signal to travel from that input
of the circuit to the output. The propagation delay is inversely
proportional to the speed of the architecture and hence it is important
performance parameter. The basic equation of delay in presence of sleep
transistor is shown in Eq. (9) the propagation delay for an integrated
circuit (IC) logic gate may differ for each of the inputs. If all other factors
are held constant, the average propagation delay in a logic gate IC
increases as the complexity of the internal circuitry increases.

Some IC technologies have inherently longer tpd values than others, and
are considered "slower." Propagation delay is important because it has a
direct effect on the speed at which a digital device, such as a computer,
can operate. This is true of memory chips as well as microprocessors.

Fig.11.Delay Comparison Graph of 10T and 14T Full Adder Circuit.

5. CONCLUSION
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The analysis carried out while analyzing both l0T and 14T full adders
individually and comparing them on the basis of calculation of active
power, leakage current and delay by varying different parameters. The
outcomes of the simulation show that l0T full adder to be a better option
with improved performance over 14T structure. As compare to 14T
double gate full adder active power of 10T full adder is reduced from
13.7W to 9.34 W at 0.7V. As compare to 14T double gate full adder
Leakage current of 10T full adder is reduced from 58.2pA to 3.646pA at
0.7V.As compare to 10T double gate full adder Delay of 14T double gate
full adder is reduced from 171.3ps to 151ps.
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