Decoders and Encoders

Lesson Objectives
In this lesson, we will learn about
o Decoders
o Expansion of decoders
o Combinational circuit implementation with decoders
o Some examples of decoders
o Encoders
o Major limitations of encoders
o Priority encoders
o Some examples of ecnoders

Decoders
As its name indicates, a decoder is a circuit component that decodes an input code. Given
a binary code of n-bits, a decoder will tell which code is this out of the 2n possible codes
(See Figure 1(a)).

n-to-2n
Decoder

n Inputs

0
1
2n-1

Figure 1(a): A typical decoder

Thus, a decoder has n- inputs and 2n outputs. Each of the 2n outputs corresponds to one
of the possible 2n input combinations.

n Inputs

Enable

n-to-2n
Decoder

2 n Outputs

Figure 1(b): A typical decoder

Figure 1(b) shows the block diagram o f a typical decoder, which has n input lines, and m
output lines, where m is equal to 2n . The decoder is called n-to- m decoder. Apart
from this, there is also a single line connected to the decoder called enable line. The
operations of the enable line will be discussed in the flowing text.

o
i.

In general, output i equals 1 if and only if the input binary code has a value of

Thus, each output line equals 1 at only one input combination but is equal to 0 at
all other combinations.

In other words, each decoder output corresponds to a minterm of the n input

variables.

Thus, the decoder generates all of the 2n minterms of n input variables.

Example: 2-to-4 decoders

Let us discuss the operation and combinational circuit design of a decoder by taking the
specific example of a 2-to-4 decoder. It contains two inputs denoted by A1 and A0 and
four outputs denoted by D0 , D1 , D2 , and D3 as shown in figure 2. Also note that A1 is
the MSB while A0 is the LSB.

D0 = A1A0
A0
A1

D1 = A1A0

2-to-4
Decoder

D2= A1A0
D3 = A1A0

Figure 2: A 2- to -4 decoder without enable

Decimal #
0
1
2
3

Input
A1
A0
0
0
0
1
1
0
1
1

D0
1
0
0
0

Output
D1
D2
0
0
1
0
0
1
0
0

D3
0
0
0
1

Table 1: Truth table for 2-to -4 decoder

As we see in the truth table (table 1), for each input combination, one output line is
activa ted, that is, the output line corresponding to the input combination becomes 1,
while other lines remain inactive. For example, an input of 00 at the input will activate
line D0 . 01 at the input will activate line D1 , and so on.

Notice that, each output of the decoder is actually a minterm resulting from a
certain combination of the inputs, that is
o D0 =A1 A0 , ( minterm m0 ) which corresponds to input
00 o D1 =A1 A0 , ( minterm m1 ) which corresponds to
input 01 o D2 =A1 A0 , ( minterm m2 ) which corresponds
to input 10 o D3 =A1 A0 , ( minterm m3 ) which
corresponds to input 11

This is depicted in Figures 2 where we see that each input combination will
inovke the corresponding output, where each output is minterm corresponding to
the input combination.
A1

A0

D0 = A1A0
D1 = A1A0
D2 = A1A0
D3 = A1A0
Figure 3: Implementation 2-to -4 decoder
The circuit is implemented with AND gates, as shown in figure 3. In this circuit we see
that the logic equation for D0 is A1 / A0 /. D0 is A1 / A0 , and so on. These are in fact
the minterms being implemented. Thus, each output of the decoder generates a minterm
corresponding to the input combination.

The enable input in decoders

Generally, decoders have the enable input .The enable input perroms no logical
operation, but is only responsible for making the decoder ACTIVE or
INACTIVE. o If the enable E
o is zero, then all outputs are zero regardless of the input values.
o is one, then the decoder performs its normal operation.
For example, consider the 2-to-4 decoder with the enable input (Figure 4). The enable
input is only responsible for making the decoder active or inactive. If Enable E is zero,
then all outputs of the decoder will be zeros, regardless of the values of A1 and A0 .
However, if E is 1, then the decoder will perform its normal operation, as is shown in the

truth table (table 2). In this table we see that as long as E is zero, the outputs D0 to
D3 will remain zero, no matter whatever value you provide at the inputs A1 A0 , depicted
by two dont cares. When E becomes 1, then we see the same behavior as we saw in the
case of 2-to-4 decoder discussed earlier.
E

A1

A0

D0
D1
D2
D3

Figure 4: Implementation 2-to -4 decoder with enable

Decimal Enable
value
E
0
0
1
1
1
2
1
3
1

Inputs
A1
X
0
0
1
1

A0
X
0
1
0
1

Outputs
D0
0
1
0
0
0

D1
0
0
1
0
0

D2
0
0
0
1
0

D3
0
0
0
0
1

Table 2: Truth table of 2-to -4 decoder with enable

Example: 3-to-8 decoders

In a three to eight decoder, there are three inputs and eight outputs, as shown in figure 5.
A0 is the least significant variable, while A2 is the most significant variable.
The three inputs are decoded into eight outputs. That is, binary values at the input form a
combination, and based on this combination, the corresponding output line is activated.

A0
A1
A2

D0 = A2A1A0
D1 = A2A1A0
D2 = A2A1A0
D3 = A2A1A0
D4 = A2A1A0
D5 = A2 A1 A0
D6 = A2A1A0
D7 = A2A1A0

3-to-8
Decoder

Enable

Figure 5: A 3- to -8 decoder with enable

Each output represents one minterm .
o For example, for input combination A2 A1 A0 = 001, output line D1 equals 1 while
all other output lines equal 0s
o It should be noted that at any given instance of time, one and only one output line
can be activated. It is also obvious from the fact that only one combination is
possible at the input at a time, so the corresponding output line is activated.
Dec.
Code
0
1
2
3
4
5
6
7

Inputs

Outputs

A2 A1 A0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

1
0
0
0
0
0
0
0

0
1
0
0
0
0
0
0

0
0
1
0
0
0
0
0

0
0
0
1
0
0
0
0

0
0
0
0
1
0
0
0

0
0
0
0
0
1
0
0

0
0
0
0
0
0
1
0

0
0
0
0
0
0
0
1

Table 3: Truth table of 3-to -8 decoder

Since each input combination represents one minterm, the truth table (table 3) contains
eight output functions, from D0 to D7 seven, where each function represents one and only
one minterm. Thus function D0 is A2 / A1 / A0 /. Similarly function D7 is A2 A1 A0 .
The corresponding circuit is given in Figure 6. In this figure, the three inverters
provide complement of the inputs, and each one of the AND gates generates one of the
minterms. It is also possible to add an Enable input to this decoder.

Figure 6: Implementation of a 3-to -8 decoder without enable

Decoder Expansion
o

It is possible to build larger decoders using two or more smaller ones.

For example, a 6-to-64 decoder can be designed with four 4-to-16 decoders and one
2-to-4 line decoder.

Example : Construct a 3-to-8 decoder using two 2-to-4 deocders with

enable inputs.
Figure 7 shows how decoders with enable inputs can be connected to form a larger
decoder. Two 2-to-4 line decoders are combined to build a 3-to-8 line decoder.
o The two least signifncat bits (i.e. A1 and A0 ) are connected to both decoders
o Most signifcant bit (A2 ) is connected to the enable input of one decoder.
o The complement of most significant bit (A2 ) is connected to the enable of the
other decoder.
o When A2 = 0, upper decoder is enabled, while the lower is disabled. Thus, the
outputs of the upper decoder correspond to minterms D0 through D3.
o When A2 = 1, upper decoder is disabled, while the lower is enabled. Thus, the
outputs of the lower decoder correspond to minterms D4 through D7 .

Figur e 7: Implementing a 3-to -8 decoder with two 2-to -4 decoders

Decoder design with NAND gates

o

Some decoders are constructed with NAND rather than AND gates.

In this case, all decoder outputs will be 1s except the one corresponding to the input
code which will be 0.
Decimal #
0
1
2
3

Input
A1
A0
0
0
0
1
1
1
1
1

D0
0
1
1
1

Output
D1 D2
1
1
0
1
1
0
1
1

D3
1
1
1
0

Table 4: Truth table of 2-to -4 decoder with NAND gates

This decoder can be constructed without enable, similar to what we have seen in the
design of decoder with AND gates, without enable. The truth table and corresponding
minters are given in table 4. Notice that the minters are in the complemented form.

Figure 8: A 2- to -4 decoder with Enable constructed with NAND gates.

Decimal Enable
value

E
0
1
2
3

1
0
0
0
0

Inputs
A1
X
0
0
1
1

A0
X
0
1
1
1

Outputs
D0
1
0
1
1
1

D1
1
1
0
1
1

D2
1
1
1
0
1

D3
1
1
1
1
0

Table 5: Truth table of 2-to -4 decoder with Enable using NAND gates
A 2-to-4 line decoder with an enable input constructed with NAND gates is shown in
figure 8. The circuit operates with complemented outputs and enable input E is also
complemented to match the outputs of the NAND gate decoder. The decoder is enabled
when E is equal to zero. As indicated by the truth table, only one output can be equal to
zero at any given time, all other outputs being equal to one. The output with the value of
zero represents the minterm selected by inputs A1 and A0 . The circuit is disabled when
E is equal to one, regardless of the values of the other two inputs. When the circuit is
disabled, none of the outputs are equal to zero, and none of the minterms are selected.
The corresponding logic equations are also given in table 5.

Combinational circuit implementation using decoder

o
o
o
o

As known, a decoder provides the 2n minterms of n input variables

Since any boolean functions can be expressed as a sum of minterms, one can use a
decoder to implement any function of n variables.
n
In this case, the decoder is used to generate the 2 minterms and an additional OR
gate is used to generate the sum of the required minterms.
In this way, any combinational circuit with n inputs and m outputs can be

implemented using an n-to-2n decoder in addition to m OR gates.

Remember,
that
o The function need not be simplified since the decoder implements a function using
the minterms, not product terms.
o

Any number of output functions can be implemented using a single decoder,

provided that all those outputs are functions of the same input variables.

Example : Decoder Implementation of a Full Adder

Let us look at the truth table (table 6) for the given problem. We have two outputs, called
S, which stands for sum, and C, which stands for carry. Both sum and carry are functions
of X, Y, and Z.
Decimal
value

Input

0
1
2
3
4
5
6
7

Output

0
0

0
1

1
0

1
1

0
0

1
1

0
0

0
1

1
0

0
1

1
1

1
1

0
1

0
1

1
1

Table 6: Truth table of the Full Adder

o
The output functions S & C can be expressed in sum-of-minterms forms as
follows:
o S (X,Y,Z) = m (1,2,4,7)
o C (X,Y,Z) = m (3,5,6,7)
Looking at the truth table and the functions in sum of minterms form, we observe that
there are three inputs, X, Y, and Z that correspond to eight minterms. This implies that a
3-to-8 decoder is needed to implement this function. This implementation is given in
Figure 9, where the sum S is implemented by taking minterms 1, 2, 4, and 7 and the OR
gates forms the logical sum of minterm for S. Similarly, carry C is implemented by
taking logical sum of minterms 3, 5, 6, and 7 from the same decoder.
3-to-8
Decoder

20

21

22

0
1
2

3
4
5
6
7

Encoders
o
o
o
o

Figure 9: Decoder implementation of a Full Adder

An encoder performs the inverse operation of a decoder, as shown in Figure 10.

n
It has 2 inputs, and n output lines.
Only one input can be logic 1 at any given time (active input). All other inputs must
be 0s.
Output lines generate the binary code corresponding to the active input.
2n-to-n
Encoder

2 Inputs

n Outputs

Figure 10: A typical Encoder

Example: Octal-to-binary encoder

We will use 8-to-3 encoder (Figure 11) for this problem, since we have eight inputs, one
for each of the octal digits, and three outputs that generate the corresponding binary
number. Thus, in the truth table, we see eight input variables on the left side of the
vertical lines, and three variables on the right side of the vertical line (table 7).
Inputs
E7 E6 E5 E4 E3 E2 E1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0

Outputs
E0 A2 A1 A0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1

Decimal
Code
0
1
2
3
4
5
6
7

Table 7: Truth table of Octal-to -binary encoder

8 Inputs

E0
E1
E2
E3
E4
E5
E6
E7

A0

8-to-3
Encoder

3 Outputs

A1
A2

Figure 11: Octal-to -binary encoder

o
o
o
o

Note that not all input combinations are valid.

Valid combinations are those which have exactly one input equal to logic 1 while all
other inputs are logic 0s.
Since, the number of inputs = 8, K-maps cannot be used to derive the output Boolean
expressions.
The encoder implementation, however, can be directly derived from the truth table
o Since A0 = 1 if the input octal digit is 1 or 3 or 5 or 7, then we can write:
A0 = E1 + E3 + E5 + E7
o Likewise, A1 = E2 + E3 + E6 + E7 , and similarly
o A2 = E4 + E5 + E6 + E7
Thus, the encoder can be implemented using three 4- input OR gates.

Major Limitation of Encoders

o
o
o

Exactly one input must be active at any given time.

If the number of active inputs is less than one or more than one, the output will be
incorrect.
For example, if E3 = E6 = 1, the output of the encoder A2 A1 A0 = 111, which
implies incorrect output.

Two Problems to Resolve.

1. If two or more inputs are active at the same time, what should the output be?
2. An output of all 0's is generated in 2 cases:
o when all inputs are 0
o when E0 is equal to 1.
How can this ambiguity be resolved?
Solution To Problem 1:
o Use a Priority Encoder which produces the output corresponding to the input with
higher priority.
o Inputs are assigned priorities according to their subscript value; e.g. higher subscript
inputs are assigned higher priority.
o In the previous example, if E3 = E6 = 1, the output corresponding to E6 will
be produced (A2 A1 A0 = 110) since E6 has higher priority than E3 .

Solution To Problem 2:
o Provide one more output signal V to indicate validity of input data.
o V = 0 if none of the inputs equals 1, otherwise it is 1

Example : 4-to-2 Priority Encoders

o
o
o

Sixteen input combinations

Three output variables A1, A0, and V
V is needed to take care of situation when all inputs are equal to zero.
Outputs
Inputs
E3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

E2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

E1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

E0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

A1
X
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

A0
X
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1

V
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

Invalid
Input

Table 8: Truth table of 4-to -2 Priority Encoder

In the truth table (table 8), we have sixteen input combinations. In the output, we have
three variables. The variable V is needed to take care of the situation where all inputs
are zero. In that case V is kept at zero, regardless of the values of A1 and A0 . This
combination is highlighted green. In all other cases, V is kept at 1, because at least one of
the inputs is one.
When E0 is 1, the output combination of A1 and A0 is 00. This combination is
highlighted blue.
Then we have two combinations highlighted yellow. In both these combinations, A1 and
A0 are 01. This is because in both these combinations E1 is 1, regardless of the value of
E0 , and since E1 has higher subscript, the corresponding output value is 01.
This is followed by four input combinations in pink. In these four combinations, the
output A1 A0 is 10, since E2 is 1 in all these combinations, and E2 has the
highest

precedence compared to E0 and E1 . Although E0 and E1 are also having a value of one
in this set of four combinations, but they do not have the priority.
Finally we have the last eight input combinations, whose output is 11. This is because E3
is the highest priority input, and it is equal to 1. Though the other inputs with smaller
subscripts, namely, E2, E1, and E0 are also having values of one in some combinations,
but they do not have the priority.
The truth table can be rewritten in a more compact form using dont care conditions for
inputs as shown below in table 9.
Inputs

1
2
3
4
5

E3 E2
0
0
0
0
0
0
0
1
1 X

E1 E0
0
0
0
1
1 X
X X
X X

Outputs
A1 A0 V
X X 0
0
0 1
0
1 1
1
0 1
1
1 1

Table 9: Truth table of 4-to -2 priority encoder (compact fo rm)

o

With 4 Input variables, the truth table must have 16 rows, with each row
representing an input combination.

With dont care input conditions, the number of rows can be reduced since rows with
dont care inputs will actually represent more than one input combination.

Thus, for example, row # 3 represents 2 combinations since it represents the input
conditions E3 E2 E1 E0 =0010 and 0011.

Likewise, row # 4 represents 4 combinations since it represents the input conditions

E3 E2 E1 E0 =0100, 0101, 0110 and 0111.

Similarly, row # 5 represents 8 combinations.

Thus, the total number of input combinations represented by the 5-row truth table =
1+ 1+ 2+ 4 + 8= 16 input combinations.

Boolean Expressions for V, A1 and A0 and the circuit:

See next page:

Figure 12: Equations and circuit for 4-to -2 priority encoder