EC 101AComputerOrganization
EC 101AComputerOrganization
Processor
``CPU''
Control
Datapath
+
Control
Unit
Datapath
Input
Memory
Output
Software
Hardware
Operating System
Compiler
(Unix;
Windows 2000)
Assembler
Instruction Set
Architecture
Execution Cycle
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction
STORE
For writing a word into
a given memory
location:
1. MAR [R1]
2. MDR [R2], Write
3. Wait for MFC
Register transfers
Data transfer requires input and
output gates. These are
controlled in and out signals. For
register Ri:
Ri_in = 1 => data available on
common bus is loaded into Ri
Ri_out = 1 => Contents of Ri are
placed on the bus.
To transfer contents of R1 to R4
Set R1_out to 1 => contents
of R1 placed on CPU bus
Set R4_in to 1 => data loaded
from the CPU bus into R4
Instructions