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VHDL - Master D Flipflop

We first define a NAND gate entity. Then, we construct a D-latch entity using four NAND gates. Finally, we construct a master-slave D flip-flop using two D-latches and two inverters. The document then provides VHDL code defining these structural components.

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106 views2 pages

VHDL - Master D Flipflop

We first define a NAND gate entity. Then, we construct a D-latch entity using four NAND gates. Finally, we construct a master-slave D flip-flop using two D-latches and two inverters. The document then provides VHDL code defining these structural components.

Uploaded by

kkjkjkjkljkghk
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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1] First, we define a NAND Gate entit

--2] Second, we construct a D-latch entity using four


-NAND Gates.
--3] Finally, we construct the master-slave D flipflop
-using two D-latches and two inverters.
--One of the advantages of structural designs is that
-from the VHDL program you can tell what the physical
-circuit looks like.
--It is very important to learn structural design (RTL)
-strategies because as your assignments become larger
-and larger, knowledge of register transfer level
-(RTL) design strategies become indispensable.
-------------------------------------------------------------- We first define a NAND Gate entity. Later we will
-- construct the D-latch entity using this NAND Gate.
library ieee;
use ieee.std_logic_1164.all;
entity nandGate is
port(A, B : in std_logic;
F : out std_logic);
end nandGate;
-----------architecture nandFunc of nandGate is
begin
F <= A nand B;
end nandFunc;
--*===================================== END NAND GATE
--Here we define the D-Latch entity. Observe that in
--the architecture section the NAND Gate is used to
--build the structural core of the D-latch.
library ieee;
use ieee.std_logic_1164.all;
entity D_latch is
port(clk, D : in std_logic;
Q, notQ : out std_logic);
end D_latch;
-architecture func of D_latch is
component nandGate is
port(A, B : in std_logic;
F : out std_logic);
end component;
-signal topWire, botWire, Qback, notQback : std_logic;
begin
G1: nandGate port
G2: nandGate port
G3: nandGate port
G4: nandGate port
Q <= Qback;
notQ <= notQback;

map(D, clk, topWire);


map(topWire, clk, botWire);
map(topWire, notQback, Qback);
map(Qback, botWire, notQback);

end func;
--*===================================== END Data Latch
--Before we define the master-slave D-flipflop, we must
--first define an inverter entity; as we will need
--inverters to build the structural core D-flipflop.
library ieee;
use ieee.std_logic_1164.all;
entity notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end notGate;
-architecture func of notGate is
begin
outPort <= not inPort;
end func;
--*===================================== END NOT Gate
--Finally we define the Master-Slave Data flipflop circuit.
--After this we are done as it is the top-level of our design
library ieee;
use ieee.std_logic_1164.all;
entity ms_Data_ff is
port( clk, D : in std_logic;
Q, notQ : out std_logic);
end ms_Data_ff;
-architecture func of ms_Data_ff is
--import the inverter entity as a component
component notGate is
port( inPort : in std_logic;
outPort : out std_logic);
end component;
--import the D-latch entity as a component
component D_latch is
port(clk, D : in std_logic;
Q, notQ : out std_logic);
end component;
--interconnecting wires carrying signals to the components
--we define a dummy signal because all ports must be wired
signal invOut1, invOut2, Dout, dummy : std_logic;
begin
G1: notGate port map(clk, invOut1);
G2: notGate port map(invOut1, invOut2);
G3: D_latch port map(invOut1, D, Dout, dummy);
G4: D_latch port map(invOut2, Dout, Q, notQ);
end func;
----------------------------------------------------------END
----------------------------------------------------------END

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