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LAB 8."binary Multiplier" in FPGA

This document describes a student lab assignment to implement 4-bit binary multipliers in an FPGA. It discusses two architectures - one using three 4-bit adders and one using partial product blocks. The students synthesized and simulated both architectures in VHDL before implementing on an FPGA board using switches as inputs and LEDs as outputs. They verified the designs worked correctly by performing sample multiplications. The lab helped them learn binary multiplication methodology and building complex designs from basic components like adders and gates. Analysis found the first design used 25 LUTs, 15 IOBs, and 35% of FPGA resources with no flip-flops.

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MarcoCiau
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208 views2 pages

LAB 8."binary Multiplier" in FPGA

This document describes a student lab assignment to implement 4-bit binary multipliers in an FPGA. It discusses two architectures - one using three 4-bit adders and one using partial product blocks. The students synthesized and simulated both architectures in VHDL before implementing on an FPGA board using switches as inputs and LEDs as outputs. They verified the designs worked correctly by performing sample multiplications. The lab helped them learn binary multiplication methodology and building complex designs from basic components like adders and gates. Analysis found the first design used 25 LUTs, 15 IOBs, and 35% of FPGA resources with no flip-flops.

Uploaded by

MarcoCiau
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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LAB 8.

Binary Multiplier in FPGA


Ciau Ku Marco, Sma Canul Ana Laura, Soriano Pat
Marvin, Uitz Ojeda Erik.
DIEEE

Ciau Ku Marco, Sma Canul Ana Laura, Soriano Pat


Marvin, Uitz Ojeda Erik.
DIEEE

Mrida Yucatn
[email protected]

Mrida Yucatn
[email protected]

Objective

This lab meant that students can implement a 4 bit


combinational multiplier, which in turn serves to properly
understand the method of binary multiplication, and the
construction of complex structures from basic blocks
previously implemented, how for example: adders and logic
gates.

Abstract

In this lab you will work with binary multipliers. Two


architectures of multipliers are implemented. The first is a
multiplier in which the structure is formed by three 4-bit
adders, which through cumulative sum allows us to obtain the
final product. The second is constituted by small blocks, in
which the calculation of the partial product is made. Later,
these architectures will be implemented in the FPGA device.
.
I.

INTRODUCTION

Sometimes in digital design there are certain operations or


combinational circuits that seem very complex; for example a
multiplier. It seems difficult to make your design, but it's
funny to say that the multiplication of binary numbers is done
like that for decimal numbers. Let's say that we are asked to
multiply a number by another B. multiplying each bit is
multiplied by the multiplier, starting with the least significant
bit. As in the decimal system, each of these forms a partial
product multiplication. Successive partial products are shifted
one position to the left. The final product is obtained by
adding the partial products.
Explain how a binary multiplier implemented in a
combinational circuit; consider the multiplication of two
numbers of two bits (A0, A1) and (B0, B1). The multiplicand

bits B1 and B0 are the bits of the multiplier are A1 and A0,
and the product is C3C2C1C0. The first partial product is
formed by multiplying A0 B1B0. The partial product can be
implemented with AND gates. The second partial product is
formed by multiplying A1B1B0 and a position is shifted to
the left. The two partial products with two circuits half adder
(HA). Usually, the partial products are more bits, and this
requires using full adders for the sum of the partial products.
Note that the least significant bit of the product does not have
to go through an adder because it forms with the output of the
first AND gate.

II.

DEVELOP OF THE PRACTICE

The procedure is divided into two parts. The first is the


synthesis and implementation of the code in VHDL
architecture 1. In this process it is necessary to copy the code
given in the manual. After the synthesis and our project
simulation (the simulation is shown in Figure 1, the next step
is to load the file UCF; Lastly proceed to program the FPGA
In our device, is used as input switches and as the LED's
output will be used.
It is found that our implementation is correct by performing
several multiplications.
The second part of the practice is based on the realization of
the synthesis and implementation architecture VHDL 2 as
indicated in the manual. New projects are created and
synthesized the corresponding code to architecture; then
proceed to perform the simulation to verify the correct
functioning of our architecture before implementing in the
FPGA.

The result of this simulation is shown in Figure 2. Now, we


will implement our work on our device, for that, the UCF file
is created and implemented the multiplier. As in the previous
process, in our device, are used as inputs and outputs
switches and LEDs are used. It is found that our
implementation is correct by performing several
multiplications.

a)

III.

CONCLUTIONS

In this lab, it is possible to learn two basic things; the first


was the method of multiplying in the binary system. The
second lesson was the implementation of relatively complex
architectures by instantiating components. It is noteworthy
that the instantiation process was very useful for the
realization of VHDL code that helped in optimizing the
duration and time of practice.

IV.

PERFORMANCE ANALYSIS OF FPGA ARCHITECTURES

1. - How many LUTs used in the synthesis?


R= Used 25 LUTs
2. - How many Flip-flops used in the synthesis?
R= none
3. - What is the number of IOBs used in the synthesis?
R= Used 15 IOBs
b)

Figure1. Simulation signal multiplier a) in


binary b) in decimal.

a)

b)

Figure1. Simulation signal multiplier a) in


binary b) in decimal.

4. - What is the percentage of gates used in the Design?


R= The 35% of programming

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