Microprocessors and Microcontrollers III B.

Tech II Sem

UNIT I
8086 Architecture

Contents:

1.1 Introduction to 8085 Microprocessor

1.1.1 Features of 8085
1.1.2 Functional Block Diagram
1.1.3 Pin Diagram
1.2 8086 Architecture
1.2.1 Features of 8086
1.2.2 Functional Block Diagram
1.3 Register organization(Programming model) of 8086
1.3.1 Registers of 8086
1.3.2 General purpose resisters & their special functions
1.3.3 Pointer & Index Registers
1.3.4 Segment Registers
1.3.5 Other Registers (Instruction Pointer, Flag Register)
1.4 Memory Segmentation, Memory Addresses
1.5 Physical Memory Organization
1.6 Signal Descriptions of 8086 (Pin Diagram)
1.6.1 Common function signals
1.6.2 Minimum mode signals
1.6.3 Maximum mode signals
1.7 Timing Diagrams
1.7.1 General Bus Operation
1.7.2 Minimum mode timing diagram
1.7.3 Maximum mode timing diagram
1.8 Interrupts of 8086

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1.1 Introduction to 8085 Microprocessor

1.1.1 Features of 8085
It is an 8 bit microprocessor.
It is manufactured with N-MOS technology.
It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory
locations through A0-A15.
The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0-AD7.
Data bus is a group of 8 lines D0-D7.
It supports external interrupt request.
A 16 bit program counter (PC).
A 16 bit stack pointer (SP).
Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
It is enclosed with 40 pins DIP (Dual in line package).

1.1.2 Functional Block Diagram

Interrupt Controller

ACC
8 bit

Temp
Reg-8 bit

Flags
5 bit

Serial I/O Controller

Instruction
Reg 8 bit

B Reg-8 bit C Reg-8 bit

D Reg-8 bit E Reg-8 bit
H Reg-8 bit L Reg-8 bit

ALU
8 bit

Instruction
decoder
and
machine
cycle
encoder

Timing and
Controller

Stack Pointer 16 bit

Program Counter 16 bit
Increment/Decrement
Address Latch 16 bit

Address Buffer
8 bit

Data/Address
Buffer 8 bit

Data Bus: It has an 8-bit bidirectional data bus which is used for data input as well as data output in
the form of 8 bit words.
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Address Bus: The address bus is 16-bit wide, i.e., the 8085 has 16 bit address transmission
capability. Which means that a total of 216 (65536) memory locations can be addressed directly by
8085 or we can say that the memory address space is 64 Kbytes.
ALU: 8-bit ALU, where the arithmetic and logical operations are performed.
General Purpose Registers: There are six 8 bit general purpose registers labeled as B, C, D, E, H
and L. These registers are used in pairs, as BC, DE and HL.
Accumulator: While performing arithmetic and logical operations, etc. one of the operand is
contained in the accumulator. The result of these operations is also stored in the accumulator. It is
an 8 bit register labeled as A.
Stack Pointer: It is a 16 bit register used by the programmer to maintain a stack in the memory. It
points to a memory location in R/W memory and the beginning of the stack is defined by loading
the 16 bit address in the stack pointer.
Program Counter: The function of the program counter is to point to the memory location from
which the next byte is to be fetched. When a byte is being fetched the program counter is
incremented by one to point to the next memory location.
Instruction Register: An instruction fetched from memory is temporarily stored in the IR prior to its
decoding.
Flags: There are five flag bits used in 8085.
1. Zero (Z)
2. Sign (S)
3. Parity (P)
4. Carry (CY)
5. Auxiliary Carry (AC)

Timing & Control: Is used to generate proper timing & control signals which control &
synchronize all the operations performed by various sections.
Interrupt Controller: It receives hardware interrupt signals & sends an acknowledgement for
receiving the interrupt signals.
Serial I/O control: It has two control signals named SID & SOD for serial data transmission.

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1.1.3 Pin Diagram of 8085

Power Supply and Clock frequency signals

VCC: + 5 volt power supply
GND: Ground Reference
X1, X2: Crystal or R/C network or LC network connections to set the frequency of internal
clock generator.
CLKOUT (output)-Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
Address Bus
A8 - A15 (output; 3-state)
It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address.
Multiplexed Address / Data Bus
AD0 - AD7 (input/output; 3-state)
These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order
address A0 - A7.
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In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.
The CPU may read or write out data through these lines.
Control signals
ALE (output) - Address Latch Enable. This signal helps to capture the lower order address
presented on the multiplexed address / data bus.
RD (output 3-state, active low) - Read memory or IO device. This indicates that the selected
memory location or I/O device is to be read and that the data bus is ready for accepting data
from the memory or I/O device.
WR (output 3-state, active low) - Write memory or IO device. This indicates that the data
on the data bus is to be written into the selected memory location or I/O device.
IO/M (output) - Select memory or an IO device. This status signal indicates that the read /
write operation relates to whether the memory or I/O device. It goes high to indicate an I/O
operation. It goes low for memory operations.
Status signals
It is used to know the type of current operation of the microprocessor.

Interrupts and externally initiated operations:

They are the signals initiated by an external device to request the microprocessor to do a
particular task or work.
There are five hardware interrupts called,
o TRAP
o RST 7.5
o RST 6.5
o RST 5.5
o INTR

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INTA: On receipt of an interrupt, the microprocessor acknowledges the interrupt by the
active low INTA (Interrupt Acknowledge) signal.

Reset In (input, active low)

This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero. The buses are tri-stated.

Reset Out (Output)

It indicates CPU is being reset. Used to reset all the connected devices when the
microprocessor is reset.

HOLD, HLDA
HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer of
data.

READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle further
data or control signal from CPU.
The processor sets the READY signal after completing the present job to access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.

Single Bit Serial I/O ports:

SID (input): Serial input data line
SOD (output): Serial output data line
These signals are used for serial communication.

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1.2 8086 Architecture

1.2.1 Features of 8086
It is a 16-bit Microprocessor (p).Its ALU, internal registers works with 16bit binary word.
8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.
8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at
a time.
It can support up to 64K I/O ports.
It provides 14, 16 -bit registers.
Frequency range of 8086 is 6-10 MHz
It has multiplexed address and data bus AD0- AD15 and A16 A19.
It requires single phase clock with 33% duty cycle to provide internal timing.
It can pre-fetch up to 6 instruction bytes from memory and queues them in order to speed up
instruction execution.
It requires +5V power supply.
A 40 pin dual in line package.
8086 is designed to operate in two modes, Minimum mode and Maximum mode.
The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a
single microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a
multi micro processors configuration.

1.2.2 Functional block diagram of 8086

8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).
The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands. The
instruction bytes are transferred to the instruction queue.
EU executes instructions from the instruction system byte queue.
Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the
system bus and system performance.
BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.
EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag
register.
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BUS INTERFACE UNIT:

It provides a full 16 bit bidirectional data bus and 20 bit address bus.
The bus interface unit is responsible for performing all external bus operations.
Specifically it has the following functions:
o Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation
and Bus control.
The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.
This queue permits pre-fetch of up to six bytes of instruction code. Whenever the queue of
the BIU is not full, it has room for at least two more bytes and at the same time the EU is
not requesting it to read or write operands from memory, the BIU is free to look ahead in
the program by pre-fetching the next sequential instruction.
These pre-fetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.
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The EU accesses the queue from the output end. It reads one instruction byte after the other
from the output of the queue. If the queue is full and the EU is not requesting access to
operand in memory, these intervals of no bus activity, which may occur between bus cycles
are known as idle state.
If the BIU is already in the process of fetching an instruction when the EU request it to read
or write operands from memory or I/O, the BIU first completes the instruction fetch bus
cycle before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20 bit physical
address that is output on the address bus. This address is formed by adding an appended 16
bit segment address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents of
the instruction pointer IP register.
The BIU is also responsible for generating bus control signals such as those for memory
read or write and I/O read or write.

EXECUTION UNIT:
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write
bys cycles to memory or I/O and perform the operation specified by the instruction on the
operands.
During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to
top of the queue.
When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

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1.3 Register Organization

1.3.1 Registers of 8086
The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer.
It is divided into four groups. They are:
General purpose registers (4)
o AX (AH-AL) Accumulator
o BX (BH-BL) Base Register
o CX (CH-CL) Count Register
o DX (DH-DL) Data Register
Index/Pointer registers (4)
o SI Source Index
o DI Destination Index
o BP Base Pointer
o SP Stack Pointer
Segment registers (4)
o CS Code Segment
o DS Data Segment
o SS Stack Segment
o ES Extra Segment
Other registers (2)
o IP Instruction Pointer
o Flag Register

1.3.2 General Purpose Registers and their special functions

Accumulator: register consists of two 8-bit registers AL and AH, which can be combined together
and used as a 16-bit register AX. AL in this case contains the low order byte of the word, and AH
contains the high-order byte. Accumulator can be used for I/O operations and string manipulation.
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Base register: consists of two 8-bit registers BL and BH, which can be combined together and used
as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains
the high-order byte. BX register usually contains a data pointer used for based, based indexed or
register indirect addressing.
Count register: consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the low order byte of the word,
and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions
and as a counter in string manipulation
Data register: consists of two 8-bit registers DL and DH, which can be combined together and used
as a 16-bit register DX. When combined, DL register contains the low order byte of the word, and
DH contains the high-order byte. Data register can be used as a port number in I/O operations. In
integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial
or resulting number.

1.3.3 Pointer and Index Registers

Stack Pointer (SP) is a 16-bit register pointing to program stack, i.e, it is used to hold the address of
the top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack segment
(specified by the SS segment register).Unlike the SP register, the BP can be used to specify the
offset of other program segments.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used by
subroutines to locate variables that were passed on the stack by a calling program. BP register is
usually used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data addresses in string manipulation instructions. Used in
conjunction with the DS register to point to data locations in the data segment.

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Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in string
operations. DI is used for indexed, based indexed and register indirect addressing, as well as a
destination data addresses in string manipulation instructions. In short, Destination Index and SI
Source Index registers are used to hold address.

1.3.4 Segment Registers

Most of the registers contain data/instruction offsets within 64 KB memory segment. There
are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1
MB of processor memory these 4 segments are located the processor uses four segment registers.

Code segment (CS) is a 16-bit register containing address of 64KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack. By
default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer
(BP) registers is located in the stack segment. SS register can be changed directly using POP
instruction.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data. By
default, the processor assumes that all data referenced by general registers (AX, BX, CX, and DX)
and index register (SI, DI) is located in the data segment. DS register can be changed directly using
POP and LDS instructions.
Extra segment (ES) used to hold the starting address of Extra segment. Extra segment is provided
for programs that need to access a second data segment. Segment registers cannot be used in
arithmetic operations.

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1.3.5 Other Registers

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is used to
control which instruction the CPU executes. The IP, or program counter, is used to store the
memory location of the next instruction to be executed. The CPU checks the program counter to
ascertain which instruction to carry out next. It then updates the program counter to point to the
next instruction. Thus the program counter will always point to the next instruction to be executed.

Flag Register contains a group of status bits called flags that indicate the status of the CPU or the
result of arithmetic operations. There are two types of flags
1) The status flags which reflect the result of executing an instruction. The programmer
cannot set/reset these flags directly.
2) The control flags enable or disable certain CPU operations. The programmer can set/reset
these bits to control the CPU's operation.

STATUS FLAGS: There are six status flags

1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too
large to fit in the destination register. This happens when there is an end carry in an addition
operation or there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no
carry.
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2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too
large to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when
adding two numbers with the same sign (i.e. both positive or both negative). A value of 1 =
overflow and 0 = no overflow.
3. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is
negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means
negative and 0 = positive.
4. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal
to zero. A value of 1 means the result is zero and a value of 0 means the result is not zero.
5. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to
bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry.
6. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the
number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0.

CONTROL FLAGS: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by such instructions as
MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the
STD (set D) and CLD (clear D) instructions.
2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are
actions initiated by hardware block such as input devices that will interrupt the normal
execution of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and
can be manipulated by the CLI (clear I) and STI (set I) instructions.
3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each
instruction. When this flag is set (i.e. = 1), the programmer can single step through his program
to debug any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3
instruction.

1.4 Memory Segmentation, Memory Address

The 8086 architecture uses the concept of segmented memory. The 8086 has 20 address
lines to enable it to address 1MB (220=1Meg) of memory. However, the largest register is only
16 bits (64k). This 1 megabyte memory is divided into 16 logical segments. Each segment
contains 64 Kbytes of memory.

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Thus a memory location may be specified by providing the 16-bit segment base address,
and a 16-bit offset, written in the form segment:offset; this is known as a logical address for
the memory location.
The addresses of the segment may be assigned as 0000H to F000H respectively. The offset
values are from 0000H to FFFFFH.
If the segmentation is done as per above mentioned way, the segments are called nonoverlapping segments.
In some cases segment may overlap also. Suppose a segment starts at a particular address
and its maximum size can go up to 64 Kbytes. But if another segment starts before this 64
Kbytes location of the first segment, the two segments are said to be overlapping segment.
The area of memory from the start of the second segment to the possible end of the first
segment is called as overlapped segment.

The main advantages of the segmented memory scheme are as follows:

a) Allows the memory capacity to be 1 Mbyte although the actual addresses to be handled are
of 16-bit size
b) Allows the placing of code data and stack portions of the same program in different parts
(segments) of memory, for data and code protection.
c) Permits a program and/ or its data to be put into different areas of memory each time
program is executed, ie, provision for relocation may be done.
Generating a physical address:
The content of segment register (segment address) is shifted left bit-wise four times.
The content of an offset register (offset address) is added to the result of the previous shift
operation.
These two operations together produce a 20-bit physical address.
For example, consider the segment address is 2010H and the offset address is 3535H.
The physical address is calculated as:
Segment Address (2000)
Shifted left by 4 bit positions
Offset address

0010 0000 0000 0000

0010 0000

0000 0000 0000

0011

0101 0011 0101

--------------------------------------------------------------Physical address

0010 0011

0 1 1 0 0 0 1 1 0 1 0 1 (23535H)

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The segment address by the segment value 2000H can have offset value from 0000H to
FFFFH within it, ie. Maximum 64K locations may be accommodated in the segment. The physical
address range for this segment is from 20000H to 2FFFFH.
The segment register indicates the base address of a particular segment and CS, DS, SS and
ES are used to keep the segment address.
The offset indicates the distance of the required memory location in the segment from the
base address, and the offset may be the content of register IP, BP, SI, DI and SP.

1.5 Physical Memory Organization

The memory address space of the 8086-based microcomputers has different logical and
physical organizations.
Logically, memory is implemented as a single 1M 8 memory chunk. The byte-wide
storage locations are assigned consecutive addresses over the range from 00000 16 through
FFFFF16.
Physically, memory is implemented as two independent 512Kbyte banks: the low (even)
bank and the high (odd) bank. Data bytes associated with an even address (00000 16,
0000216, etc.) reside in the low bank, and those with odd addresses (00001 16, 0000316, etc.)
reside in the high bank.
Address bits A1 through A19 select the storage location that is to be accessed. They are
applied to both banks in parallel. A0 and bank high enable (BHE) are used as bank-select
signals.
Each of the memory banks provides half of the 8086's 16-bit data bus. The lower bank
transfers bytes of data over data lines D0 through D7, while data transfers for a high bank
use D8 through D15.

MEMORY ACCESS
Fig(a) shows how a byte-memory operation is performed to address X, an even-addressed
storage location. A0 is set to logic 0 to enable the low bank of memory and BHE to logic 1
to disable the high bank. Data are transferred to or from the lower bank over data bus lines
D0 through D7.
Fig(b) shows how a byte-memory operation is performed to an odd-addressed storage
location such as X + 1. A0 is set to logic 1 and BHE to logic 0. This enables the high bank
of memory and disables the low bank. Data are transferred over bus lines D8 through D15.
D8 represents the LSB.
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Fig(c) illustrates how an aligned word (at even address X) is accessed. Both the high and
low banks are accessed at the same time. Both A0 and BHE are set to 0. This 16-bit word is
transferred over the complete data bus D0 through D15 in just one bus cycle.
Fig(d) illustrates how a misaligned word (at address X + 1) is accessed. Two bus cycles are
needed. During the first bus cycle, the byte of the word located at address X + 1 in the high
bank is accessed over D8 through D15. Even though the data transfer uses data lines D8
through D15, to the processor it is the low byte of the addressed data word. In the second
memory bus cycle, the even byte located at X + 2 in the low bank is accessed over bus lines
D0 through D7.

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1.6 Signal Description of 8086

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and
packaged in a 40 pin CERDIP or plastic package.
The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor
mode) and other function in maximum mode configuration (multiprocessor mode).
The 8086 signals can be categorized in three groups.
o The first are the signal having common functions in minimum as well as
maximum mode.
o The second are the signals which have special functions for minimum mode
o The third are the signals having special functions for maximum mode.

1.6.1 Common function signals

AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address remains
on the lines during T1 state, while the data is available on the data bus during T 2, T3, Tw and T4.
These lines are active high and float to a tri-state during interrupt acknowledge and local bus hold
acknowledge cycles.

A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
o During T1 these are the most significant address lines for memory operations.
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o During I/O operations, these lines are low.
o During memory or I/O operations, status information is available on those lines for T2, T3,
Tw and T4.
o The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
o The S4 and S3 combinely indicate which segment register is presently being used for
memory accesses as in below fig.
o These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is
always low.
o The address bits are separated from the status bit using latches controlled by the ALE
signal.
S4

S3

Indication

0
0
1
1

0
1
0
1

Alternate Data
Stack
Code or None
Data

BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order (D15D8) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to derive
chip selects of odd address memory bank or peripherals.
RD Read: This signal on low indicates the peripheral that the processor is performing memory or
I/O read operation. RD is active low and shows the state for T 2, T3, Tw of any read cycle. The signal
remains tri-stated during the hold acknowledge.

READY: This is the acknowledgement from the slow device or memory that they have completed
the data transfer. The signal made available by the devices is synchronized by the 8284A clock
generator to provide ready input to the 8086. The signal is active high.

INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles of
each instruction to determine the availability of the request. If any interrupt request is pending, the
processor enters the interrupt acknowledge cycle. This can be internally masked by resulting the
interrupt enable flag. This signal is active high and internally synchronized.

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TEST: This input is examined by a WAIT instruction. If the TEST pin goes low, execution will
continue, else the processor remains in an idle state. The input is synchronized internally during
each clock cycle on leading edge of clock.

CLK- Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle.

1.6.2 Minimum mode signals

M/IO Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is
low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the CPU
is having a memory operation. This line becomes active high in the previous T4 and remains active
till final T4 of the current cycle. It is tri-stated during local bus hold acknowledge .
INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt acknowledge
cycles. i.e. when it goes low, the processor has accepted the interrupt.
ALE Address Latch Enable: This output signal indicates the availability of the valid address on
the address/data lines, and is connected to latch enable input of latches. This signal is active high
and is never tri-stated.
DT/R Data Transmit/Receive: This output is used to decide the direction of data flow through
the Tran receivers (bidirectional buffers). When the processor sends out data, this signal is high and
when the processor is receiving data, this signal is low.
DEN Data Enable: This signal indicates the availability of valid data over the address/data lines.
It is used to enable the Tran receivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is
tri-stated during hold acknowledge cycle.

HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the processor that
another master is requesting the bus access. The processor, after receiving the HOLD request,
issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after
completing the current bus cycle.
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1.6.3 Maximum mode signals
S2, S1, S0 Status Lines: These are the status lines which reflect the type of operation, being
carried out by the processor. These become activity during T4 of the previous cycle and active
during T1 and T2 of the current bus cycles.

S2 S1 S0 Indication
0

Interrupt Acknowledge

Read I/O port

Write I/O port

Halt

Code Access

Read Memory

Write Memory

Passive

LOCK: This output pin indicates that other system bus master will be prevented from gaining the
system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK prefix
instruction and remains active until the completion of the next instruction. When the CPU is
executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures
that other processors connected in the system will not gain the control of the bus.

QS1, QS0: Used to know the Queue operation.

QS1 QS0 Indication

0

No Operation

First Byte of the opcode from the queue

Empty Queue

Subsequent Byte from the Queue

RQ/GT0, RQ/GT1 Request/Grant: These pins are used by the other local bus master in
maximum mode, to force the processor to release the local bus at the end of the processor current
bus cycle. Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.
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Microprocessors and Microcontrollers III B.Tech II Sem

1.7 Timing Diagrams

1.7.1 General Bus Operation
The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus.
The main reason behind multiplexing address and data over the same pins is the maximum
utilization of processor pins and it facilitates the use of 40 pin standard DIP package.
The bus can be de-multiplexed using a few latches and transreceivers, when ever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are
referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is
present on the bus only for one cycle.
The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type
of operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Maximum mode
o In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
o In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
o In the maximum mode, there may be more than one microprocessor in the system
configuration.
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Microprocessors and Microcontrollers III B.Tech II Sem

Minimum mode
o In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode
by strapping its MN/MX pin to logic 1.
o In this mode, all the control signals are given out by the microprocessor chip itself.
o There is a single microprocessor in the minimum mode system.

1.7.2 Minimum mode timing diagram

Write Cycle
o The working of the minimum mode configuration system can be better described in terms of
the timing diagrams rather than qualitatively describing the operations.
o The opcode fetch and read cycles are similar. Hence the timing diagram can be categorized
in two parts, the first is the timing diagram for read cycle and the second is the timing
diagram for write cycle.
o The read cycle begins in T1 with the assertion of address latch enable (ALE) signal and also
M / IO signal. During the negative going edge of this signal, the valid address is latched on
the local bus.
o The BHE and A0 signals address low, high or both bytes. From T1 to T4 , the M/IO signal
indicates a memory or I/O operation.
o At T2, the address is removed from the local bus and is sent to the output. The bus is then
tri-stated. The read (RD) control signal is also activated in T2.
o The read (RD) signal causes the address device to enable its data bus drivers. After RD goes
low, the valid data is available on the data bus.

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Microprocessors and Microcontrollers III B.Tech II Sem

o A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO signal is again asserted to indicate a memory or I/O operation. In T2, after sending the
address in T1, the processor sends the data to be written to the addressed location.
o The data remains on the bus until middle of T4 state. The WR becomes active at the
beginning of T2 (unlike RD is somewhat delayed in T2 to provide time for floating).
o The BHE and A0 signals are used to select the proper byte or bytes of memory or I/O word
to be read or write.
Bus Request and Grant

o Hold Response sequence: The HOLD pin is checked at leading edge of each clock pulse. If
it is received active by the processor before T4 of the previous cycle or during T1 state of
the current cycle, the CPU activates HLDA in the next clock cycle and for succeeding bus
cycles, the bus will be given to another requesting master.
o The control of the bus is not regained by the processor until the requesting master does not
drop the HOLD pin low. When the request is dropped by the requesting master, the HLDA
is dropped by the processor at the trailing edge of the next clock.

1.7.3 Maximum mode timing diagram

In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus
controller derives the control signal using this status information.
In the maximum mode, there may be more than one microprocessor in the system
configuration.
The components in the system are same as in the minimum mode system.
The basic function of the bus controller chip IC 8288, is to derive control signals like RD
and WR (for memory and I/O devices), DEN, DT/R, ALE etc. using the information by the
processor on the status lines.
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Microprocessors and Microcontrollers III B.Tech II Sem

The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to 8288 are driven
by CPU.

It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC and
AIOWC.
Here the only difference between in timing diagram between minimum mode and maximum
mode is the status signals used and the available control and advanced command signals.
S0, S1, S2 are set at the beginning of bus cycle. 8288 bus controller will output a pulse as
on the ALE and apply a required signal to its DT / R pin during T1.
In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will activate
MRDC or IORC. These signals are activated until T4. For an output, the AMWC or
AIOWC is activated from T2 to T4 and MWTC or IOWC is activated from T3 to T4.
The status bit S0 to S2 remains active until T3 and become passive during T3 and T4.

If reader input is not activated before T3, wait state will be inserted between T3 and T4.
Write Cycle

Request and Grant Cycle

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Microprocessors and Microcontrollers III B.Tech II Sem

o The request/grant response sequence contains a series of three pulses. The request/grant
pins are checked at each rising pulse of clock input.
o When a request is detected and if the conditions for HOLD request are satisfied, the
processor issues a grant pulse over the RQ/GT pin immediately during T4 (current) or T1
(next) state.
o When the requesting master receives this pulse, it accepts the control of the bus; it sends a
release pulse to the processor using RQ/GT pin.

Read Cycle

1.8 Interrupts of 8086

Interrupts is to break the sequence of operation. While the CPU is executing a program, on
interrupt breaks the normal sequence of execution of instructions, diverts its execution to some
other program called Interrupt Service Routine (ISR).After executing ISR , the control is
transferred back again to the main program.
Interrupts are particularly useful when interfacing I/O devices that provide or require data at
relatively low data transfer rate.
There are two types of Interrupts in 8086. They are:
1. Hardware Interrupts
2. Software Interrupts
1. Hardware Interrupts (External Interrupts). The 8086 microprocessors support hardware
interrupts through:
Two pins that allow interrupt requests, INTR and NMI
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Microprocessors and Microcontrollers III B.Tech II Sem

One pin that acknowledges, INTA, the interrupt requested on INTR.
INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of the
POPF instruction.
When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing
routine should return with the IRET instruction.
NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.
Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location
0008h. This interrupt has higher priority than the maskable interrupt.
2. Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be caused
by:
INT instruction - breakpoint interrupt. This is a type 3 interrupt.
INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
INTO instruction - interrupt on overflow
Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the
CPU processes this interrupt it clears TF flag before calling the interrupt processing routine.
Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode
(type 7).
Software interrupt processing is the same as for the hardware interrupts.
Ex: INT n (Software Instructions)
Control is provided through:
IF and TF flag bits
IRET and IRETD

27 Ravindranath M, Asst.Prof, Tirumala Engineering College