AP9213 ADVANCED

MICROPROCESSORS AND
MICROCONTROLLERS
UNIT II
HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM

Intel x86 Microprocessors

Intel introduced the 8086 microprocessor in 1978/79

8086, 8088, and 80186 processors
 16-bit processors with 16-bit registers
 16-bit data bus and 20-bit address bus
 Physical address space = 220 bytes = 1 MB

 Uses segmentation and real-address mode to address memory

 Each segment can address 216 bytes = 64 KB

 8088 is a less expensive version of 8086 [IBM PC]

 Uses an 8-bit data bus

 80186 is a faster version of 8086

8086/88 - 29k Transistors

Intel x86 Microprocessors..

80286 was introduced in 1982
 24-bit address bus 224 bytes = 16 MB address space [IBM PC/AT]
 Introduced protected mode

80286 - 130k Transistors

 Segmentation in protected mode is different from the real mode

80386 was introduced in 1985

 First 32-bit processor with 32-bit general-purpose registers
 First processor to define the IA-32 architecture
 32-bit data bus and 32-bit address bus
 232 bytes 4 GB address space
 Introduced paging, virtual memory, and the flat memory model
 Segmentation can be turned off

80386 - 375k Transistors

Intel x86 Microprocessors..

80486 was introduced 1989
 Improved version of Intel 80386
 On-chip Floating-Point unit (DX versions)
 On-chip unified Instruction/Data Cache (8 KB)

80486 1.2M Transistors

 Uses Pipelining: can execute up to 1 instruction per clock cycle

Pentium (80586) was introduced in 1993

 Wider 64-bit data bus, but address bus is still 32 bits
 Two execution pipelines: U-pipe and V-pipe
 Superscalar performance: can execute 2 instructions per clock cycle

 Separate 8 KB instruction and 8 KB data caches

80586 3.1M Transistors

 MMX instructions (later models) for multimedia applications

Pentium CPU Architecture

32bit processor

Separate 8Kb code and 8Kb data cache

32 bit address bus

64 bit data bus

Ten 32-bit registers
 EAX, EBX, ECX, EDX, ESI, EDI,
EBP, ESP, EIP & EFlag

Six 16-bit registers

 CS,SS,DS,ES,FS,GS

Parallel Integer Execution units

 U-pipeline and V-pipeline

Enhanced Floating point unit

Pentium CPU Architecture

Standard general purpose registers
EAX, EBX, ECX, and EDX - Each has special jobs in certain arithmetic instructions
32-bit General-Purpose Registers

Specialized uses of Registers

EAX Accumulator register

EAX
EBX

EBP

ECX

ESI

EDX

EDI

Automatically used by multiplication and division instructions

ECX Counter register

Automatically used by LOOP instructions

16-bit Segment Registers

EFLAGS
EIP

ESP Stack Pointer register

Used by PUSH and POP instructions, points to top of stack

ESI and EDI Source Index and Destination Index register

Used by string instructions

EBP Base Pointer register

Used to reference parameters and local variables on the stack

ESP

CS

ES

SS

FS

DS

GS

Pentium CPU Architecture

Pentium CPU Architecture

IOPL (I/O privilege level)
IOPL is used in protected mode operation to select the privilege level for I/O devices. Note that an IOPL of 00 is the
highest or most trusted: if IOPL is 11, it is the lowest or least trusted.

NT (nested task)
The nested task flag indicates that the current task is nested within another task in protected mode operation.

RF (resume)
The resume flag is used with debugging to control the resumption of execution after the next instruction.

VM (virtual mode)
The VM flag bit selects virtual mode operation in a protected mode system. A virtual mode system allows multiple DOS
memory partitions that are 1M byte in length to coexist in the memory system. Essentially, this allows the system
program to execute multiple DOS programs.

Pentium CPU Architecture

AC (alignment check)
The alignment check flag bit activates if a word or doubleword is addressed on a non-word or nondoubleword boundary. That is primarily used by its companion numeric coprocessor, for synchronization.

VIF (virtual interrupt flag)

The VIF is a copy of the interrupt flag bit available to the Pentium-Pentium II microprocessors.

VIP (virtual interrupt pending)

VIP provides information about a virtual mode interrupt for the Pentium-Pentium II microprocessors. This is
used in multitasking environments to provide the operating system with virtual interrupt flags and interrupt
pending information.

ID (identification)
The ID flag indicates that the Pentium-Pentium II microprocessors support the CPUID instruction.

Pentium Pin Dgm

Pentium
processor (510/60,
567/66)

Unused active LOW inputs should

be connected to VCC.
Unused active HIGH inputs should
be connected to GND.
No Connect (NC) pins must remain
unconnected.

Pentium Pin Dgm

Address.
Data.
Clock.
Bus.
Test.
Interrupt.
Cache.
Error.
Initialization.

Pentium Pin Dgm

Address A3 to A31 (Address Bus), AP (Address Parity), PEN (Parity Enable)
Data D0 to D63 (Data Bus), BE0 to BE7 (Bus Enable), DP0 to DP7 (Data Parity)
Clock.
Bus.
Test.
Interrupt.
Cache.
Error.
Initialization.
Branch Trace (BT0-BT3).

FEATURES
The Pentium processor achieves higher performance than the fastest Intel486 processor by
making use of the following advanced technologies.
SUPERSCALAR EXECUTION: The Intel486 processor can execute only one instruction at a time.
With superscalar execution, the Pentium processor can sometimes execute two instructions
simultaneously.
PIPELINE ARCHITECTURE: Like the Intel486 processor, the Pentium processor executes
instructions in five stages. This staging, or pipelining, allows the processor to overlap multiple
instructions so that it takes less time to execute two instructions in a row. Because of its
superscalar architecture, the Pentium processor has two independent processor pipelines.
INSTRUCTION OPTIMIZATION: The Pentium processor has been optimized to run critical
instructions in fewer clock cycles than the Intel486 processor.
FLOATING-POINT OPTIMIZATION: The Pentium processor executes individual instructions
faster through execution pipelining, which allows multiple floating-point instructions to be
executed at the same time.
PENTIUM EXTENSIONS: The Pentium processor has fewer instruction set extensions than the
Intel486 processors. The Pentium processor also has a set of extensions for multiprocessor (MP)
operation. This makes a computer with multiple Pentium processors possible.

ADDRESSING MODES
The way to accessing the operands in a instruction is
called addressing mode.
Types :
Register, Data, Memory & I/O.
Effective Address = base reg + (index reg * scaling factor) + disp
Where,
base reg is EAX, EBX, ECX, EDX or ESP or EBP;
index reg is EDI or ESI;
scaling factor is 1, 2, 4, or 8 .

Addressing Modes
REGISTER MODE:
Both operands are registers in a instruction.
Eg: MOV EAX,ECX
Both operands use register mode. The contents of register
ECX is copied to register EAX.

IMMEDIATE MODE :
The source operand is immediate data.
Eg: MOV EAX, 12345678
The second operand uses immediate mode. It is copied to
register EAX.

Addressing Modes
DIRECT MODE :
The Effective address is in the instruction.
Eg: MOV EAX, m_addr
The second operand uses direct mode. The instruction
contains the effective address. The contents of memory at the
effective address are copied into register EAX.
REGISTER INDIRECT MODE :
The effective address is in a register.
Eg: MOV EAX, [EBP]
The second operand uses register indirect mode. The contents
of register EBP is the effective address. The contents of
memory at the effective address are copied into register EAX.

Addressing Modes
BASE DISPLACEMENT MODE :
The effective address is the sum of a constant and the contents of a register.
Eg: MOV EAX, [EBP + 4000]
The second operand uses base displacement mode. The instruction contains
a constant. That constant is added to the contents of register EBP to form an
effective address. The contents of memory at the effective address are copied
into register EAX.
INDEX DISPLACEMENT MODE:
The effective address is the sum of a constant and the contents of a register.
Eg: MOV EAX,[ESI+4000]
The second operand uses base displacement mode. The instruction contains
a constant. That constant is added to the contents of register ESI to form an
effective address. The contents of memory at the effective address are copied
into register EAX.

Addressing Modes
BASE INDEXED MODE:
The effective address is the sum of the contents of two registers.
Eg: MOV EAX, [EBP][ESI]
The contents of registers EBP and ESI are added to form an effective
address. The contents of memory at the effective address are copied into
register EAX.
RELATIVE BASED INDEXED MODE :
The effective address is the sum of a constant and the contents of registers.
Eg: MOV EAX, [EBP] [ESI + 4000]
The second operand uses base displacement mode. The instruction contains
a constant. That constant is added to the contents of registers ESI & EBP to
form an effective address. The contents of memory at the effective address
are copied into register EAX.

Addressing Modes
INTRA SEGMENT INDIRECT:
INTRA SEGMENT DIRECT :
INTER SEGMENT INDIRECT:
INTER SEGMENT DIRECT :
DIRECT I/O:
INDIRECT I/O:
IMPLIED / IMPLICIT / INHERENT:

INSTRUCTION SETS
Instruction set is divided into 9 categories of operations. In addition to
commonly available instructions, high level language support and operating
system support.
An instruction may have 0-3 operands and the operand can be 8, 16, or 32bits long.
handles various types of data such as Single bit, string of bits, signed and
unsigned 8, 16, 32 and 64 bit data, ASCII character and BCD numbers.

Integer Arithmetic
Logical Arithmetic
Floating Point Arithmetic
I/O
Control Instructions

Instruction Sets
Many of the instructions have exactly 2 operands. If there are 2 operands,
then one of them will be required to use register mode, and the other will
have no restrictions on its addressing mode.
There are most often ways of specifying the same instruction for 8-, 16-, or
32-bit operands.

INSTRUCTION

FUNCTION

CMPXCHG

Compare and exchange 88-bytes

CPUID

Return CPU identification code

RDTSC

Read time
time--stamp counter

RDMSR/WRMSR

Read/Write model
model--specific register

RSM

Return from system management interrupt

OPERATING MODES
PROTECTED MODE:
This is the native state of the microprocessor. In this mode all instructions and architectural features
are available, providing the highest performance and capability. This is the recommended mode that all
new applications and operating systems should target.
Among the capabilities of protected mode is the ability to directly execute "real-address mode" 8086
software in a protected, multi-tasking environment. This feature is known as Virtual-8086 "mode" (or
"V86 mode").
REAL-ADDRESS MODE:
This mode provides the programming environment of the Intel 8086 processor, with a few extensions.
Reset initialization places the processor in real mode where, with a single instruction, it can switch to
protected mode.
SYSTEM MANAGEMENT MODE:
The Pentium microprocessor also provides support for System Management Mode (SMM). SMM is a standard
architectural feature unique to all new Intel microprocessors, beginning with the Intel386 SL processor, which
provides an operating-system and application independent and transparent mechanism to implement system
power management. SMM is entered through activation of an external interrupt pin (SMI#), which switches
the CPU to a separate address space while saving the entire context of the CPU. SMM-specific code may then
be executed transparently.

Bus Operations

Bus Cycle Encodings

Bus Operations

Special Bus Cycle

Bus Operations

Bus State Transitions

Bus Operations

Bus Operations

Bus Operations

PIPELINING

Pipelining

Branch Prediction

BTB Branch Target Buffer, a special Cache stores the inst and target addr of any branch inst

Floating--Point Unit
Floating

Floating--Point Unit
Floating
Unit

Floating--Point Unit
Floating
Unit

SEGMENTATION

Segmentation

Segmentation

Segmentation

Segmentation

Segmentation

PAGING

Paging

Paging

TLB Translation Look-aside Buffers

Paging

MULTITASKING

Multitasking

Multitasking

Multitasking

Multitasking

Multitasking

EXCEPTIONS and INTERRUPTS

Exceptions & Interrupts

Exceptions & Interrupts

Exceptions & Interrupts

Exceptions & Interrupts