Lecture 01

EEE 425/591: Digital Systems and Circuits
L-1: Introduction
Fall 2014, ASU

Yu (Kevin) Cao, [email protected], GWC 336
Highlight
Course orientation
Objective, textbook, and grading
VLSI design evolution

History, today, and tomorrow
Integration and abstraction
Key design metrics:

Area, performance, power, reliability, and cost
Challenges and trend for nanoscale design

Reading: Chapter 1
Handout: the syllabus and tentative schedule
EEE425/591, ASU, Y. Cao
Lecture 01
-2-
Basic Information
Instructor: Y. Kevin Cao, GWC 336
Office hours: M/W, 1:30pm-2:30pm; E-mail: [email protected]
Teaching Assistants (Lab at GWC 273):

Office TA (GWC 303): David Ganger ([email protected]),
Tu: 4-5pm, Th/F: 1:30-2:30pm

Lab TAs (GWC 273): David Ganger ([email protected]), Sankalp Jain
([email protected]), Mengbing Liang ([email protected]), Curtis
Mackay ([email protected]), Gaurav Singla ([email protected]),
Mahraj Sivaraj ([email protected])
Textbook:
Digital Integrated Circuits: A Design Perspective, by Jan M. Rabaey, et al.
(http://bwrc.eecs.berkeley.edu/IcBook/)
Other references:
CMOS VLSI Design: A Circuits and Systems Perspective, by Neil H. E. Weste and
David Harris
Logical Effort: Designing Fast CMOS Circuits, by Ivan Sutherland, Robert F. Sproull,
David Harris
Lectures, notes etc. are available at http://my.asu.edu

Lecture 01
-3-
What will you learn

Digital IC design knowledge that is both fundamental and practical,
in the context of key design principles
Pre-requisite: basic understanding of circuits and logic (ECE 334)

Schedule:
Design metrics
Fundamental
Practical
CMOS, interconnect
logic, memory,
cost, performance,
clock, power
power, and reliability
Further study: Silicon technology, analog design, computer
architecture and CAD
Lecture 01
-4-
Assignment and Exams

Homework (12%): exercise your learning
Once every two weeks (6 totally)
Labs (20%): practice the design and tools

5 software labs, using 32nm PDK
Lab 4&5 are combined as a mini design project
Online students: remote login available
Examination: evaluate your knowledge

Two mid-terms (20% each): design fundamentals
Final (28%) on December 3rd
All closed book with one page of cheatsheet
Lecture 01
-5-
Grading Policy
Letter grade depends on the relative distribution, with
+ and (: average; : standard deviation)
EEE 425 (undergraduate)*
EEE 591 (graduate)
A+: top 10%
A+: top 10%
A: > +
A: > + 0.5
A-: > + 0.5
A-: >
B+: >
B+: > 0.5
B: > 0.5
B: >
B-: >
B-: > 1.5
C: > 1.5
C: > 2
D: > 2
*The baseline of 425 will be reviewed later in the semester

Lecture 01
-6-
Highlight
Course information
Textbook, materials, project, and grading

Key design metrics:

Challenges and trend for nano-VLSI

Reading: Chapter 1
Lecture 01
-7-
The First Computing System

Abacus
(3000 B.C. 300 A. D.)
by Chinese
and Mesoamerican
Size: > 10cm
Speed: your finger-run
Power: no sweating
Cost: home made
Lecture 01
-8-
The First Computer

The Babbage Difference Engine
(1832)
Designed by Charles Babbage
Size: 11 feet long, 7 feet tall,
25,000 parts
Speed: mechanical
Power: mechanical
Cost: 17,470
Lecture 01
-9-
The First Electronic Computer

ENIAC
(1946)
by U.S.A.
Size: 1800 ft2
Speed: 40 div./sec.
Power: 160kW
Cost: $486, 804.22
Lecture 01
- 10 -
The First Transistor: A Revolution

Transistor
(1948)
by Bell Labs
Nobel Prize, 1951
Shockley, Bardeen,
and Brattain
Much better scalability and reliability
Lecture 01
- 11 -
The First Integrated Circuit

Integrated Circuit
(1958)
by TI
Nobel Prize, 2000
Kilby
1 transistor, 3 resistors, and 1 capacitor
Lecture 01
- 12 -
The First Microprocessor Chip

4004 CPU
(1971)
by Intel
Size: ~ 9mm2,
2.3 K transistors @10m
Speed: 1MHz
Design team: 3
Lecture 01
- 13 -
The Pentium 4 CPU

MOSFET
Interconnect
P4 CPU (2002)
Size: ~217mm2, 42M @ 0.18m
Speed: 2GHz
Design team: 1000
Lecture 01
- 14 -
The Cell Processor

Used MOSFET
in PS3 and other
applications
8 processor cores
Low-power and highspeed
Cell BE (2006)
Size: ~221mm2, 234M @ 90nm
Speed: 4GHz
Design team: STIR
Lecture 01
- 15 -
Moores Law
In 1965, Gordon Moore (Intel) noted that the number of
transistors on a chip doubled every 18 to 24 months.
Prediction: semiconductor technology will double its

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Electronics,
1975
1974
1973
1972
1971
1970
1969
1968
1967
1966
1965
1964
1963
1962
1961
1960
April 19, 1965

1959
LOG2 OF THE NUMBER OF

COMPONENTS PER INTEGRATED FUNCTION
effectiveness every 18 months
Lecture 01
- 16 -
Moores Law in Microprocessors

Year
Transistors
1980
1990
2000
2010
Chip
Frequency
(Hz)
3.2G
1000M
100M
Itanium
10M
1.0G
Pentium
1M
80386
100K
8086
Technology
Node
200M
33M/ 2 years
Transistor counts: 2x
Channel length: 0.7 5M

/ 18 months
3.0m 1.0m 0.35m 180nm
50nm
Lecture 01
- 17 -
Lecture 01
- 18 -
Evolution in Complexity
Driving Forces
Technology scaling
Semiconductor device shrinks by 0.7x / generation
Circuit and design

Cleverness
Functions per chip doubles every generation;
chip cost does not increase significantly
Cost of a function decreases by 2x
On the other hand:

Design population does not double every two years
Productivity per designer decreases due to
complexities of design and team management

Lecture 01
- 19 -
10,000
10,000,000
100,000
100,000,000
Logic Tr./Chip
Tr./Staff Month.
1,000
1,000,000
Source: Sematech
10,000
10,000,000
100
100,000
Productivity
(K) Trans./Staff - Mo.
Complexity
Logic Transistor per Chip (M)
Productivity Trends
1,000
1,000,000
58%/Yr. compounded
Complexity growth rate
10
10,000
100
100,000
1,0001
10
10,000
x
0.1
100
xx
0.01
10
xx
x
1
1,000
21%/Yr. compound
Productivity growth rate
0.1
100
0.01
10
2009
2007
2005
2003
2001
1999
1997
1995
1993
1991
1989
1987
1985
1983
1981
0.001
1
Profound impact on the way VLSI is designed

Exploit different levels of abstraction
Automated design with CAD tools
Lecture 01
- 20 -
10
Design Abstraction Levels

SYSTEM
MODULE
+
GATE
CIRCUIT
DEVICE
G
D
S
n+
n+
Lecture 01
- 21 -
Top-Down Design Automation

systems
systems
application software
system software
Outp
ut
M2
k
T
h=
3;
k = h; h
>3;
M1
h<
3;
sapchg#
platform / architecture
circuits
LA TC H
s a b it
s a b it #
devices/interconnect
structures
structures
materials
materials
physics
physics
Tool capability is limited and exploited

by our physical understanding
Lecture 01
- 22 -
11
Highlight
Course orientation
Objective, textbook, project, and grading

Key design metrics:

Challenges and trend for nano-VLSI

Reading: Chapter 1
Lecture 01
- 23 -
Design Adaptation
speed
area/cost
1970s
speed
speed/power
/reliability
speed/power
power
low power
1980s
1990s
reliable ultralow power

2000s
Lecture 01
- 24 -
12
Challenges in Future VLSI

Macroscopic Issues
Microscopic Problems
Time-to-Market
Millions of Gates
High-Level Abstractions
Reuse & IP: Portability
Predictability
Ultra-high speed design

Interconnect
Noise, Crosstalk
Reliability, Manufacturability
Power Dissipation
Clock distribution
Main roadblocks: power, cost, and reliability
Lecture 01
- 25 -
Power Dissipation
18KW
5KW
1.5KW
Power (Watts)
104
500W
103
Pentium proc
102
103
102
Power (W)
105
486
8086 386
8080
10
Switching
101
100
10-1
10-2
10-3
1 4004
Source: Intel
Leakage
10-4
10m
0.1
1971 1974 1978 1985 1992 2000 2004 2008
1m
100nm
10nm
Technology node
Year
Power delivery and dissipation will be prohibitive

Courtesy, Intel
Lecture 01
- 26 -
13
Power Density
Power/transistor switching goes down with
technology scaling, but:
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
Hot Plate
10
8086
4004
8008 8085
1
1970
P6
Pentium
386
286
486
8080
1980
1990
2000
2010
Source: Intel
Year
Lecture 01
- 27 -
Innovative Design Demanded

Module Heat Flux (w/cm2)
14
IBM ES9000
12
Bipolar
CMOS
10
8
Fujitsu VP2000
IBM 3090S
NTT
IBM RY5
IBM RY7
Fujitsu M-780
IBM3090
CDC Cyber 205
IBM4381
IBM3084
IBM370 Fujitsu
IBM360
IBM3033 M380
Pulsar
IBM RY6
IBM RY4
Apache
Pentium II
0
1950
1960
1970
1980
1990
2000
2010
Year of Announcement
Technology used to be the answer for this

trouble; but, no candidate around the corner
Lecture 01
- 28 -
14
Reliability
Process variations
Dynamic uncertainties:
Temperature
Power supply (Ldi/dt noise)
138 W/cm2
Crosstalk
Soft error
All degrade your yield

and waste resource
Lecture 01
- 29 -
Cost of Integrated Circuits

NRE (non-recurrent engineering), i.e., fixed costs
Design time and effort
Mask generation
Design verification
Recurrent costs, i.e., Proportional cost

Silicon processing (proportional to chip area)
Packaging (proportional to volume)
Test (proportional to volume)
EEE425/591, ASU
Lecture 01
- 30 -
15
NRE Cost
EEE425/591, ASU
Lecture 01
- 31 -
Recurrent Cost
Cost per Transistor
10-4
10-5
Dollar
10-6
10-7
10-8
10-9
1m
EEE425/591, ASU
100nm
10nm
Lecture 01
- 32 -
16
Design Trend I: Integration

Integrate various technologies
Integral design solutions
Small
Signal RF
Power
RF
Power
Management
Analog
Baseband
Digital Baseband
(DSP + MCU)
Lecture 01
- 33 -
Design Trend II: Parallelism

Concurrency for better
reliability, programmability,
and cost factor
Examples:
Multiple chip
Array structure
Lecture 01
- 34 -
17
Broader Applications
Digital IC have come a long way and still have
quite some potential left for the coming
decades:
Computation and Communications
Automobile (30-70 chips/car now)
Consumer electronics
Energy conservation
Security and intelligence
Biomedical
Much more with your innovation
Lecture 01
- 35 -
Summary
EEE 425/591: digital design fundamentals and
practices underlying VLSI systems
Design metrics: timing, power, and reliability

Challenges ahead: power and reliability
Clear understanding from a circuit perspective
Office hours: M/W 1:30pm-2:30pm, GWC 336
Contact: [email protected],
Web access: http://my.asu.edu
Lecture 01
- 36 -
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EEE 425/591: Digital Systems and Circuits

Fall 2014, ASU

VLSI design evolution

Key design metrics:

Challenges and trend for nanoscale design

Teaching Assistants (Lab at GWC 273):

Tu: 4-5pm, Th/F: 1:30-2:30pm

Lectures, notes etc. are available at http://my.asu.edu

What will you learn

Pre-requisite: basic understanding of circuits and logic (ECE 334)

Assignment and Exams

Labs (20%): practice the design and tools

Examination: evaluate your knowledge

EEE 591 (graduate)

A+: top 10%

A+: top 10%

A-: > + 0.5

B+: > 0.5

B-: > 1.5

*The baseline of 425 will be reviewed later in the semester

VLSI design evolution

Key design metrics:

Challenges and trend for nano-VLSI

The First Computing System

The First Computer

The First Electronic Computer

EEE425/591, ASU, Y. Cao

The First Transistor: A Revolution

The First Integrated Circuit

EEE425/591, ASU, Y. Cao

The First Microprocessor Chip

EEE425/591, ASU, Y. Cao

The Pentium 4 CPU

The Cell Processor

Prediction: semiconductor technology will double its

EEE425/591, ASU, Y. Cao

April 19, 1965

LOG2 OF THE NUMBER OF

effectiveness every 18 months

Moores Law in Microprocessors

Channel length: 0.7 5M

3.0m 1.0m 0.35m 180nm

EEE425/591, ASU, Y. Cao

EEE425/591, ASU, Y. Cao

Circuit and design

On the other hand:

complexities of design and team management

Profound impact on the way VLSI is designed

Design Abstraction Levels

EEE425/591, ASU, Y. Cao

Top-Down Design Automation

Tool capability is limited and exploited

VLSI design evolution

Key design metrics:

Challenges and trend for nano-VLSI

EEE425/591, ASU, Y. Cao

reliable ultralow power

Challenges in Future VLSI

Ultra-high speed design

Main roadblocks: power, cost, and reliability