61145L

PIC32
PIC32 Flash Programming Specification

1.0
DEVICE OVERVIEW
This document defines the programming specification

for the PIC32 families of 32-bit microcontrollers. This
programming specification is designed to guide
developers of external programmer tools. Customers
who are developing applications for PIC32 devices
should use development tools that already provide
support for device programming.
An external tool programming setup consists of an

external programmer tool and a target PIC32 device.
Figure 2-1 illustrates the block diagram view of the
typical programming setup. The programmer tool is
responsible for executing necessary programming
steps and completing the programming operation.
FIGURE 2-1:
The major topics of discussion include:
Section 1.0 Device Overview

Section 2.0 Programming Overview
Section 3.0 Programming Steps
Section 4.0 Connecting to the Device
Section 5.0 EJTAG vs. ICSP
Section 6.0 Pseudo Operations
Section 7.0 Entering 2-Wire Enhanced ICSP Mode
Section 8.0 Check Device Status
Section 9.0 Erasing the Device
Section 10.0 Entering Serial Execution Mode
Section 11.0 Downloading the Programming Executive (PE)
Section 12.0 Downloading a Data Block
Section 13.0 Initiating a Flash Row Write
Section 14.0 Verify Device Memory
Section 15.0 Exiting Programming Mode
Section 16.0 The Programming Executive
Section 17.0 Checksum
Section 18.0 Configuration Memory and Device ID
Section 19.0 TAP Controllers
Section 20.0 AC/DC Characteristics and Timing Requirements
Appendix A: PIC32 Flash Memory Map
Appendix B: Hex File Format
Appendix C: Revision History
PROGRAMMING SYSTEM
SETUP
Target PIC32 Device
External
Programmer
CPU
On-Chip Memory
2.1
Devices with Dual Flash Panel and

Dual Boot Regions
Self-programming
External tool programming
The PIC32MZ Embedded Connectivity (EC) family of

devices incorporate several features useful for field
(self) programming of the device. These features
include dual Flash panels with dual Boot regions, an
aliasing scheme for the Boot regions allowing automatic selection of Boot code at start-up and a panel
swap feature for program Flash. The two Flash panels
and their associated Boot regions can be erased and
programmed separately. Refer to Section 3. Memory
Organization (DS61115) in the PIC32 Family
Reference Manual for a detailed explanation of these
features.
The self-programming method requires that the target

device already contains executable code with the logic
necessary to complete the programming sequence.
A development tool used for production programming

will not be concerned about most of these features with
the following exceptions:
The external tool programming method does not

require any code in the target device it can program
all target devices with or without any executable code.
Insuring that the SWAP bit (NVMCON<7>) is in the

proper setting. The default setting is 0 for no swap
of panels. The development tool should assume the
default setting when generating source files for the
programming tool.
Proper handling of the aliasing of the Boot memory
in the checksum calculation. The aliased sections
will be duplicates of the fixed sections. See
Section 17.0 Checksum for more information on
checksum calculations with aliased regions.
2.0
PROGRAMMING OVERVIEW
All PIC32 devices can be programmed through two

primary methods:
This document describes the external tool

programming method. Refer to the individual sections
of the PIC32 Family Reference Manual and the
specific device data sheet for more information about
using the self-programming method.
2007-2013 Microchip Technology Inc.
DS61145L-page 1
PIC32
2.2
Programming Interfaces
All PIC32 devices provide two physical interfaces to the

external programmer tool:
2-wire In-Circuit Serial Programming (ICSP)
4-wire Joint Test Action Group (JTAG)
See Section 4.0 Connecting to the Device for
more information.
Either of these methods may use a downloadable
Programming Executive (PE). The PE executes from
the target device RAM and hides device programming
details from the programmer. It also removes overhead
associated with data transfer and improves overall data
throughput. Microchip has developed a PE that is
available for use with any external programmer (see
Section 16.0 The Programming Executive for
more information).
2.3
Enhanced JTAG (EJTAG)
The 2-wire and 4-wire interfaces use the EJTAG

protocol to exchange data with the programmer. While
this document provides a working description of this
protocol as needed, advanced users are advised to
refer to the EJTAG Specification (MD00047), which is
available
from
MIPS
Technologies,
Inc.
(www.mips.com).
2.4
Data Sizes
Per the EJTAG Specification, data sizes are defined as

follows:
One Word: 32 bits

One-half Word: 16 bits
One-quarter Word: 8 bits
One Byte: 8 bits
Section 3.0 Programming Steps describes highlevel programming steps, followed by a brief
explanation of each step. Detailed explanations are
available in corresponding sections of this document.
More information on programming commands, EJTAG,
and DC specifications are available in the following
sections:
Section 18.0 Configuration Memory and
Device ID
Section 19.0 TAP Controllers
Section 20.0 AC/DC Characteristics and
Timing Requirements
DS61145L-page 2
PIC32
3.0
PROGRAMMING STEPS
All tool programmers must perform a common set of

steps, regardless of the actual method being used.
Figure 3-1 shows the set of steps to program PIC32
devices.
FIGURE 3-1:
The following sequence lists the steps, with a brief

explanation of each step. More detailed information
about the steps is available in the following sections.
1.
Connect to the Target Device.

To ensure successful programming, all required
pins must be connected to appropriate signals.
See Section 4.0 Connecting to the Device
in this document for more information.
PROGRAMMING FLOW
2.
Start
Place the Target Device in Programming Mode.

For 2-wire programming methods, the target
device must be placed in a special programming
mode (Enhanced ICSP) before executing any
other steps.
Enter Enhanced ICSP

(Only required for 2-wire)
Note:
For the 4-wire programming methods,

Step 2 is not required.
See Section 7.0 Entering 2-Wire Enhanced

ICSP Mode for more information.
Check Device Status
3.
Check the Status of the Device.

Step 3 checks the status of the device to ensure
it is ready to receive information from the
programmer.
Erase Device
See Section 8.0 Check Device Status for

more information.
Enter Serial Exec Mode
4.
If the target memory block in the device is not

blank, or if the device is code-protected, an
erase step must be performed before
programming any new data.
Download the PE
(Optional)
See Section 9.0 Erasing the Device for

more information.
5.
Download a Data Block
See Section 10.0 Entering Serial Execution

Mode for more information.
6.
Done
Enter Programming Mode.

Step 5 verifies that the device is not codeprotected and boots the TAP controller to start
sending and receiving data to and from the
PIC32 CPU.
Initiate Flash Write
No
Erase the Target Device.
Download the Programming Executive (PE).

The PE is a small block of executable code that
is downloaded into the RAM of the target device.
It will receive and program the actual data.
Yes
Note:
Verify Device
Exit Programming Mode
If the programming method being used

does not require the PE, Step 6 is not
required.
See
Section 11.0
Downloading
the
Programming Executive (PE) for more
information.
Done
DS61145L-page 3
PIC32
7.
Download the Block of Data to Program.

All methods, with or without the PE, must download the desired programming data into a block
of memory in RAM.
See Section 12.0 Downloading a Data
Block for more information.
8.
Initiate Flash Write.

After downloading each block of data into RAM,
the programming sequence must be started to
program it into the target devices Flash
memory.
See Section 13.0 Initiating a Flash Row
Write for more information.
9.
Repeat Steps 7 and 8 until all data blocks are

downloaded and programmed.
DS61145L-page 4
10. Verify the program memory.

After all programming data and Configuration
bits are programmed, the target device memory
should be read back and verified for the
matching content.
See Section 14.0 Verify Device Memory for
more information.
11. Exit the Programming mode.
The newly programmed data is not effective until
either power is removed and reapplied to the
target device or an exit programming sequence
is performed.
See Section 15.0 Exiting
Mode for more information.
Programming
PIC32
4.0
CONNECTING TO THE DEVICE
The PIC32 family provides two possible physical

interfaces for connecting to and programming the
memory contents (Figure 4-1). For all programming
interfaces, the target device must be properly powered
and all required signals must be connected. In addition,
the interface must be enabled, either through its
Configuration bit, as in the case of the JTAG 4-wire
interface, or though a special initialization sequence, as
is the case for the 2-wire ICSP interface.
The JTAG interface is enabled by default in blank
devices shipped from the factory.
Enabling ICSP is described in Section 7.0 Entering
2-Wire Enhanced ICSP Mode.
FIGURE 4-1:
TCK Test Clock Input

TMS Test Mode Select Input
TDI Test Data Input
TDO Test Data Output
These signals are described in the following four

sections. Refer to the specific device data sheet for the
connection of the signals to the device pins.
TEST CLOCK INPUT (TCK)
TCK is the clock that controls the updating of the TAP

controller and the shifting of data through the Instruction or selected Data register(s). TCK is independent of
the processor clock with respect to both frequency and
phase.
2-wire
ICSP
Programmer
4-wire Interface
One possible interface is the 4-wire JTAG (IEEE

1149.1) port. Table 4-1 lists the required pin
connections. This interface uses the following four
communication lines to transfer data to and from the
PIC32 device being programmed:
4.1.1
PROGRAMMING
INTERFACES
PIC32
OR
4.1
4-wire
JTAG
4.1.2
TEST MODE SELECT INPUT (TMS)
TMS is the control signal for the TAP controller. This

signal is sampled on the rising edge of TCK.
+ MCLR, VDD, VSS
4.1.3
TEST DATA INPUT (TDI)
TDI is the test data input to the Instruction or selected

Data register(s). This signal is sampled on the rising
edge of TCK for some TAP controller states.
4.1.4
TEST DATA OUTPUT (TDO)
TDO is the test data output from the Instruction or Data

register(s). This signal changes on the falling edge of
TCK. TDO is only driven when data is shifted out,
otherwise the TDO is tri-stated.
TABLE 4-1:
4-WIRE INTERFACE PINS
Device Pin Name
Pin Type
Pin Description
MCLR
I
Programming Enable
ENVREG(2)
I
Enable for On-Chip Voltage Regulator
P
Power Supply
VDD and AVDD(1)
P
Ground
VSS and AVSS(1)
VCAP
P
CPU logic filter capacitor connection
TDI
I
Test Data In
TDO
O
Test Data Out
TCK
I
Test Clock
TMS
I
Test Mode State
Legend: I = Input
O = Output
P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground
(AVSS).
2: The ENVREG pin is not available on all devices. Please refer to the Pin Diagrams section in the
specific device data sheet to determine availability.
DS61145L-page 5
PIC32
4.2
2-wire Interface
4.2.1
Another possible interface is the 2-wire ICSP port.

Table 4-2 lists the required pin connections. This
interface uses the following two communication lines to
transfer data to and from the PIC32 device being
programmed:
PGECx Serial Program Clock
PGEDx Serial Program Data
TABLE 4-2:
Device
Pin Name
PGECx is the clock that controls the updating of the

TAP controller and the shifting of data through the
Instruction or selected Data register(s). PGECx is
independent of the processor clock, with respect to
both frequency and phase.
4.2.2
These signals are described in the following two

sections. Refer to the specific device data sheet for the
connection of the signals to the chip pins.
SERIAL PROGRAM CLOCK

(PGECX)
SERIAL PROGRAM DATA (PGEDX)
PGEDx is the data input/output to the Instruction or

selected Data Register(s), it is also the control signal
for the TAP controller. This signal is sampled on the
falling edge of PGECx for some TAP controller states.
2-WIRE INTERFACE PINS

Programmer
Pin Name
Pin Type
Pin Description
MCLR
MCLR
P
Programming Enable
N/A
I
Enable for On-Chip Voltage Regulator
ENVREG(2)
VDD and AVDD(1) VDD
P
Power Supply
P
Ground
VSS and AVSS(1) VSS
N/A
P
CPU logic filter capacitor connection
VCAP
PGEC1
PGEC
I
Primary Programming Pin Pair: Serial Clock
PGED1
PGED
I/O
Primary Programming Pin Pair: Serial Data
PGEC2
PGEC
I
Secondary Programming Pin Pair: Serial Clock
PGED2
PGED
I/O
Secondary Programming Pin Pair: Serial Data
Legend: I = Input
O = Output
P = Power
Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground (AVSS).
2: The ENVREG pin is not available on all devices. Please refer to either the Pin Diagrams or Pin
Tables section in the specific device data sheet to determine availability.
DS61145L-page 6
PIC32
4.3
Power Requirements
FIGURE 4-2:
Devices in the PIC32 family are dual voltage supply

designs. There is one supply for the core and
another for peripherals and I/O pins. All devices
contain an on-chip regulator for the lower voltage
core supply to eliminate the need for an additional
external regulator. There are three implementations
of the on board regulator:
The first version has an internal regulator that can
be disabled using the ENVREG pin. When disabled,
an external power supply must be used to power the
core. If enabled, a low-ESR filter capacitor must be
connected to the VCAP pin (see Figure 4-2).
The second version has an internal regulator that
cannot be disabled. A low-ESR filter capacitor must
always be connected to the VCAP pin.
The third version has an internal regulator that
cannot be disabled and does not require a filter
capacitor
INTERNAL REGULATOR
ENABLE/DISABLE
OPTIONS
Regulator Enabled(2)
(ENVREG tied to VDD)
3.3V
PIC32
VDD
ENVREG
VCAP
CEFC
(10 F typical)
VSS
Regulator Disabled(2)
(ENVREG tied to ground)
1.8V(1)
3.3V(1)
PIC32
VDD
Please refer to Section 20.0 AC/DC Characteristics

and Timing Requirements and the Electrical
Characteristics chapters in the specific device data
sheet for the power requirements for your device.
ENVREG
VCAP
VSS
Note 1:
These are typical operating voltages. Refer

to Section 20.0 AC/DC Characteristics and
Timing Requirements for the full operating
ranges of VDD and VCAP.
2:
Regulator Enabled and Regulator Disabled

mode are not available on all devices.
Please refer to the specific device data
sheet to determine availability.
DS61145L-page 7
PIC32
5.0
EJTAG vs. ICSP
Programming is accomplished through the EJTAG

module in the CPU core. EJTAG is connected to either
the full set of JTAG pins, or a reduced 2-wire to 4-wire
EJTAG interface for ICSP mode. In both modes,
programming of the PIC32 Flash memory is
accomplished through the ETAP controller. The TAP
Controller uses the TMS pin to determine if Instruction
or Data registers should be accessed in the shift path
between TDI and TDO (see Figure 5-1).
FIGURE 5-1:
The basic concept of EJTAG that is used for

programming is the use of a special memory area
called DMSEG (0xFF200000 to 0xFF2FFFFF), which
is only available when the processor is running in
Debug mode. All instructions are serially shifted into an
internal buffer, and then loaded into the Instruction
register and executed by the CPU. Instructions are fed
through the ETAP state machine in 32-bit groups.
TAP CONTROLLER
Tap Controller
TMS
TCK
TDO
TDI
Instruction, Data and Control Registers
DS61145L-page 8
PIC32
5.1
Programming Interface
Figure 5-2 shows the basic programming interface in

PIC32 devices. Descriptions of each interface block are
provided in subsequent sections.
FIGURE 5-2:
BASIC PIC32 PROGRAMMING INTERFACE BLOCK DIAGRAM
TMS
TCK
Common
ETAP
VDD
CPU
TDI
TDO
VSS
MTAP
Flash
Controller
MCLR
or
PGECx
PGEDx
5.1.1
2-wire
to
4-wire
ETAP
Flash
Memory
5.1.4
CPU
This block serially feeds instructions and data into the

CPU.
The CPU executes instructions at 8 MHz through the

internal oscillator.
5.1.2
5.1.5
MTAP
In addition to the EJTAG TAP (ETAP) controller, the

PIC32 device uses a second proprietary TAP controller
for additional operations. The Microchip TAP (MTAP)
controller supports two instructions relevant to
programming: MTAP_COMMAND and TAP switch
Instructions. See Table 19-1 for a complete list of
Instructions. The MTAP_COMMAND instruction provides
a mechanism for a JTAG probe to send commands to
the device through its Data register.
The programmer sends commands by shifting in the
MTAP_COMMAND instruction through the SendCommand
pseudo operation, and then sending MTAP_COMMAND
DR commands through XferData pseudo operation
(see Table 19-2 for specific commands).
The probe does not need to issue a MTAP_COMMAND
instruction for every command shifted into the Data
register.
5.1.3
2-WIRE TO 4-WIRE
This block converts the 2-wire ICSP interface to the

4-wire JTAG interface.
FLASH CONTROLLER
The Flash controller controls erasing and programming

of the Flash memory on the device.
5.1.6
FLASH MEMORY
The PIC32 device Flash memory is divided into two

logical Flash partitions consisting of the Boot Flash
Memory (BFM) and Program Flash Memory (PFM).
The BFM begins at address 0x1FC00000, and the PFM
begins at address 0x1D000000. Each Flash partition is
divided into pages, which represent the smallest block
of memory that can be erased. Depending on the
device, page sizes are 256 words (1024 bytes), 1024
words (4096 bytes), or 4096 words (16,384 bytes).
Row size indicates the number of words that are programmed with the row program command. There are
always 8 rows within a page; therefore, devices with
256, 1024, and 4096 word page sizes have 32, 128,
and 512 word row sizes, respectively. Table 5-1 shows
the PFM, BFM, Row, and Page size of each device
family.
The highest memory locations of the BFM are reserved
for the device Configuration registers (see
Section 18.0 Configuration Memory and Device
ID for details).
DS61145L-page 9
PIC32
TABLE 5-1:
CODE MEMORY SIZE
PIC32 Device
Row Size Page Size

(Words) (Words)
Boot Flash Memory Address

(Bytes)
Program Flash Memory Address

(Bytes)
PIC32MX110F016B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D003FFF (16 KB)
PIC32MX110F016C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D003FFF (16 KB)
PIC32MX110F016D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D003FFF (16 KB)
PIC32MX210F016B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D003FFF (16 KB)
PIC32MX210F016C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D003FFF (16 KB)
PIC32MX210F016D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D003FFF (16 KB)
PIC32MX120F032B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX120F032C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX120F032D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX220F032B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX220F032C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX220F032D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX320F032H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX420F032H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D007FFF (32 KB)
PIC32MX130F064B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX130F064C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX130F064D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX230F064B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX230F064C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX230F064D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX320F064H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX330F064H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX430F064H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX534F064H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX564F064H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX664F064H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX330F064L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX430F064L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX534F064L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX564F064L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX664F064L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D00FFFF (64 KB)
PIC32MX150F128B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX150F128C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX150F128D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX250F128B
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX250F128C
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX250F128D
32
256
0x1FC00000-0x1FC00BFF (3 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX320F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX340F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX350F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX440F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX450F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX564F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX664F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX764F128H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX320F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX340F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
DS61145L-page 10
PIC32
TABLE 5-1:
CODE MEMORY SIZE (CONTINUED)
PIC32 Device
Row Size Page Size

(Words) (Words)

(Bytes)

(Bytes)
PIC32MX350F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX440F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX450F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX564F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX664F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX764F128L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D01FFFF (128 KB)
PIC32MX340F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX350F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX440F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX450F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX575F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX675F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX775F256H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX350F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX360F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX450F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX460F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX575F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX675F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX775F256L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MX340F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX360F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX370F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX440F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX470F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX575F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX675F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX695F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX775F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX795F512H
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX360F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX370F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX460F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX470F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX575F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX675F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX695F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX775F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MX795F512L
128
1024
0x1FC00000-0x1FC02FFF (12 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0256ECE064
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECE100
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECE124
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECE144
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECF064
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECF100
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECF124
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
PIC32MZ0256ECF144
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D03FFFF (256 KB)
DS61145L-page 11
PIC32
TABLE 5-1:
CODE MEMORY SIZE (CONTINUED)
PIC32 Device
Row Size Page Size

(Words) (Words)

(Bytes)

(Bytes)
PIC32MZ0512ECE064
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECE100
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECE124
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECE144
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECF064
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECF100
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECF124
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ0512ECF144
512
4096
0x1FC00000-0x1FC13FFF (80 KB)
0x1D000000-0x1D07FFFF (512 KB)
PIC32MZ1024ECE064
512
4096
0x1FC00000-0x1FC13FFF (80 KB) 0x1D000000-0x1D0FFFFF (1024 KB)
PIC32MZ1024ECE100
512
4096
PIC32MZ1024ECE124
512
4096
PIC32MZ1024ECE144
512
4096
PIC32MZ1024ECF064
512
4096
PIC32MZ1024ECF100
512
4096
PIC32MZ1024ECF124
512
4096
PIC32MZ1024ECF144
512
4096
PIC32MZ1024ECG064
512
4096
PIC32MZ1024ECG100
512
4096
PIC32MZ1024ECG124
512
4096
PIC32MZ1024ECG144
512
4096
PIC32MZ1024ECH064
512
4096
PIC32MZ1024ECH100
512
4096
PIC32MZ1024ECH124
512
4096
PIC32MZ1024ECH144
512
4096
PIC32MZ2048ECG064
512
4096
PIC32MZ2048ECG100
512
4096
PIC32MZ2048ECG124
512
4096
PIC32MZ2048ECG144
512
4096
PIC32MZ2048ECH064
512
4096
PIC32MZ2048ECH100
512
4096
PIC32MZ2048ECH124
512
4096
PIC32MZ2048ECH144
512
4096
DS61145L-page 12
PIC32
5.2
4-wire JTAG Details
The 4-wire interface uses standard JTAG (IEEE

1149.1-2001) interface signals.
TCK: Test Clock drives data in/out

TMS: Test Mode Select selects operational mode
TDI: Test Data In data into the device
TDO: Test Data Out data out of the device
FIGURE 5-3:
Since only one data line is available, the protocol is

necessarily serial (like SPI). The clock input is at the
TCK pin. Configuration is performed by manipulating a
state machine bit by bit through the TMS pin. One bit of
data is transferred in and out per TCK clock pulse at the
TDI and TDO pins, respectively. Different instruction
modes can be loaded to read the chip ID or manipulate
chip functions.
Data presented to TDI must be valid for a chip-specific
setup time before, and hold time, after the rising edge
of TCK. TDO data is valid for a chip-specific time after
the falling edge of TCK (refer to Figure 5-3).
4-WIRE JTAG INTERFACE
TCK
TMS
TDI
iLSb
iMSb
TDO
oLSb
oMSb
DS61145L-page 13
PIC32
5.3
2-wire ICSP Details
of PGECx, while TDO is driven on the falling edge of

PGECx. The 4-phase ICSP mode is used for both read
and write data transfers.
In ICSP mode, the 2-wire ICSP signals are time

multiplexed into the 2-wire to 4-wire block. The 2-wire
to 4-wire block then converts the signals to look like a
4-wire JTAG port to the TAP controller.
5.3.2
In 2-phase ICSP mode, the TMS and TDI device pins

are multiplexed into PGEDx in two clocks (see
Figure 5-5). The LSb is shifted first; and TDI and TMS
are sampled on the falling edge of PGECx. There is no
TDO output provided in this mode. The 2-phase ICSP
mode was designed to accelerate 2-wire, write-only
transactions.
There are two possible modes of operation:

4-phase ICSP
2-phase ICSP
5.3.1
4-PHASE ICSP
In 4-phase ICSP mode, the TDI, TDO and TMS device

pins are multiplexed onto PGEDx in four clocks (see
Figure 5-4). The Least Significant bit (LSb) is shifted
first; and TDI and TMS are sampled on the falling edge
FIGURE 5-4:
2-PHASE ICSP
Note:
The packet is not actually executed until the

first clock of the next packet. To enter 2-wire,
2-phase ICSP mode, the TDOEN bit
(DDPCON<0>) must be set to 0.
2-WIRE, 4-PHASE
TCK
TMS
TDI
IR0
IR4
TDO
PGECx
PGEDx
FIGURE 5-5:
pTDO = 1
TMS = 0
TDI = IR0
nTDO = 0
2-WIRE, 2-PHASE
TCK
TMS
TDI
IR0
IR4
TDO
PGECx
PGEDx
DS61145L-page 14
TDI = IR0
TMS = 0
PIC32
6.0
PSEUDO OPERATIONS
6.1
SetMode Pseudo Operation
To simplify the description of programming details, all

operations will be described using pseudo operations.
There are several functions used in the pseudocode
descriptions. These are used either to make the
pseudocode
more
readable,
to
abstract
implementation-specific behavior, or both. When
passing parameters with pseudo operation, the
following syntax will be used:
Format:
SetMode (mode)
5h0x03 send 5-bit hexadecimal value of 3

6b011111 send 6-bit binary value of 31
Restrictions:
None.
These functions are defined in this section, and include

the following operations:
Purpose:
To set the EJTAG state machine to a specific state.
Description:
The value of mode is clocked into the device on
signal TMS. TDI is set to a 0 and TDO is ignored.
Example:
SetMode (6b011111)
SetMode (mode)
SendCommand (command)
oData = XferData (iData)
oData = XferFastData (iData)
oData = XferInstruction (instruction)
FIGURE 6-1:
SetMode 4-WIRE
Mode = 6b011111
TCK
TMS
TDI
TDO
FIGURE 6-2:
SetMode 2-WIRE
Mode = 6b011111
PGECx
PGEDx
TDI = 0
TMS = 1
TDO = 1
TDI = 0
TMS = 0
TDO = x
DS61145L-page 15
PIC32
6.2
SendCommand Pseudo Operation
Format:
SendCommand (command)
Purpose:
To send a command to select a specific TAP register.
Description (in sequence):
1.
2.
3.
4.
The TMS Header is clocked into the device to

select the Shift IR state
The command is clocked into the device on
TDI while holding signal TMS low.
The last Most Significant bit (MSb) of the
command is clocked in while setting TMS
high.
The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
SendCommand (5h0x07)
FIGURE 6-3:
SendCommand 4-WIRE
TMS Header = 1100
Command = 5h0x07
Command (MSb)
+ TMS = 1
TMS Footer = 10
TCK
TMS
TDI
FIGURE 6-4:
iMSb
iLSb
TDO
SendCommand 2-WIRE (4-PHASE)
TMS Header = 1100
Command (5h0x07) + TMS = 0 Command (MSb) + TMS = 1
TMS Footer = 10
PGECx
PGEDx
TDI = 0
TMS = 1
DS61145L-page 16
TDO = x
TDI = iLSb TMS = 0
TDO = x
TDI = iMSb TMS = 1
TDO = x
TDI = 0
TMS = 1
TDO = x
PIC32
6.3
XferData Pseudo Operation
Format:
oData = XferData (iData)
Purpose:
To clock data to and from the register selected by the
command.
1. The TMS Header is clocked into the device to
select the Shift DR state.
2. The data is clocked in/out of the device on
TDI/TDO while holding signal TMS low.
3. The last MSb of the data is clocked in/out
while setting TMS high.
4. The TMS Footer is clocked in on TMS to return
the TAP controller to the Run/Test Idle state.
Restrictions:
None.
Example:
oData = XferData (32h0x12)
FIGURE 6-5:
XferData 4-WIRE
TMS Header = 100
Data (32h0x12) Data (MSb) + TMS =1
TMS Footer = 10
TCK
TMS
TDI
iLSb
iMSb
TDO
oLSb
oMSb
FIGURE 6-6:
XferData 2-WIRE (4-PHASE)

TMS Header = 100
PGEC
PGED
TDI = 0 TMS = 1
TDO = X
TDI = 0
Data (31h0x12) + TMS = 0
TDI = iLSb TMS = 0
TMS = 0
TDI = 0
TDO = X
TMS = 0
TDO = oLSb
Data (MSb) + TMS Footer = 1
TDI = iMSb TMS = 1
TDO =...
oLSb+1
TDO = X
TMS Footer = 10
TDI = 0 TMS = 1
TDO = X
TDI = 0
TMS = 0
TDO = X
DS61145L-page 17
PIC32
6.4
XferFastData Pseudo Operation
Restrictions:
The SendCommand (ETAP_FASTDATA) must be sent
first to select the Fastdata register, as shown in
Example 6-1. See Table 19-4 for a detailed descriptions
of commands.
Format:
oData = XferFastData (iData)
Purpose:
To quickly send 32 bits of data in/out of the device.
Note:

1. The TMS Header is clocked into the device to
select the Shift DR state.
Note:
2.
EXAMPLE 6-1:
SendCommand
// Select the Fastdata Register

SendCommand(ETAP_FASTDATA)
// Send/Receive 32-bit Data
oData = XferFastData(32h0x12)
The input value of the PrAcc bit, which is 0, is

clocked in.
Note:
3.
For 2-wire (4-phase) on the last clock,

the oPrAcc bit is shifted out on TDO while
clocking in the TMS Header. If the value of
oPrAcc is not 1, the whole operation
must be repeated.
The 2-phase XferData is only used when

talking to the PE. See Section 16.0 The
Programming Executive for more
information.
For 2-wire (4-phase) the TDO during this

operation will be the LSb of output data.
The rest of the 31 bits of the input data are
clocked in and the 31 bits of output data
are clocked out. For the last bit of the input
data, the TMS Footer = 1 is set.
TMS Footer = 10 is clocked in to return the TAP

controller to the Run/Test Idle state.
FIGURE 6-7:
XferFastData 4-WIRE
TMS Header = 100
PrAcc
Data (32h0x12)
Data (MSb) + TMS = 1
TMS Footer = 10
TCK
TMS
TDI
iLSb
iMSb
TDO
oLSb
oMSb
FIGURE 6-8:
XferFastData 2-WIRE (2-phase)

TMS Header = 100
PrAcc
Data (32h0x12)
Data (MSb) TMS = 1
TMS Footer = 10
PGECx
PGEDx
TDI = X TMS = 1
DS61145L-page 18
TDI = 0 TMS = 0 TDI =

iLSb
TMS = 0
TDI =
MSb
TMS = 1 TDI = X TMS = 1
PIC32
FIGURE 6-9:
XferFastData 2-WIRE (4-PHASE)

TMS Header = 100
PGECx
PGEDx
TDI = 0 TMS = 1
TDO = X
TDI = 0 TMS = 0
TMS = 0
TDI = 0
Data (31h12) + TMS = 0
PrAcc
TDI = 0
TDO = X
TDO = oLSb
TDI = iLSb TMS = 0
TDO = oLSb+1
TMS = 0
TDO = oPrAcc
Data (MSb) + TMS Footer = 1
TDI = iMSb
TMS = 1
TDO = X
TMS Footer = 10
TDI = 0 TMS = 1
TDO = X
TDI = 0
TMS = 0
TDO = X
DS61145L-page 19
PIC32
6.5
XferInstruction Pseudo
Operation
Format:
XferInstruction (instruction)
Purpose:
To send 32 bits of data for the device to execute.
Description:
The instruction is clocked into the device and then
executed by CPU.
Restrictions:
The device must be in Debug mode.
EXAMPLE 6-2:
XferInstruction
XferInstruction (instruction)
{
// Select Control Register
SendCommand(ETAP_CONTROL);
// Wait until CPU is ready
// Check if Processor Access bit (bit 18) is set
do {
controlVal = XferData(32h0x0004C000);
} while( PrAcc(contorlVal<18>) is not 1 );
// Select Data Register
SendCommand(ETAP_DATA);
// Send the instruction
XferData(instruction);
// Tell CPU to execute instruction
XferData(32h0x0000C000);
}
DS61145L-page 20
PIC32
7.0
ENTERING 2-WIRE ENHANCED

ICSP MODE
The programming voltage applied to MCLR is VIH,

which is essentially VDD, in PIC32 devices. There is no
minimum time requirement for holding at VIH. After VIH
is removed, an interval of at least P18 must elapse
before presenting the key sequence on PGEDx.
To use the 2-wire PGEDx and PGECx pins for programming, they must be enabled. Note that any pair of
programming pins available on a particular device may
be used, however, they must be used as a pair. PGED1
must be used with PGEC1, and so on.
Note:
The key sequence is a specific 32-bit pattern: 0100

1101 0100 0011 0100 1000 0101 0000 (the
acronym MCHP, in ASCII). The device will enter
Program/Verify mode only if the key sequence is valid.
The MSb of the Most Significant nibble must be shifted
in first.
If using the 4-wire JTAG interface, the

following procedure is not necessary.
The following steps are required to enter 2-wire

Enhanced ICSP mode:
1.
2.
3.
Once the key sequence is complete, VIH must be

applied to MCLR and held at that level for as long as
the 2-wire Enhanced ICSP interface is to be
maintained. An interval of at least time P19 and P7
must elapse before presenting data on PGEDx. Signals
appearing on PGEDx before P7 has elapsed will not be
interpreted as valid.
The MCLR pin is briefly driven high, then low.

A 32-bit key sequence is clocked into PGEDx.
MCLR is then driven high within a specified
period of time and held.
Please refer to Section 20.0 AC/DC Characteristics

and Timing Requirements for timing requirements.
FIGURE 7-1:
Upon successful entry, the programming operations

documented in subsequent sections can be performed.
While in 2-wire Enhanced ICSP mode, all unused I/Os
are placed in the high-impedance state.
ENTERING ENHANCED ICSP MODE

P20
P6
P14
MCLR
P19
P7
VIH
VIH
VDD
Program/Verify Entry Code = 0x4D434850
0
b31
PGEDx
1
b30
0
b29
0
b28
1
...
b27
0
b3
0
b2
0
b1
0
b0
PGECx
P18
P1A
P1B
DS61145L-page 21
PIC32
8.0
CHECK DEVICE STATUS
Before a device can be programmed, the programmer

must check the status of the device to ensure that it is
ready to receive information.
FIGURE 8-1:
CHECK DEVICE STATUS
8.1
4-wire Interface
Four-wire JTAG programming is a Mission mode

operation and therefore the setup sequence to begin
programing should be done while asserting MCLR.
Holding the device in Reset prevents the processor
from executing instructions or driving ports.
The following steps are required to check the device
status using the 4-wire interface:
Set MCLR low
4-wire
SetMode (6b011111)
Set MCLR pin low.

SetMode (6b011111) to force the Chip TAP
controller into Run Test/Idle state.
SendCommand (MTAP_SW_MTAP).
SendCommand (MTAP_COMMAND).
statusVal = XferData (MCHP_STATUS).
If CFGRDY (statusVal<3>) is not 1 and
FCBUSY (statusVal<2>) is not 0 GOTO step 5.
1.
2.
3.
4.
5.
6.
Note:
SendCommand (MTAP_SW_MTAP)
SendCommand (MTAP_COMMAND)
statusVal = XferData (MCHP_STATUS)
No
FCBUSY = 0
CFGRDY = 1
Yes
Done
8.2
2-wire Interface
The following steps are required to check the device

status using the 2-wire interface:
1.
2.
3.
4.
5.
SetMode (6b011111) to force the Chip TAP

controller into Run Test/Idle state.
FCBUSY (statusVal<2>) is not 0, GOTO
step 4.
Note:
DS61145L-page 22
If using the 4-wire interface, the oscillator

source, as selected by the Configuration
Words, must be present to access flash
memory. In an unprogrammed device, the
oscillator source is the internal FRC allowing for flash memory access. If the Configuration Words have been reprogrammed
selecting an external oscillator source
then it must be present for flash memory
access. See the Special Features
chapter in the specific device data sheet
for details regarding oscillator selection
using the Configuration Word settings.
If CFGRDY and FCBUSY do not come to

the proper state within 10 ms, the
sequence may have been executed
incorrectly or the device is damaged.
PIC32
9.0
ERASING THE DEVICE
Before a device can be programmed, it must be

erased. The erase operation writes all 1s to the Flash
memory and prepares it to program a new set of data.
Once a device is erased, it can be verified by
performing a Blank Check operation. See
Section 9.1 Blank Check for more information.
The procedure for erasing program memory (Program,
Boot, and Configuration memory) consists of selecting
the MTAP and sending the MCHP_ERASE command.
The programmer then must wait for the erase operation
to complete by reading and verifying bits in the
MCHP_STATUS value. Figure 9-1 illustrates the process
for performing a Chip Erase.
Note:
The Device ID memory locations are readonly and cannot be erased. Therefore,
Chip Erase has no effect on these memory
locations.
FIGURE 9-1:
ERASE DEVICE
Select MTAP
The following steps are required to erase a target

device:
XferData (MCHP_ERASE).
Delay 1 ms.
FCBUSY (statusVal<2>) is not 0, GOTO to
step 4.
1.
2.
3.
4.
5.
6.
Note:
9.1
The Chip Erase operation is a self-timed

operation. If the FCBUSY and CFGRDY
bits do not become properly set within the
specified Chip Erase time, the sequence
may have been executed incorrectly or
the device is damaged.
Blank Check
The term Blank Check implies verifying that the

device has been successfully erased and has no
programmed memory locations. A blank or erased
memory location always reads as 1.
The device Configuration registers are ignored by the
Blank Check. Additionally, all unimplemented memory
space should be ignored from the Blank Check.
Put MTAP in Command Mode

Issue Chip Erase Command

XferData (MCHP_ERASE)
1 millisecond Delay
Read Erase Status

No
FCBUSY = 0
CFGRDY = 1
Yes
Done
DS61145L-page 23
PIC32
10.0
ENTERING SERIAL
EXECUTION MODE
10.1
Before a device can be programmed, it must be

placed in Serial Execution mode. The procedure for
entering Serial Execution mode consists of verifying
that the device is not code-protected. If the device is
code-protected, a Chip Erase must be performed.
See Section 9.0 Erasing the Device for details.
FIGURE 10-1:
ENTERING SERIAL
EXECUTION MODE
Select MTAP

Cannot Enter
Must Erase First
Yes
Assert Reset
XferData (MCHP_ASSERT_RST)
2-wire
Select ETAP
SendCommand (MTAP_SW_ETAP)
Put CPU in Serial Exec Mode

SendCommand (ETAP_EJTAGBOOT)
Select MTAP
1.
2.
3.
4.
It is assumed that MCLR has been driven

low from the previous Check Device
Status step (see Figure 8-1).
If CPS (statusVal<7>) is not 1, the device must
be erased first.
SendCommand (MTAP_SW_ETAP).
SendCommand (ETAP_EJTAGBOOT).
Set MCLR high.
2-wire Interface
The following steps are required to enter Serial

Execution mode:
No
Note:
10.2
Read Code-Protect Status
CPS = 1
The following steps are required to enter Serial

Execution mode:
5.
6.
7.
4-wire Interface
If CPS (statusVal<7>) is not 1, the device must
be erased first.
5. XferData (MCHP_ASSERT_RST).
6. SendCommand (MTAP_SW_ETAP).
7. SendCommand (ETAP_EJTAGBOOT).
8. SendCommand (MTAP_SW_MTAP).
9. SendCommand (MTAP_COMMAND).
10. XferData (MCHP_DE_ASSERT_RST).
11. XferData (MCHP_FLASH_ENABLE) This step is
not required for PIC32MZ EC family devices.
12. SendCommand (MTAP_SW_ETAP).
1.
2.
3.
4.
Set MCLR High

4-wire

Release Reset
XferData (MCHP_DE_ASSERT_RST)
Enable Flash
XferData (MCHP_FLASH_EN)
Not required for PIC32MZ EC devices
Select ETAP
SendCommand (MCHP_SW_ETAP)
2-wire
DS61145L-page 24
PIC32
11.0
DOWNLOADING THE
PROGRAMMING EXECUTIVE
(PE)
The PE resides in RAM memory and is executed by the

CPU to program the device. The PE provides the
mechanism for the programmer to program and verify
PIC32 devices using a simple command set and
communication protocol. There are several basic
functions provided by the PE:
Read memory
Erase memory
Program memory
Blank check
Read executive firmware revision
Get the Cyclic Redundancy Check (CRC) of Flash
memory locations
The PE performs the low-level tasks required for

programming and verifying a device. This allows the
programmer to program the device by issuing the
appropriate commands and data. A detailed
description for each command is provided in
Section 16.2 The PE Command Set.
The PE uses the devices data RAM for variable
storage and program execution. After the PE has run,
no assumptions should be made about the contents of
data RAM.
After the PE is loaded into the data RAM, the PIC32
family can be programmed using the command set
shown in Table 16-1.
FIGURE 11-1:
DOWNLOADING THE PE
Write the PE Loader to RAM
Table 11-1 lists the steps that are required to download

the PE.
TABLE 11-1:
DOWNLOAD THE
PE
Operation
Operand
Step 1:
lui
ori
lui
ori
sw
Initialize BMXCON to 0x1F0040. The instruction

sequence executed by the PIC32 core is:
a0,0xbf88
a0,a0,0x2000 /* address of BMXCON */
a1,0x1f
a1,a1,0x40
/* $a1 has 0x1f0040 */
a1,0(a0)
/* BMXCON initialized */
XferInstruction 0x3c04bf88
XferInstruction 0x34842000
XferInstruction 0x3c05001f
XferInstruction 0x34a50040
XferInstruction 0xac850000
Step 2:
li
sw
Initialize BMXDKPBA to 0x800. The instruction

a1,0x800
a1,16(a0)
Step 3:
lw
sw
sw
Initialize BMXDUDBA and BMXDUPBA to the

value of BMXDRMSZ. The instruction sequence
executed by the PIC32 core is:
a1,64(a0)
/* load BMXDMSZ */
a1,32(a0)
a1,48(a0)
XferInstruction 0x8C850040
Step 4:
Set up PIC32 RAM address for PE. The instruction sequence executed by the PIC32 core is:
lui a0,0xa000
ori a0,a0,0x800
XferInstruction 0x3c04a000
Step 5:
Load the PE
Loading the PE in the memory is a two step process:

1.
2.
Load the PE loader in the data RAM. (The PE

loader loads the PE binary file in the proper location of the data RAM, and when done, jumps to
the programming exec and starts executing it.)
Feed the PE binary to the PE loader.
lui
ori
sw
addiu
Load the PE_Loader. Repeat this step (Step 5)

until the entire PE_Loader is loaded in the PIC32
memory. In the operands field, <PE_loader
hi++> represents the MSbs 31 through 16 of the
PE loader op codes shown in Table 11-2. Likewise, <PE_loader lo++> represents the LSbs
15 through 0 of the PE loader op codes shown in
Table 11-2. The ++ sign indicates that when
these operations are performed in succession,
the new word is to be transferred from the list of
op codes of the LPE Loader shown in Table 11-2.
The instruction sequence executed by the PIC32
core is:
a2, <PE_loader hi++>
a0,a0, <PE_loader lo++>
a2,0(a0)
a0,a0,4
XferInstruction (0x3c06 <PE_loader hi++> )

XferInstruction (0x34c6 <PE_loader lo++> )
DS61145L-page 25
PIC32
TABLE 11-1:
DOWNLOAD THE
PE (CONTINUED)
Operation
Step 6:
lui
ori
jr
nop
Operand
Jump to the PE_Loader. The instruction

t9,0xa000
t9,t9,0x800
t9
TABLE 11-2:
PE LOADER OP CODES
Op code
Instruction
0x3c07dead
lui
a3, 0xdead
0x3c06ff20
lui
a2, 0xff20
0x3c05ff20
lui
al, 0xff20
herel:
0x8cc40000
lw
XferInstruction 0x3c19a000
0x8cc30000
lw
v1, 0 (a2)
0x1067000b
beq
v1, a3, <here3>
0x00000000
nop
0x1060fffb
beqz
Step 7:
0x00000000
nop
0x8ca20000
lw
v0, 0 (a1)
0x2463ffff
addiu
v1, v1, -1
0xac820000
sw
v0, 0 (a0)
0x24840004
addiu
a0, a0, 4
0x1460fffb
bnez
v1, <here2>
0x00000000
nop
0x1000fff3
0x00000000
nop
0x3c02a000
lui
v0, 0xa000
0x34420900
ori
v0, v0, 0x900
0x00400008
jr
v0
0x00000000
nop
Load the PE using the PE_Loader. Repeat the

last instruction of this step (Step 7) until the entire
PE is loaded into the PIC32 memory. In this step,
you are given an Intel Hex format file of the PE
that you will parse and transfer a number of 32-bit
words at a time to the PIC32 memory (refer to
Appendix B: Hex File Format). The instruction
sequence executed by the PIC32 is shown in the
Instruction column of Table 11-2: PE Loader Op
Codes.
SendCommand
ETAP_FASTDATA
XferFastData
PE_ADDRESS (Address of PE
program block from PE Hex
file)
XferFastData
XferFastData
Step 8:
PE_SIZE (Number of 32-bit

words of the program block
from PE Hex file)
PE software op code from PE
Hex file (PE Instructions)
a0, 0 (a2)
v1, <here1>
here2:
<here1>
here3:
Jump to the PE. Magic number (0xDEAD0000)

instructs the PE_Loader that the PE is completely
loaded into the memory. When the PE_Loader
sees the magic number, it jumps to the PE.
XferFastData
0x00000000
XferFastData
0xDEAD0000
DS61145L-page 26
PIC32
12.0
DOWNLOADING A DATA
BLOCK
To program a block of data to the PIC32 device, it must

first be loaded into SRAM.
12.1
Without the PE
To program a block of memory without the use of the

PE, the block of data must first be written to RAM. This
method requires the programmer to transfer the actual
machine instructions with embedded (immediate) data
for writing the block of data to the devices internal RAM
memory.
FIGURE 12-1:
DOWNLOADING DATA
WITHOUT THE PE
The following steps are required to download a block of

data:
1.
2.
XferInstruction (op code).

Repeat Step 1 until the last instruction is
transferred to CPU.
TABLE 12-1:
Op code
Step 1:
Step 3:
12.2
Write 32-bit Immediate
Data to bufAddr
Increment bufAddr
lui
$s0, 0xA000;
Write the entire row of data to be programmed

into system SRAM.
3c08<DATA>
3508<DATA>
ae08<OFFSET>
bufAddr = RAM Buffer Address
Instruction
Initialize SRAM Base Address to 0xA0000000.
3c10a000
Step 2:
DOWNLOAD DATA OP
CODES
lui
ori
sw
$t0, <DATA(31:16)>;
$t0, <DATA(15:0)>;
$t0, <OFFSET>($s0);
// OFFSET increments by 4
Repeat Step 2 until one row of data has been

loaded.
With the PE
When using the PE the steps in Section 12.0 Downloading a Data Block and Section 13.0 Initiating a
Flash Row Write are handled in two single commands:
ROW_PROGRAM and PROGRAM.
The ROW_PROGRAM command programs a single row of
Flash data, while the PROGRAM command programs
multiple rows of Flash data. Both of these commands
are documented in Section 16.0 The Programming
Executive.
No
Done
DS61145L-page 27
PIC32
13.0
Note:
INITIATING A FLASH ROW

WRITE
Certain PIC32 devices have available
ECC memory. When the ECC feature is
used, Flash memory must be programmed in groups of four 32-bit words
using four, 32-bit word alignment. If ECC
is dynamically used, the programming
method determines when the feature is
used. ECC is not enabled for words programmed with the single word programming command. ECC is enabled for words
programmed in groups of four, either with
the quad word or row programming commands. Failure to adhere to these methods can result in ECC DED errors during
run-time. See the specific device data
sheet for details regarding ECC use and
configuration.
Once a row of data has been downloaded into the

devices SRAM, the programming sequence must be
initiated to write the block of data to Flash memory.
See Table 13-1 for the op code and instructions for
initiating a Flash row write.
13.1
With the PE
13.2
Without the PE
Flash memory write operations are controlled by the

NVMCON register. Programming is performed by
setting NVMCON to select the type of write operation
and initiating the programming sequence by setting the
WR control bit (NVMCON<15>).
FIGURE 13-1:
INITIATING FLASH WRITE

WITHOUT THE PE
Unprotect Control Registers
Select Write Operation
Load Addresses in NVM Registers
Unlock Flash Controller
Start Operation
Done
When using the PE, the data is immediately written to

the Flash memory from the SRAM. No further action is
required.
DS61145L-page 28
PIC32
The following steps are required to initiate a Flash
write:
1.
2.

transferred to the CPU.
TABLE 13-1:
Op Code
Step 1:
lui a0,0xbf80
ori a0,a0,0x0600
ori s3,$0,0x8080
sw s1,16(a0)
sw s2,16(a0)
sw s3,144(a0)
nop
All PIC32 devices: Set the NVMADDR register

with the address of the Flash row to be
programmed.
3c08<ADDR>
3508<ADDR>
ac880020
Step 5:
lui a0,0xbf80
ori a0,a0,0xf400
PIC32MZ EC devices only: Unlock and disable

Boot Flash write protection.
AC910010
AC920010
AC950090
00000000
Step 4:
a1,$0,0x4003
a2,$0,0x8000
a3,$0,0x4000
s1,0xaa99
s1,s1,0x6655
s2,0x5566
s2,s2,0x99aa
s0,0x0000
PIC32MZ EC devices only: Set register a0 to the

base address of the NVM register (0xBF80_0600).
Register s3 is set for the value used to disable
write protection in NVMBPB.
3c04bf80
34840600
34158080
Step 3:
ori
ori
ori
lui
ori
lui
ori
lui
PIC32MX devices only: Set register a0 to the

base address of the NVM register (0xBF80_F400).
3c04bf80
3484f400
Step 2:
Instruction
All PIC32 devices: Initialize constants. Registers

a1, a2, and a3 are set for WREN = 1 or
NVMOP<3:0> = 0011, WR = 1 and WREN = 1,
respectively. Registers s1 and s2 are set for the
unlock data values and S0 is initialized to 0.
34054003
34068000
34074000
3c11aa99
36316655
3c125566
365299aa
3c100000
Step 2:
INITIATE FLASH ROW WRITE

OP CODES FOR PIC32
DEVICES
lui t0,<FLASH_ROW_ADDR(31:16)>
ori t0,t0,<FLASH_ROW_ADDR(15:0)>
sw t0,32(a0)
PIC32MX devices only: Set the NVMSRCADDR

register with the physical source SRAM address
(offset is 64).
3610<ADDR>
ac900040
ori s0,s0,<RAM_ADDR(15:0)>
sw s0,64(a0)
TABLE 13-1:
Op Code
Step 5:
here1:
lw t0,0(a0)
andi t0,t0,0x0800
bne t0,$0,here1
nop
All PIC32 devices: Unlock the NVMCON register

and start the write operation.
ac910010
ac920010
ac860008
Step 9:
sw a1,0(a0)
delay (6 s)
PIC32MX devices only: Poll the LVDSTAT

register.
8C880000
31080800
1500fffd
00000000
Step 8:
ori s0,s0,<RAM_ADDR(15:0)>
sw s0,112(a0)
All PIC32 devices: Set up the NVMCON register

for write operation.
ac850000
Step 7:
Instruction
PIC32MZ EC devices only: Set the

NVMSRCADDR register with the physical source
SRAM address (offset is 112).
3610<ADDR>
ac900040
Step 6:
INITIATE FLASH ROW WRITE

OP CODES FOR PIC32
DEVICES (CONTINUED)
sw s1,16(a0)
sw s2,16(a0)
sw a2,8(a0)
All PIC32 devices: Loop until the WR bit

(NVMCON<15>) is clear.
8c880000
01064024
1500fffd
00000000
here2:
lw t0,0(a0)
and t0,t0,a2
bne t0,$0,here2
nop
Step 10: All PIC32 devices: Wait at least 500 ns after

seeing a 0 in the WR bit (NVMCON<15>) before
writing to any of the NVM registers. This requires
inserting a NOP in the execution. The following
example assumes that the core is executing at
8 MHz; therefore, four NOP instructions equate to
500 ns.
00000000
00000000
00000000
00000000
nop
nop
nop
nop
Step 11: All PIC32 devices: Clear the WREN bit

(NVMCONM<14>).
ac870004
sw a3,4(a0)
Step 12: All PIC32 devices: Check the WRERR bit

(NVMCON<13>) to ensure that the program
sequence has completed successfully. If an error
occurs, jump to the error processing routine.
lw t0,0(a0)
8c880000
andi t0,zero,0x2000
30082000
1500<ERR_PROC> bne t0, $0, <err_proc_offset>
nop
00000000
DS61145L-page 29
PIC32
14.0
VERIFY DEVICE MEMORY
The verify step involves reading back the code memory

space and comparing it against the copy held in the
programmers buffer. The Configuration registers are
verified with the rest of the code.
Note:
14.1
Because the Configuration registers

include the device code protection bit,
code memory should be verified immediately after writing (if code protection is
enabled). This is because the device will
not be readable or verifiable if a device
Reset occurs after the code-protect bit
has been cleared.
14.2
Verifying Memory without the PE
Reading from Flash memory is performed by executing

a series of read accesses from the Fastdata register.
Table 19-4 shows the EJTAG programming details,
including the address and op code data for performing
processor access operations.
FIGURE 14-2:
VERIFYING MEMORY
WITHOUT THE PE
Read Memory Location
Verifying Memory with the PE

Verify Location
Memory verify is performed using the GET_CRC

command, as shown in Table 16-2.
FIGURE 14-1:
VERIFYING MEMORY
WITH THE PE
No
Done
Issue Verify Command
The following steps are required to verify memory:

Receive Response
1.
2.
3.
The following steps are required to verify memory using

the PE:
1.
2.
3.
4.
XferFastData (GET_CRC).
XferFastData (start_Address).
XferFastData (length).
valCkSum = XferFastData (32h0x00).
Verify that valCkSum matches the checksum of the

copy held in the programmers buffer.
4.

transferred to the CPU.
Verify that valRead matches the copy held in the
programmers buffer.
Repeat Steps 1-3 for each memory location.
TABLE 14-1:
Op code
Step 1:
Initialize some constants.
3c13ff20
Step 2:
lui $t0,<FLASH_WORD_ADDR(31:16)>
ori $t0,<FLASH_WORD_ADDR(15:0)>
Write to Fastdata location.
8d090000
ae690000
DS61145L-page 30
lui $s3, 0xFF20
Read memory Location.
3c08<ADDR>
3508<ADDR>
Step 3:
VERIFY DEVICE OP CODES

Instruction
lw $t1, 0($t0)
sw $t1, 0($s3)
Step 4:
Read data from Fastdata register 0xFF200000.
Step 5:
Repeat Steps 2-4 until all configuration locations

are read.
PIC32
15.0
EXITING PROGRAMMING
MODE
Once a device has been properly programmed, the

device must be taken out of Programming mode to start
proper execution of its new program memory contents.
15.1
4-wire Interface
15.2
Exiting Programming mode is done by removing VIH

from MCLR, as illustrated in Figure 15-2. The only
requirement for exit is that an interval, P16, should
elapse between the last clock and program signals on
PGECx and PGEDx before removing VIH.
FIGURE 15-2:
Exiting Programming mode is done by removing VIH

from MCLR, as illustrated in Figure 15-1. The only
requirement for exit is that an interval, P16, should
elapse between the last clock and program signals
before removing VIH.
FIGURE 15-1:
2-wire Interface
2-WIRE EXIT
PROGRAMMING MODE
P16
P17
VIH
MCLR
VDD
4-WIRE EXIT
PROGRAMMING MODE
PGEDx
P16
VIH
PGECx
MCLR
PGEDx = Input
VDD
The following list provides the actual steps required to

exit Programming mode:
TCK
TMS
TDI
TDO
1.
2.
3.
4.
SetMode (5b11111).
Assert MCLR.
Issue a clock pulse on PGECx.
Remove power (if the device is powered).
The following steps are required to exit Programming

mode:
1.
2.
3.
SetMode (5b11111).
Assert MCLR.
Remove power (if the device is powered).
DS61145L-page 31
PIC32
16.0
THE PROGRAMMING
EXECUTIVE
Note: The Programming Executive (PE) is included

with your installation of MPLAB IDE. To
download the appropriate PE file for your
device, please visit the related product page
on the Microchip web site.
16.1
PE Communication
The programmer and the PE have a master-slave

relationship, where the programmer is the master
programming device and the PE is the slave.
All communication is initiated by the programmer in the
form of a command. The PE is able to receive only one
command at a time. Correspondingly, after receiving
and processing a command, the PE sends a single
response to the programmer.
16.1.1
2-WIRE ICSP EJTAG RATE
In Enhanced ICSP mode, the PIC32 family devices

operate from the internal Fast RC oscillator, which has
a nominal frequency of 8 MHz.
16.1.2
COMMUNICATION OVERVIEW
The programmer and the PE communicate using the

EJTAG Address, Data and Fastdata registers. In particular, the programmer transfers the command and data
to the PE using the Fastdata register. The programmer
receives a response from the PE using the Address
and Data registers. The pseudo operation of receiving
a response is shown in the GetPEResponse pseudo
operation below:
Format:
response = GetPEResponse()
Purpose:
Enables the programmer to receive the 32-bit
response value from the PE.
EXAMPLE 16-1:
// Wait until CPU is ready

// Check if Proc. Access bit (bit 18) is set
do {
controlVal=XferData(32h0x0004C000 );
} while( PrAcc(contorlVal<18>) is not 1 );
// Select Data Register
SendCommand(ETAP_DATA);
// Receive Response
response = XferData(0);
// Tell CPU to execute instruction
XferData(32h0x0000C000);
// return 32-bit response
return response;
}
The typical communication sequence between the

programmer and the PE is shown in Table 16-1.
The sequence begins when the programmer sends the
command and optional additional data to the PE, and
the PE carries out the command.
When the PE has finished executing the command, it
sends the response back to the programmer.
The response may contain more than one response.
For example, if the programmer sent a READ
command, the response will contain the data read.
TABLE 16-1:
COMMUNICATION
SEQUENCE FOR THE PE
Operation
Step 1:
Operand
Send command and optional data from

programmer to the PE.
XferFastData
(Command | data len)
XferFastData..
optional data..
Step 2:
DS61145L-page 32
GetPEResponse EXAMPLE
WORD GetPEResponse()
{
WORD response;
Programmer reads the response from the PE.
GetPEResponse
response
GetPEResponse...
response...
PIC32
16.2
The PE Command Set
The PE command set is shown in Table 16-2. This

table contains the op code, mnemonic, and short
description for each command. Functional details on
each command are provided in Section 16.2.3
ROW_PROGRAM
Command
through
Section 16.2.14 CHANGE_CFG Command.
The PE sends a response to the programmer for each
command that it receives. The response indicates if the
command was processed correctly. It includes any
required response data or error data.
16.2.1
COMMAND FORMAT
All PE commands have a general format consisting of

a 32-bit header and any required data for the command
(see Figure 16-1). The 32-bit header consists of a
16-bit Op code field, which is used to identify the
command, and a 16-bit command Operand field. Use
of the Operand field varies by command.
Note:
Some commands have no Operand information, however, the Operand field must
be sent and the programming executive
will ignore the data.
TABLE 16-2:
Op code
FIGURE 16-1:
COMMAND FORMAT
31
16
Op code
15
0
Operand (optional)
31
16
Command Data High (if required)
15
0
Command Data Low (if required)
The command in the Op code field must match one of

the commands in the command set that is listed in
Table 16-2. Any command received that does not
match a command the list returns a NACK response,
as shown in Table 16-3.
The PE uses the command Operand field to determine
the number of bytes to read from or to write to. If the
value of this field is incorrect, the command is not be
properly received by the PE.
PE COMMAND SET
Mnemonic
Description
0x0
ROW_PROGRAM(1)
Program one row of Flash memory at the specified address.
0x1
READ
Read N 32-bit words of memory starting from the specified address (N < 65,536).
0x2
PROGRAM
Program Flash memory starting at the specified address.

(3)
0x3
WORD_PROGRAM
0x4
CHIP_ERASE
Chip Erase of entire chip.
0x5
PAGE_ERASE
Erase pages of code memory from the specified address.
0x6
BLANK_CHECK
Blank Check code.
Program one word of Flash memory at the specified address.
0x7
EXEC_VERSION
Read the PE software version.
0x8
GET_CRC
Get the CRC of Flash memory.
0x9
PROGRAM_CLUSTER
Programs the specified number of bytes to the specified address.
0xA
GET_DEVICEID
Returns the hardware ID of the device.
0xB
CHANGE_CFG
(2)
0xC
GET_CHECKSUM
0xD
QUAD_WORD_PGRM
Used by the probe to set various configuration settings for the PE.
Get the checksum of Flash memory.
(4)
Program four words of Flash memory at the specified address.
Note 1: Refer to Table 5-1 for the row size for each device.
2: This command is not available in PIC32MX1XX/2XX devices.
3: On the PIC32MZ EC family devices, which incorporate ECC, the WORD_PROGRAM command will not
generate the ECC parity bits. Reading a location programmed with the WORD_PROGRAM command with
ECC enabled will cause a DED fault.
4: This command is available on PIC32MZ EC family devices only.
DS61145L-page 33
PIC32
16.2.2
RESPONSE FORMAT
16.2.3
The PE response set is shown in Table 16-3. All PE

responses have a general format consisting of a 32-bit
header and any required data for the response (see
Figure 16-2).
FIGURE 16-2:
RESPONSE FORMAT
31
16
ROW_PROGRAM COMMAND
The ROW_PROGRAM command instructs the PE to

program a row of data at a specified address.
The data to be programmed to memory, located in
command words Data_1 through Data_N, must be
arranged using the packed instruction word format
shown in Table 16-4 (this command expects an entire
row of data).
Last Command
15
Operand
31
31
16
16
Data_High_N
15
Addr_High
15
0
Data_Low_N
Addr_Low
31
16
Data_High_1
Last_Cmd Field
Last_Cmd is a 16-bit field in the first word of the

response and indicates the command that the PE
processed. It can be used to verify that the PE correctly
received the command that the programmer
transmitted.
15
0
Data_Low_1
31
16
Data_High_N
15
Response Code
Data_Low_N
The response code indicates whether the last

command succeeded or failed, or if the command is a
value that is not recognized. The response code values
are shown in Table 16-3.
TABLE 16-3:
RESPONSE VALUES
Mnemonic
0x0
PASS
0x2
FAIL
0x3
NACK
16.2.2.3
0
Data_Low_1
Op code
Op code
15
15
16.2.2.2
16
16
Data_High_1
16.2.2.1
ROW_PROGRAM COMMAND
31
Response Code
31
FIGURE 16-3:
Description
Command successfully
processed
Command unsuccessfully
processed
Command not known
Optional Data
The response header may be followed by optional data

in case of certain commands such as read. The
number of 32-bit words of optional data varies
depending on the last command operation and its
parameters.
TABLE 16-4:
ROW_PROGRAM FORMAT
Field
Description
Op code
0x0
Operand
Not used
Addr_High
High 16 bits of 32-bit destination

address
Addr_Low
Low 16 bits of 32-bit destination

address
Data_High_1 High 16 bits data word 1

Data_Low_1
Low 16 bits data word 1
Data_High_N High 16 bits data word 2 through N

Data_Low_N Low 16 bits data word 2 through N
Expected Response (1 word):
FIGURE 16-4:
ROW_PROGRAM RESPONSE
31
16
Last Command
15
0
Response Code
DS61145L-page 34
PIC32
16.2.4
READ COMMAND
The READ command instructs the PE to read from

memory the number of 32-bit words specified in the
Operand field starting from the 32-bit address specified
by the Addr_Low and Addr_High fields. This command
can be used to read Flash memory, as well as
Configuration Words. All data returned in response to
this command uses the packed data format that is
shown in Table 16-5.
FIGURE 16-5:
READ COMMAND
31
16
Op code
15
0
Operand
31
16
Addr_High
15
0
Addr_Low
TABLE 16-5:
READ FORMAT
Field
Description
Op code
0x1
Operand
N number of 32-bit words to read

(maximum of 65,535)
Addr_Low
Low 16 bits of 32-bit source address
Addr_High
High 16 bits of 32-bit source

address
Expected Response:
FIGURE 16-6:
READ RESPONSE
31
16
Last Command
15
0
Response Code
31
16
Data_High_1
15
0
Data_Low_1
31
16
Data_High_N
15
0
Data_Low_N
Note:
Reading unimplemented memory will

cause the PE to reset. Please ensure that
only memory locations present on a
particular device are accessed.
DS61145L-page 35
PIC32
16.2.5
PROGRAM COMMAND
There are three programming scenarios:
The PROGRAM command instructs the PE to program

Flash memory, including Configuration Words, starting
from the 32-bit address specified in the Addr_Low and
Addr_High fields. A 32-bit length field specifies the
number of bytes to program.
The address must be aligned to a Flash row size
boundary and the length must be a multiple of a Flash
row size. Flash row sizes are either 32 words (128
bytes) or 128 words (512 bytes). Please refer to
Table 5-1.
PROGRAM COMMAND
FIGURE 16-7:
31
16
Op code
15
0
Operand
31
16
Addr_High
15
0
Addr_Low
31
16
Length_High
15
0
Length_Low
31
16
Data_High_1
15
0
Data_Low_1
31
1.
The length of the data to be programmed is the

size of a single flash row.
The length of the data to be programmed is the
size of two flash rows.
The length of the data to be programmed is
larger than the size of two flash rows.
2.
3.
When the data length is equal to 512 bytes, the PE

receives the 512-byte block of data from the probe and
immediately sends the response for this command
back to the probe.
The PE will respond for each row of data that it
receives. If the data length of the command is equal to
a single row, a single PE response is generated. If the
data length is equal to two rows, the PE waits to
receive both rows of data, and then sends back-toback responses for each data row. If the data length is
greater than two rows of data, the PE will send the
response for the first row after receiving the first two
rows of data. Subsequent responses are sent after
receiving subsequent data row packets. The
responses will lag the data by one row. When the last
row of data is received the PE will respond with backto-back responses for the second-to-last data row
followed by the last row.
If the PE encounters an error in programming any of
the blocks, it sends a failure status to the probe and
aborts the PROGRAM command. On receiving the failure
status, the probe must stop sending data. The PE will
not process any other data for this command from the
probe. The process is illustrated in Figure 16-9.
Note:
16
Data_High_N
15
0
Data_Low_N
PROGRAM FORMAT
TABLE 16-6:
Field
Description
Op code
0x2
Operand
Not used
Addr_Low

address
Addr_High

address
Length_Low
Low 16 bits of Length
Length_High
High 16 bits Length
Data_Low_N
Low 16 bits data word 2 through N
Data_High_N
High 16 bits data word 2 through N
If the PROGRAM command fails, the

programmer should read the failing row
using the READ command from the Flash
memory. Next, the programmer should
compare the row received from Flash
memory to its local copy, word-by-word, to
determine the address where Flash
programming fails.
The response for this command is a little different than

the response for other commands. The 16 MSbs of the
response contain the 16 LSbs of the destination
address, where the last block is programmed. This
helps the probe and the PE maintain proper
synchronization of sending, and receiving, data and
responses.
FIGURE 16-8:
PROGRAM RESPONSE
31
16
LSB 16 bits of the destination address of last block

15
0
Response Code
DS61145L-page 36
PIC32
FIGURE 16-9:
PROGRAM COMMAND ALGORITHM

Start
Data is
equal to a
single row
Data is
equal to
two rows
Data
is larger than
two rows
Send one row

of data
Send first row

of data
Send first row

of data
Receive status
(LSB 16 bits of
Destination Address
Status Value)
Send second row

of data
Send second row

of data
Receive status
for Row 1
Receive status
for Row 1
Receive status
for Row 2
Send third row

of data
Receive status
for Row 2
Send Nth row

of data
Receive status
for Row N-1
Receive status
for Row N
Done
DS61145L-page 37
PIC32
16.2.6
WORD_PROGRAM COMMAND
16.2.7
CHIP_ERASE COMMAND
The WORD_PROGRAM command instructs the PE to

program a 32-bit word of data at the specified address.
The CHIP_ERASE command erases the entire chip,

including the configuration block.
FIGURE 16-10:
After the erase is performed, the entire Flash memory

contains 0xFFFFFFFF.
WORD_PROGRAM
COMMAND
31
16
Op code
15
0
Operand
31
16
FIGURE 16-12:
CHIP_ERASE COMMAND
31
16
Op code
15
0
Operand
Addr_High
15
TABLE 16-8:
Addr_Low
31
Field
16
Data_High
15
0
Data_Low
TABLE 16-7:
WORD_PROGRAM FORMAT
Field
Description
Op code
0x3
Operand
Not used
CHIP_ERASE FORMAT
Description
Op code
0x4
Operand
Not used
Addr_Low

address
Addr_High

address
FIGURE 16-13:
Addr_High

address
31
Addr_Low

address
15
Data_High
High 16 bits data word
Data_Low
Low 16 bits data word
CHIP_ERASE RESPONSE
16
Last Command
0
Response Code
FIGURE 16-11:
WORD_PROGRAM
RESPONSE
31
16
Last Command
15
0
Response Code
DS61145L-page 38
PIC32
16.2.8
PAGE_ERASE COMMAND
16.2.9
BLANK_CHECK COMMAND
The PAGE_ERASE command erases the specified

number of pages of code memory from the specified
base address. Depending on the device, the specified
base address must be a multiple of 0x400 or 0x100.
The BLANK_CHECK command queries the PE to

determine whether the contents of code memory and
code-protect Configuration bits (GCP and GWRP) are
blank (contains all 1s).
After the erase is performed, all targeted words of code

memory contain 0xFFFFFFFF.
FIGURE 16-16:
BLANK_CHECK COMMAND
31
FIGURE 16-14:
16
PAGE_ERASE COMMAND
31
Op code
16
15
31
16
15
31
Op code
15
Operand
16
Operand
31
Addr_High
0
Addr_High
15
Addr_Low
16
Addr_Low
TABLE 16-9:
Length_High
15
PAGE_ERASE FORMAT
Field
0
Length_Low
Description
TABLE 16-10: BLANK_CHECK FORMAT
Op code
0x5
Operand
Number of pages to erase
Addr_Low

address
Op code
0x6
Addr_High

address
Operand
Not used
Address
Address where to start the Blank

Check
Length
Number of program memory locations

to check in terms of bytes
Field
FIGURE 16-15:
PAGE_ERASE RESPONSE
31
16
Last Command
15
Description
Expected Response (1 word for blank device):
FIGURE 16-17:
0
BLANK_CHECK RESPONSE
31
Response Code
16
Last Command
15
0
Response Code
DS61145L-page 39
PIC32
16.2.10
EXEC_VERSION COMMAND
GET_CRC COMMAND
16.2.11
EXEC_VERSION queries for the version of the PE

software stored in RAM.
GET_CRC calculates the CRC of the buffer from the

specified address to the specified length, using the
table look-up method. The CRC details are as follows:
FIGURE 16-18:
EXEC_VERSION
COMMAND
31
16
Op code
15
0
Operand
CRC-CCITT, 16-bit
Polynomial: X^16+X^12+X^5+1, hex 0x00011021
Seed: 0xFFFF
Most Significant Byte (MSB) shifted in first
Note 1: In the response, only the CRC Least
Significant 16 bits are valid.
2: The PE will automatically determine if the
hardware CRC is available and use it by
default. The hardware CRC is not used
on PIC32MX1XX/2XX devices.
TABLE 16-11: EXEC_VERSION FORMAT

Field
Op code
Operand
Description
FIGURE 16-20:
0x7
GET_CRC COMMAND
31
Not used
16
Op code
FIGURE 16-19:
15
EXEC_VERSION
RESPONSE
31
0
Operand
31
16
Addr_High
16
15
Last Command
15
0
Addr_Low
0
Version Number
31
16
Length_High
15
0
Length_Low
TABLE 16-12: GET_CRC FORMAT

Field
Description
Op code
0x8
Operand
Not used
Address
Address where to start calculating the

CRC
Length
Length of buffer on which to calculate

the CRC, in number of bytes
Expected Response (2 words):
FIGURE 16-21:
GET_CRC RESPONSE
31
16
Last Command
15
0
Response Code
31
16
CRC_High
15
0
CRC_Low
DS61145L-page 40
PIC32
16.2.12
PROGRAM_CLUSTER COMMAND
16.2.13
PROGRAM_CLUSTER programs the specified number of

bytes to the specified address. The address must be
32-bit aligned, and the number of bytes must be a
multiple of a 32-bit word.
FIGURE 16-22:
PROGRAM_CLUSTER
COMMAND
31
The GET_DEVICEID command returns the hardware

ID of the device.
FIGURE 16-24:
Op code
16
Op code
15
0
Operand
0
Operand
31
TABLE 16-14: GET_DEVICEID FORMAT

16
Addr_High
15
Field
16
Length_High
15
0
Length_Low
0xA
Operand
Not used
FIGURE 16-25:
16
Last Command
15
Description
0
Device ID
Op code
0x9
Operand
Not used
Address
Start address for programming
Length
Length of area to program in number

of bytes
Note:
GET_DEVICEID
RESPONSE
31
TABLE 16-13: PROGRAM_CLUSTER FORMAT

Field
Description
Op code
Addr_Low
31
GET_DEVICEID
COMMAND
31
16
15
GET_DEVICEID COMMAND
If the PROGRAM_CLUSTER command fails,

the programmer should read the failing row
using the READ command from the Flash
memory. Next, the programmer should
compare the row received from Flash
memory to its local copy word-by-word to
determine the address where Flash
programming fails.
FIGURE 16-23:
PROGRAM_CLUSTER
RESPONSE
31
16
Last Command
15
0
Response Code
DS61145L-page 41
PIC32
16.2.14
CHANGE_CFG COMMAND
16.2.15
GET_CHECKSUM COMMAND
CHANGE_CFG is used by the probe to set various configuration settings for the PE. Currently, the single configuration setting determines which of the following
calculation methods the PE should use:
GET_CHECKSUM returns the sum of all the bytes

starting at the address argument up to the length
argument. The result is a 32-bit word.
Software CRC calculation method

Hardware calculation method
FIGURE 16-28:
CHANGE_CFG COMMAND
31
16
Op code
FIGURE 16-26:
CHANGE_CFG COMMAND
31
15
16
Op code
15
Operand
31
16
0
Operand
31
Addr_High
15
16
CRCFlag_High
15
Addr_Low
31
16
0
CRCFlag_Low
Length_High
15
0
Length_Low
TABLE 16-15: CHANGE_CFG FORMAT

Field
Description
Op code
0xB
Operand
Not used
CRCFlag
If the value is 0, the PE uses the

software CRC calculation method.
If the value is 1, the PE uses the
hardware CRC unit to calculate the
CRC.
TABLE 16-16: GET_CHECKSUM FORMAT

Field
FIGURE 16-27:
CHANGE_CFG RESPONSE
31
Op code
0x0C
Operand
Not used
Addr_High
High-order 16 bits of the 32-bit starting

address of the data to calculate the
checksum for.
Addr_Low
Low-order 16 bits of the 32-bit starting

address of the data to calculate the
checksum for.
16
Length_High High-order 16 bits of the 32-bit length

of data to calculate the checksum for
in bytes.
Length_Low
Last Command
15
Response Code
Note:
Description
The command, CHANGE_CFG, is not

available in PIC32MX1XX/2XX devices.
Low-order 16 bits of the 32-bit length

of data to calculate the checksum for
in bytes.
FIGURE 16-29:
GET_CHECKSUM
RESPONSE
31
16
Last Command
15
0
Response Code
31
16
Checksum_High
15
0
Checksum_Low
DS61145L-page 42
PIC32
16.2.16
QUAD_WORD_PROGRAM COMMAND
QUAD_WORD_PROGRAM instructs the PE to program

four, 32-bit words at the specified address. The
address must be an aligned four word boundary (bits 01 must be 0). If not, the command will return a FAIL
response value and no data will be programmed.
FIGURE 16-30:
Field
Op code
Not used
High-order 16 bits of the 32-bit starting
address.
16
Addr_Low
Low -order 16 bits of the 32-bit starting

address.
Data0_High
High-order 16 bits of Data Word 0.
Data0_Low
Low-order 16 bits of Data Word 0.
Data1_High
Data1_Low
Data2_High
Data2_Low
Data3_High
Data3_Low
Operand
31
16
Addr_High
15
0
Addr_Low
31
16
Data0_High
15
0
Data0_Low
31
16
Data1_High
15
FIGURE 16-31:
QUAD_WORD_PROGRAM
RESPONSE
31
0
Data1_Low
31
0x0C
Addr_High
Op code
15
Description
Operand
QUAD_WORD_PROGRAM
COMMAND
31
TABLE 16-17: QUAD_WORD_PROGRAM

FORMAT
16
Last Command
15
16
0
Response Code
Data2_High
15
0
Data2_Low
31
16
Data3_High
15
0
Data3_Low
DS61145L-page 43
PIC32
17.0
CHECKSUM
17.2
17.1
Theory
The mask value of a device Configuration is calculated

by setting all the unimplemented bits to 0 and all the
implemented bits to 1.
The checksum is calculated as the 32-bit summation of

all bytes (8-bit quantities) in program Flash, boot Flash
(except device Configuration Words), the Device ID
register with applicable mask, and the device Configuration Words with applicable masks. Next, the 2s
complement of the summation is calculated. This final
32-bit number is presented as the checksum.
REGISTER 17-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Mask Values
For example, Register 17-1 shows the DEVCFG0 register of the PIC32MX360F512L device. The mask value
for this register is:
mask_value_devcfg0 = 0x110FF00B
Table 17-1 lists the mask values of the four device Configuration registers and Device ID registers to be used
in the checksum calculations.
DEVCFG0 REGISTER OF PIC32MX360F512L

Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-0
r-1
r-1
R/P-1
r-1
r-1
r-1
R/P-1
CP
BWP
r-1
r-1
r-1
r-1
R/P-1
R/P-1
R/P-1
R/P-1
PWP19
PWP18
PWP17
PWP16
R/P-1
R/P-1
R/P-1
R/P-1
r-1
r-1
r-1
r-1
PWP15
PWP14
PWP13
PWP12
R/P-1
R/P-1
r-1
r-1
r-1
r-1
R/P-1
r-1
ICESEL
Legend:
R = Readable bit
-n = Value at POR
DS61145L-page 44
P = Programmable bit
W = Writable bit
1 = Bit is set
DEBUG<1:0>
r = Reserved bit
U = Unimplemented bit, read as 0
0 = Bit is cleared
x = Bit is unknown
PIC32
TABLE 17-1:
DEVICE CONFIGURATION REGISTER MASK VALUES OF CURRENTLY

SUPPORTED PIC32 DEVICES
Device
DEVCFG0
DEVCFG1
DEVCFG2
DEVCFG3
DEVID
All PIC32MX1XX Family
0x1100FC1F
0x03DFF7A7
0x0070077
0xF0000000
0x0FFFFFFF
All PIC32MX2XX Family
0x1100FC1F
0x03DFF7A7
0x0078777
0xF0000000
0x0FFFFFFF
All PIC32MX320/340/360 Family
0x110FF00B
0x009FF7A7
0x00070077
0x00000000
0x000FF000
0x110FF01F
0x03DFF7A7
0x00070077
0x30C70000
0x00FFFFFF
0x110FF00B
0x009FF7A7
0x00078777
0x00000000
0x000FF000
0x110FF01F
0x03DFF7A7
0x00078777
0xF0C70000
0x00FFFFFF
All PIC32MZ EC Family
0x7FFFFFFF
0xFFFFFFFF
0xFFFFFFFF
0xFFFF0000
0x0FFFFFFF
PIC32MX534F064H
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x0FFFF000
PIC32MX534F064L
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x0FFFF000
PIC32MX564F064H
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x0FFFF000
PIC32MX564F064L
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x0FFFF000
PIC32MX564F128H
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x0FFFF000
PIC32MX564F128L
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x0FFFF000
PIC32MX575F256H
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x000FF000
PIC32MX575F256L
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x000FF000
PIC32MX575F512H
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x000FF000
PIC32MX575F512L
0x110FF00F
0x009FF7A7
0x00078777
0xC4070000
0x000FF000
PIC32MX664F064H
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x0FFFF000
PIC32MX664F064L
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x0FFFF000
PIC32MX664F128H
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x0FFFF000
PIC32MX664F128L
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x0FFFF000
PIC32MX675F256H
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x000FF000
PIC32MX675F256L
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x000FF000
PIC32MX675F512H
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x000FF000
PIC32MX675F512L
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x000FF000
PIC32MX695F512H
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x000FF000
PIC32MX695F512L
0x110FF00F
0x009FF7A7
0x00078777
0xC3070000
0x000FF000
PIC32MX764F128H
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x0FFFF000
PIC32MX764F128L
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x0FFFF000
PIC32MX775F256H
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x000FF000
PIC32MX775F256L
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x000FF000
PIC32MX775F512H
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x000FF000
PIC32MX775F512L
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x000FF000
PIC32MX795F512H
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x000FF000
PIC32MX795F512L
0x110FF00F
0x009FF7A7
0x00078777
0xC7070000
0x000FF000
DS61145L-page 45
PIC32
17.3
Algorithm
An example of a high-level algorithm for calculating the

checksum for a PIC32 device is illustrated in Figure 17-1
to demonstrate one method to derive a checksum. This
is merely an example of how the actual calculations can
be accomplished, the method that is ultimately used is
left to the discretion of the software developer.
As stated earlier, the PIC32 checksum is calculated as
the 32-bit summation of all bytes (8-bit quantities) in
program Flash, boot Flash (except device
Configuration Words), the Device ID register with
applicable mask, and the device Configuration Words
with applicable masks.
FIGURE 17-1:
Next, the 2s complement of the summation is

calculated. This final 32-bit number is presented as the
checksum.
The mask values of the device Configuration and
Device ID registers are derived as described in the
previous section, Section 17.2 Mask Values.
Another noteworthy point is that the last four 32-bit
quantities in boot Flash are the device Configuration
registers. An arithmetic AND operation of these device
Configuration register values is performed with the
appropriate mask value, before adding their bytes to
the checksum.
Similarly, an arithmetic AND operation of the Device ID
register is performed with the appropriate mask value,
before adding its bytes to the checksum.
HIGH-LEVEL ALGORITHM FOR CHECKSUM CALCULATION
pic32_checksum
Read Program Flash, Boot Flash (including DEVCFG

registers) and DEVID register in tempBuffer
Apply DEVCFG and DEVID masks to appropriate

locations in tempBuffer
tmpChecksum (32-bit quantity) = 0
Finish processing all

bytes (8-bit quantities) in
tempBuffer?
No
tmpChecksum = tempChecksum + Current Byte Value

(8-bit quantity) in tmpBuffer
Yes
Checksum (32-bit quantity) = 2s complement
of tmpChecksum
Done
DS61145L-page 46
PIC32
The formula to calculate the checksum for a PIC32
device is provided in Equation 17-1.
EQUATION 17-1:
CHECKSUM FORMULA
Checksum = 2s complement PF + BF + DCR + DIR
Where,
PF = 32-bit summation of all bytes in Program Flash
BF = 32-bit summation of all bytes in boot Flash, except device Configuration registers
3
DCR = 32-bit summation of bytes MASK DEVCFGX & DEVCFGx
X = 0
DIR = 32-bit summation of bytes MASK DEVID & DEVID
MASKDEVCFGX = mask value from Table 17-1
MASKDEVID = mask value from Table 17-1
17.4
Example of Checksum Calculation
17.4.2
The following five sections demonstrate a checksum

calculation for the PIC32MX360F512L device using
Equation 17-1.
The size of the boot Flash is 12 KB, which equals

12288 bytes. However, the last 16 bytes are device
Configuration registers, which are treated separately.
Therefore, the number of bytes in boot Flash that we
consider in this step is 12272. Since the boot Flash is
assumed to be in erased state, the value of BF is
resolved through the following calculation:
The following assumptions are made for the purpose of

this checksum calculation example:
Program Flash and boot Flash are in the erased
state (all bytes are 0xFF)
Device Configuration is in the default state of the
device (no configuration changes are made)
BF = 0xFF + 0xFF + 12272 times

BF = 0x002FC010 (32-bit number)
To begin, each item on the right-hand side of the equation (PF, BF, DCR, DIR) is individually calculated. After
those values have been derived, the final value of the
checksum can be determined.
17.4.1
17.4.3
CALCULATING FOR DCR IN THE

CHECKSUM FORMULA
Since the device Configuration registers are left in their

default state, the value of the appropriate DEVCFG
register as read by the PIC32 core, its respective
mask value, the value derived from applying the mask,
and the 32-bit summation of bytes (all as shown in
Table 17-2) provide the total of the 32-bit summation of
bytes.
CALCULATING FOR PF IN THE

CHECKSUM FORMULA
The size of Program Flash is 512 KB, which equals

524288 bytes. Since the program Flash is assumed to
be in erased state, the value of PF is resolved through
the following calculation:
From Table 17-2, the value of DCR is:
PF = 0xFF + 0xFF + 524288 times
DCR = 0x000003D6 (32-bit number)
PF = 0x7F80000 (32-bit number)
TABLE 17-2:
CALCULATING FOR BF IN THE

CHECKSUM FORMULA
DCR CALCULATION EXAMPLE

POR Default Value & 32-Bit Summation of
Mask
Bytes
Register
POR Default Value
Mask
DEVCFG0
0x7FFFFFFF
0x110FF00B
0x110FF00B
0x0000011B
DEVCFG1
0xFFFFFFFF
0x009FF7A7
0x009FF7A7
0x0000023D
DEVCFG2
0xFFFFFFFF
0x00070077
0x00070077
0x0000007E
DEVCFG3
0xFFFFFFFF
0x00000000
0x00000000
Total of the 32-bit Summation of Bytes =
0x00000000
0x000003D6
DS61145L-page 47
PIC32
17.4.4
CALCULATING FOR DIR IN THE

CHECKSUM FORMULA
The value of Device ID register, its mask value, the

value derived from applying the mask, and the 32-bit
summation of bytes are shown in Table 17-3.
From Table 17-3, the value of DIR is:
DIR = 0x00000083 (32-bit number.)
TABLE 17-3:
17.4.5
DIR CALCULATION EXAMPLE
Register
POR Default Value
Mask
POR Default Value

& Mask
32-Bit Summation of
Bytes
DEVID
0x00938053
0x000FF000
0x00038000
0x00000083
COMPLETING THE PIC32

CHECKSUM CALCULATION
The values derived in previous sections (PF, BF, DCR,

DIR) are used to calculate the checksum value. First,
perform the 32-bit summation of the PF, BF, DCR and
DIR as derived in previous sections and store it in a
variable, called temp, as shown in Example 17-1.
EXAMPLE 17-1:
1.
CHECKSUM CALCULATION PROCESS
First, temp = PF + BF + DCR + DIR, which translates to:

temp = 0x7F80000 + 0x002FC010 + 0x000003D6 + 0x00000083
2.
3.
Adding all four values results in temp being equal to 0x0827C406

Next, the 1s complement of temp, called temp1, is calculated:
4.
Finally, the 2s complement of temp is the checksum:
temp1 = 1s complement (temp), which is now equal to 0xF7D83B96

Checksum = 2s complement (temp), which is Checksum = temp1 + 1, resulting in 0xF7D83B97
17.4.6
CHECKSUM VALUES WHILE

DEVICE IS CODE-PROTECTED
Since the device Configuration Words are not readable

while the PIC32 devices are in code-protected state,
the checksum values are zeros for all devices.
DS61145L-page 48
PIC32
18.0
CONFIGURATION MEMORY
AND DEVICE ID
PIC32 devices include several features intended to

maximize application flexibility and reliability, and
minimize cost through elimination of external
components. These features are configurable through
specific Configuration bits for each device.
Refer to the Special Features chapter in the specific
device data sheet for a full list of available features,
Configuration bits, and the Device ID register.
See Table 18-4 for a full list of Device ID and
revision number for specific devices.
18.1
Device Configuration
In PIC32 devices, the Configuration Words select various

device configurations that are set at device Reset prior to
execution of any code. These values are located at the
highest locations of Boot Flash Memory (BFM) and since
they are part of the program memory, are included in the
programming file along with executable code and program constants. The names and locations of these Configuration Words are listed in Table 18-1 through
Table 18-3.
During programming, a Configuration Word can be

programmed a maximum of two times for PIC32MX
devices and only one time for PIC32MZ EC devices
before a page erase must be performed.
After programming the Configuration Words, a device
Reset will cause the new values to be loaded into the
Configuration registers. Because of this, the programmer
should program the Configuration Words just prior to verification of the device. The final step is programming the
code protection Configuration Word.
These Configuration Words determine the oscillator
source. If using the 2-wire Enhanced ICSP mode the
Configuration Words are ignored and the device will
always use the FRC; however, in 4-wire mode this is
not the case. If an oscillator source is selected by the
Configuration Words that is not present on the device
after reset, the programmer will not be able to perform
Flash operations on the device after it is reset. See the
Special Features chapter in the specific device data
sheet for details regarding oscillator selection using the
Configuration Words.
Additionally, Table 18-3 includes Configuration Words for

PIC32MZ EC family devices with dual boot and dual
panel Flash. Refer to Section 3. Memory Organization (DS61115) in the PIC32 Family Reference
Manual for a detailed description of the dual boot
regions.
TABLE 18-1:
DEVCFG LOCATIONS
Configuration Word
Physical Address
DEVCFG0
DEVCFG1
DEVCFG2
DEVCFG3
0x1FC02FFC
0x1FC02FF8
0x1FC02FF4
0x1FC02FF0
TABLE 18-2:
DEVCFG LOCATIONS FOR

PIC32MX1X0 AND
PIC32MX20X DEVICES ONLY
Configuration Word
Physical Address
DEVCFG0
DEVCFG1
DEVCFG2
DEVCFG3
0x1FC00BFC
0x1FC00BF8
0x1FC00BF4
0x1FC00BF0
On Power-on Reset (POR), or any reset, the Configuration Words are copied from the boot Flash memory to
their corresponding Configuration registers. A Configuration bit can only be programmed = 0 (unprogrammed
state = 1).
DS61145L-page 49
PIC32
TABLE 18-3:
CONFIGURATION WORD LOCATIONS FOR PIC32MZ EC FAMILY DEVICES

Register Physical Address
Configuration Word
(see Note 1)
Fixed Boot
Region 1
Fixed Boot
Region 2
Active Boot
Alias Region
(see Note 2)
Inactive Boot
Alias Region
(see Note 2)
Boot Sequence Number
0x1FC4FFF0
0x1FC6FFF0
0x1FC0FFF0
0x1FC2FFF0
Code Protection
0x1FC4FFD0
0x1FC6FFD0
0x1FC0FFD0
0x1FC2FFD0
DEVCFG0
0x1FC4FFCC
0x1FC6FFCC
0x1FC0FFCC
0x1FC2FFCC
DEVCFG1
0x1FC4FFC8
0x1FC6FFC8
0x1FC0FFC8
0x1FC2FFC8
DEVCFG2
0x1FC4FFC4
0x1FC6FFC4
0x1FC0FFC4
0x1FC2FFC4
DEVCFG3
0x1FC4FFC0
0x1FC6FFC0
0x1FC0FFC0
0x1FC2FFC0
Alternate Boot Sequence Number
0x1FC4FF70
0x1FC6FF70
0x1FC0FF70
0x1FC2FF70
Alternate Code Protection
0x1FC4FF50
0x1FC6FF50
0x1FC0FF50
0x1FC2FF50
Alternate DEVCFG0
0x1FC4FF4C
0x1FC6FF4C
0x1FC0FF4C
0x1FC2FF4C
Alternate DEVCFG1
0x1FC4FF48
0x1FC6FF48
0x1FC0FF48
0x1FC2FF48
Alternate DEVCFG2
0x1FC4FF44
0x1FC6FF44
0x1FC0FF44
0x1FC2FF44
Alternate DEVCFG3
0x1FC4FF40
0x1FC6FF40
0x1FC0FF40
0x1FC2FF40
Note 1:
2:
Each of the following Configuration Word Groups should be programmed using the
QUAD_WORD_PROGRAM command to insure proper ECC configuration:
Boot Sequence Number (single quad word programming operation)
Code Protection (single quad word programming operation)
DEVCFG3, DEVCFG2, DEVCFG1, and DEVCFG0 (single quad word programming operation)
Alternate Boot Sequence Number (single Quad Word programming operation)
Alternate Code Protection (single Quad Word programming operation)
Alternate DEVCFG3, alternate DEVCFG2, alternate DEVCFG1, and alternate DEVCFG0 (single quad
word programming operation)
Active/Inactive boot alias selections are assumed for an unprogrammed device where Fixed Region 1 is
active and Fixed Region 2 is inactive. Refer to Section 3. Memory Organization (DS61115) for a
detailed description of the alias boot regions.
DS61145L-page 50
PIC32
18.1.1
CONFIGURATION REGISTER
PROTECTION
To prevent inadvertent Configuration bit changes during code execution, all programmable Configuration
bits are write-once. After a bit is initially programmed
during a power cycle, it cannot be written to again.
TABLE 18-4:
Changing a device configuration requires changing the

Configuration data in the boot Flash memory, and
cycling power to the device.
To ensure integrity of the 128-bit data, a comparison is
made between each Configuration bit and its stored
complement continuously. If a mismatch is detected, a
Configuration Mismatch Reset is generated, which
causes a device Reset.
DEVICE IDs AND REVISION

Device
PIC32MX110F016B
PIC32MX110F016C
PIC32MX110F016D
PIC32MX120F032B
PIC32MX120F032C
PIC32MX120F032D
PIC32MX130F064B
PIC32MX130F064C
PIC32MX130F064D
PIC32MX150F128B
PIC32MX150F128C
PIC32MX150F128D
PIC32MX210F016B
PIC32MX210F016C
PIC32MX210F016D
PIC32MX220F032B
PIC32MX220F032C
PIC32MX220F032D
PIC32MX230F064B
PIC32MX230F064C
PIC32MX230F064D
PIC32MX250F128B
PIC32MX250F128C
PIC32MX250F128D
PIC32MX330F064H
PIC32MX330F064L
PIC32MX430F064H
PIC32MX430F064L
PIC32MX350F128H
PIC32MX350F128L
PIC32MX450F128H
PIC32MX450F128L
PIC32MX350F256H
PIC32MX350F256L
PIC32MX450F256H
PIC32MX450F256L
PIC32MX370F512H
PIC32MX370F512L
PIC32MX470F512H
PIC32MX470F512L
DEVID Register Value
Revision ID and Silicon Revision
0x04A07053
0x04A09053
0x04A0B053
0x04A06053
0x04A08053
0x04A0A053
0x04D07053
0x04D09053
0x04D0B053
0x04D06053
0x04D08053
0x04D0A053
0x04A01053
0x04A03053
0x04A05053
0x04A00053
0x04A02053
0x04A04053
0x04D01053
0x04D03053
0x04D05053
0x04D00053
0x04D02053
0x04D04053
0x05600053
0x05601053
0x05602053
0x05603053
0x0570C053
0x0570D053
0x0570E053
0x0570F053
0x05704053
0x05705053
0x05706053
0x05707053
0x05808053
0x05809053
0x0580A053
0x0580B053
0x0 A0 Revision
DS61145L-page 51
PIC32
TABLE 18-4:
DEVICE IDs AND REVISION (CONTINUED)

Device
PIC32MX360F512L
0x0938053
PIC32MX360F256L
PIC32MX340F128L
PIC32MX320F128L
PIC32MX340F512H
PIC32MX340F256H
PIC32MX340F128H
PIC32MX320F128H
PIC32MX320F064H
PIC32MX320F032H
PIC32MX460F512L
PIC32MX460F256L
PIC32MX440F128L
PIC32MX440F256H
PIC32MX440F512H
PIC32MX440F128H
PIC32MX420F032H
PIC32MX534F064H
PIC32MX534F064L
PIC32MX564F064H
PIC32MX564F064L
PIC32MX564F128H
PIC32MX564F128L
PIC32MX575F256H
PIC32MX575F256L
PIC32MX575F512H
PIC32MX575F512L
PIC32MX664F064H
PIC32MX664F064L
PIC32MX664F128H
PIC32MX664F128L
PIC32MX675F256H
PIC32MX675F256L
PIC32MX675F512H
PIC32MX675F512L
PIC32MX695F512H
PIC32MX695F512L
PIC32MX764F128H
PIC32MX764F128L
PIC32MX775F256H
PIC32MX775F256L
PIC32MX775F512H
PIC32MX775F512L
PIC32MX795F512H
PIC32MX795F512L
0x0934053
0x092D053
0x092A053
0x0916053
0x0912053
0x090D053
0x090A053
0x0906053
0x0902053
0x0978053
0x0974053
0x096D053
0x0952053
0x0956053
0x094D053
0x0942053
0x4400053
0x440C053
0x4401053
0x440D053
0x4403053
0x440F053
0x4317053
0x4333053
0x4309053
0x430F053
0x4405053
0x4411053
0x4407053
0x4413053
0x430B053
0x4305053
0x430C053
0x4311053
0x4325053
0x4341053
0x440B053
0x4417053
0x4303053
0x4312053
0x430D053
0x4306053
0x430E053
0x4307053
DS61145L-page 52
0x3 B2 Revision
0x4 B3 Revision
0x5 B4 Revision
0x5 B6 Revision
0x0 A0 Revision
0x1 A1 Revision
PIC32
TABLE 18-4:
DEVICE IDs AND REVISION (CONTINUED)

Device
PIC32MZ0256ECE064
PIC32MZ0256ECE100
PIC32MZ0256ECE124
PIC32MZ0256ECE144
PIC32MZ0256ECF064
PIC32MZ0256ECF100
PIC32MZ0256ECF124
PIC32MZ0256ECF144
PIC32MZ0512ECE064
PIC32MZ0512ECE100
PIC32MZ0512ECE124
PIC32MZ0512ECE144
PIC32MZ0512ECF064
PIC32MZ0512ECF100
PIC32MZ0512ECF124
PIC32MZ0512ECF144
PIC32MZ1024ECE064
PIC32MZ1024ECE100
PIC32MZ1024ECE124
PIC32MZ1024ECE144
PIC32MZ1024ECF064
PIC32MZ1024ECF100
PIC32MZ1024ECF124
PIC32MZ1024ECF144
PIC32MZ1024ECG064
PIC32MZ1024ECG100
PIC32MZ1024ECG124
PIC32MZ1024ECG144
PIC32MZ1024ECH064
PIC32MZ1024ECH100
PIC32MZ1024ECH124
PIC32MZ1024ECH144
PIC32MZ2048ECG064
PIC32MZ2048ECG100
PIC32MZ2048ECG124
PIC32MZ2048ECG144
PIC32MZ2048ECH064
PIC32MZ2048ECH100
PIC32MZ2048ECH124
PIC32MZ2048ECH144

0x05100053
0x0510A053
0x05114053
0x0511E053
0x05105053
0x0510F053
0x05119053
0x05123053
0x05101053
0x0510B053
0x05115053
0x0511F053
0x05106053
0x05110053
0x0511A053
0x05124053
0x05102053
0x0510C053
0x05116053
0x05120053
0x05107053
0x05111053
0x0511B053
0x05125053
0x05103053
0x0510D053
0x05117053
0x05121053
0x05108053
0x05112053
0x0511C053
0x05126053
0x05104053
0x0510E053
0x05118053
0x05122053
0x05109053
0x05113053
0x0511D053
0x05127053
0x0 A0 Revision
0x0 A0 Revision
DS61145L-page 53
PIC32
18.2 Device Code Protection bit (CP)
18.3 Program Write Protection bits (PWP)
The PIC32 family of devices feature code protection, which when enabled, prevents reading of Flash
memory by an external programming device. Once
code protection is enabled, it can only be disabled
by erasing the device with the Chip Erase command
(MCHP_ERASE).
The PIC32 families of devices include write protection

features, which prevent designated boot and program
Flash regions from being erased or written during
program execution.
When programming a device that has opted to utilize code protection, the programming device must
perform verification prior to enabling code protection. Enabling code protection should be the last step
of the programming process. Location of the code
protection enable bits vary by device. Refer to the
Special Features chapter in the specific device
data sheet for details.
Note:
Once code protection is enabled, the

Flash memory can no longer be read and
can only be disabled by an external programmer using the Chip Erase Command
(MCHP_ERASE).
DS61145L-page 54
In PIC32MX devices, write protection is implemented in

Configuration memory by the Device Configuration
Words, while in PIC32MZ EC devices, this feature is
implemented through Special Function Registers
(SFRs) in the Flash controller.
When write protection is implemented by Device
Configuration Words, the write protection register
should only be written when all boot and program Flash
memory has been programmed. Refer to the Special
Features chapter in the specific device data sheet for
details.
If write protection is implemented using SFRs, certain
steps may be required during initialization of the device
by the external programmer prior to programming
Flash regions. Refer to the Flash Program Memory
chapter in the specific device data sheet for details.
PIC32
19.0
TAP CONTROLLERS
TABLE 19-1:
Command
MCHP TAP INSTRUCTIONS

Value
Description
MTAP_COMMAND
5h0x07
TDI and TDO connected to MCHP Command Shift register (See Table 19-2).
MTAP_SW_MTAP
5h0x04
Switch TAP controller to MCHP TAP controller.
MTAP_SW_ETAP
5h0x05
Switch TAP controller to EJTAG TAP controller.
MTAP_IDCODE
5h0x01
Select Chip Identification Data register.
19.1
Microchip TAP Controllers (MTAP)
19.1.1
MTAP_COMMAND INSTRUCTION
MTAP_COMMAND selects the MCHP Command Shift

register. See Table 19-2 for available commands.
19.1.1.1
MCHP_STATUS INSTRUCTION
MCHP_STATUS returns the 8-bit Status value of the

Microchip TAP controller. Table 19-3 shows the format
of the Status value returned.
19.1.1.2
MCHP_ASSERT_RST INSTRUCTION
MCHP_ASSERT_RST performs a persistent device

Reset. It is similar to asserting and holding MCLR. Its
associated Status bit is DEVRST.
19.1.1.3
MCHP_DE_ASSERT_RST
INSTRUCTION
MCHP_DE_ASSERT_RST removes the persistent

device Reset. It is similar to de-asserting MCLR. Its
associated Status bit is DEVRST.
19.1.1.4
MCHP_FLASH_DISABLE
INSTRUCTION
MCHP_FLASH_DISABLE clears the FAEN bit which

controls processor accesses to the Flash memory. The
FAEN bits state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
Note:
19.1.2
This command is not required

PIC32MZ EC family devices.
for
MTAP_SW_MTAP INSTRUCTION
MTAP_SW_MTAP switches the TAP instruction set to the

MCHP TAP instruction set.
19.1.3
MTAP_SW_ETAP INSTRUCTION
MTAP_SW_ETAP effectively switches the TAP

instruction set to the EJTAG TAP instruction set. It does
this by holding the EJTAG TAP controller in the Run
Test/Idle state until a MTAP_SW_ETAP instruction is
decoded by the MCHP TAP controller.
19.1.4
MCHP_ERASE INSTRUCTION
MCHP_ERASE performs a Chip Erase. The CHIP_

ERASE command sets an internal bit that requests
the Flash Controller to perform the erase. Once the
controller becomes busy, as indicated by FCBUSY
(Status bit), the internal bit is cleared.
19.1.1.5
19.1.1.6
MTAP_IDCODE INSTRUCTION
MTAP_IDCODE returns the value stored in the DEVID

register.
MCHP_FLASH_ENABLE
INSTRUCTION
MCHP_FLASH_ENABLE sets the FAEN bit, which controls processor accesses to the Flash memory. The
FAEN bits state is returned in the field of the same
name. This command has no effect if CPS = 0. This
command requires a NOP to complete.
Note:
This command is not required

PIC32MZ EC family devices.
for
DS61145L-page 55
PIC32
TABLE 19-2:
MTAP_COMMAND DR COMMANDS
Command
Value
Description
MCHP_STATUS
8h0x00
NOP and return Status.
MCHP_ASSERT_RST
8h0xD1
Requests the reset controller to assert device Reset.
MCHP_DE_ASSERT_RST
8h0xD0
Removes the request for device Reset, which causes the reset
controller to de-assert device Reset if there is no other source
requesting Reset (i.e., MCLR).
MCHP_ERASE
8h0xFC
Cause the Flash controller to perform a Chip Erase.
MCHP_FLASH_ENABLE(1)
8h0xFE
Enables fetches and loads to the Flash (from the processor).
MCHP_FLASH_DISABLE(1)
8h0xFD
Disables fetches and loads to the Flash (from the processor).
Note 1:
This command is not required for PIC32MZ EC family devices.
TABLE 19-3:
MCHP STATUS VALUE
Bit
Range
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7:0
CPS
NVMERR(1)
CFGRDY
FCBUSY
FAEN(2)
DEVRST
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
CPS: Code-Protect State bit

1 = Device is not code-protected
0 = Device is code-protected
Unimplemented: Read as 0
NVMERR: NVMCON Status bit(1)
1 = An Error occurred during NVM operation
0 = An Error did not occur during NVM operation
CFGRDY: Code-Protect State bit
1 = Configuration has been read and CP is valid
0 = Configuration has not been read
FCBUSY: Flash Controller Busy bit
1 = Flash controller is busy (Erase is in progress)
0 = Flash controller is not busy (either erase has not started or it has finished)
FAEN: Flash Access Enable bit(2)
This bit reflects the state of CFGCON.FAEN.
1 = Flash access is enabled
0 = Flash access is disabled (i.e., processor accesses are blocked)
DEVRST: Device Reset State bit
1 = Device Reset is active
0 = Device Reset is not active
This bit is not implemented in PIC32MX320/340/360/420/440/460 devices.
This bit is not implemented in PIC32MZ EC family devices.
TABLE 19-4:
EJTAG TAP INSTRUCTIONS
Command
ETAP_ADDRESS
Value
5h0x08
Description
Select Address register.
ETAP_DATA
5h0x09
Select Data register.
ETAP_CONTROL
5h0x0A
Select EJTAG Control register.
ETAP_EJTAGBOOT
5h0x0C
Set EjtagBrk, ProbEn and ProbTrap to 1 as the reset value.
ETAP_FASTDATA
5h0x0E
Selects the Data and Fastdata registers.
DS61145L-page 56
PIC32
19.2
19.2.1
EJTAG TAP Controller

ETAP_ADDRESS COMMAND
ETAP_ADDRESS selects the Address register. The

read-only Address register provides the address for a
processor access. The value read in the register is
valid if a processor access is pending, otherwise the
value is undefined.
The two or three Least Significant Bytes (LSBs) of the
register are used with the Psz field from the EJTAG
Control register to indicate the size and data position of
the pending processor access transfer. These bits are
not taken directly from the address referenced by the
load/store.
19.2.2
ETAP_DATA COMMAND
ETAP_DATA selects the Data register. The read/write

Data register is used for op code and data transfers
during processor accesses. The value read in the Data
register is valid only if a processor access for a write is
pending, in which case the Data register holds the store
value. The value written to the Data register is only
used if a processor access for a pending read is
finished afterwards; in which case, the data value
written is the value for the fetch or load. This behavior
implies that the Data register is not a memory location
where a previously written value can be read
afterwards.
19.2.3
ETAP_CONTROL COMMAND
ETAP_CONTROL selects the Control register. The

EJTAG Control register (ECR) handles processor Reset
and soft Reset indication, Debug mode indication,
access start, finish and size, and read/write indication.
The ECR also provides the following features:
Controls debug vector location and indication of
serviced processor accesses
Allows a debug interrupt request
Indicates a processor low-power mode
Allows implementation-dependent processor and
peripheral Resets
19.2.3.1
EJTAG Control Register (ECR)
The EJTAG Control register (see Register 19-1) is not

updated/written in the Update-DR state unless the
Reset occurred; that is ROCC (bit 31) is either already
0 or is written to 0 at the same time. This condition
ensures proper handling of processor accesses after a
Reset.
Reset of the processor can be indicated through the
ROCC bit in the TCK domain a number of TCK cycles
after it is removed in the processor clock domain in
order to allow for proper synchronization between the
two clock domains.
Bits that are Read/Write (R/W) in the register return
their written value on a subsequent read, unless other
behavior is defined.
Internal synchronization ensures that a written value is
updated for reading immediately afterwards, even
when the TAP controller takes the shortest path from
the Update-DR to Capture-DR state.
DS61145L-page 57
PIC32
REGISTER 19-1:
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
R/W-0
R-0
R-0
Rocc
R-0
bit 17
bit 16
bit 15
bit 14
bit 13
bit 12
bit 11-4
bit 3
bit 2-0
Note 1:
Bit
Bit
28/20/12/4 27/19/11/3
Psz<1:0>
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R-0
R-0
R/W-0
R-0
R/W-0
VPED
Doze
Halt
PerRst
PrnW
PrACC
PrRst
R/W-0
R/W-0
U-0
R/W-0
U-0
U-0
U-0
U-0
ProbEn
ProbTrap
EjtagBrk
U-0
U-0
U-0
U-0
R-0
U-0
U-0
U-0
DM
Legend:
R = Readable bit
-n = Value at POR
bit 31-29
bit 28-24
bit 23-19
bit 18
ECR: EJTAG CONTROL REGISTER
W = Writable bit
1 = Bit is set
U = Unimplemented bit, read as 0

0 = Bit is cleared
x = Bit is unknown
See Note 1
See Note 1
PrACC: Pending Processor Access and Control bit
This bit indicates a pending processor access and controls finishing of a pending processor access. A write
of 0 finishes processor access if pending. A write of 1 is ignored. A successful FASTDATA access will clear
this bit.
1 = Pending processor access
0 = No pending preprocessor access
See Note 1
ProbEn: Processor Access Service Control bit
This bit controls where the probe handles accesses to the DMSEG segment through servicing of processor
accesses.
1 = Probe services processor accesses
0 = Probe does not service processor access
ProbTrap: Debug Exception Vector Control Location bit
This bit controls the location of the debug exception vector.
1 = 0xFF200200
0 = 0xBFC00480
EjtagBrk: Debug Interrupt Exception Request bit
This bit requests a debug interrupt exception to the processor when this bit is written as 1. A write of 0 is
ignored.
1 = A debug interrupt exception request is pending
0 = A debug interrupt exception request is not pending
See Note 1
For descriptions of these bits, please refer to the EJTAG Control Register Field Descriptions in the EJTAG
Specification (MD00047), which is available from MIPS Technologies, Inc. (www.mips.com).
DS61145L-page 58
PIC32
19.2.4
ETAP_EJTAGBOOT COMMAND
The ETAP_EJTAGBOOT command causes the

processor to fetch code from the debug exception
vector after a reset. This allows the programmer to
send instructions to the processor to execute, instead
of the processor fetching them from the normal reset
vector. The Reset value of the EjtagBrk, ProbTrap, and
ProbE bits follows the setting of the internal
EJTAGBOOT indication.
If the EJTAGBOOT instruction has been given, and the
internal EJTAGBOOT indication is active, then the
Reset value of the three bits is set (1), otherwise the
Reset value is clear (0).
The results of setting these bits are:
Setting the EjtagBrk causes a Debug interrupt
exception to be requested right after the
processor Reset from the EJTAGBOOT instruction
The debug handler is executed from the EJTAG
memory because ProbTrap is set to indicate
debug vector in EJTAG memory at 0xFF200200
Service of the processor access is indicated
because ProbEn is set
With this configuration in place, an interrupt exception
will occur and the processor will fetch the handler from
the DMSEG at 0xFF200200. Since ProbEn is set, the
processor will wait for the instruction to be provided by
the probe.
19.2.5
ETAP_FASTDATA COMMAND
The ETAP_FASTDATA command provides a

mechanism for quickly transferring data between the
processor and the probe. The width of the Fastdata
register is one bit. During a fast data access, the
Fastdata register is written and read (i.e., a bit is shifted
in and a bit is shifted out). During a fast data access,
the Fastdata register value shifted in specifies whether
the fast data access should be completed or not. The
value shifted out is a flag that indicates whether the fast
data access was successful or not (if completion was
requested). The FASTDATA access is used for efficient
block transfers between the DMSEG segment (on the
probe) and target memory (on the processor). An
upload is defined as a sequence that the processor
loads from target memory and stores to the DMSEG
segment. A download is a sequence of processor
loads from the DMSEG segment and stores to target
memory. The Fastdata area specifies the legal range
of DMSEG segment addresses (0xFF200000 to
0xFF20000F) that can be used for uploads and
downloads. The Data and Fastdata registers (selected
with the FASTDATA instruction) allow efficient
completion of pending Fastdata area accesses.
During Fastdata uploads and downloads, the
processor will stall on accesses to the Fastdata area.
The PrAcc (processor access pending bit) will be 1
indicating the probe is required to complete the access.
Both upload and download accesses are attempted by
shifting in a zero SPrAcc value (to request access
completion) and shifting out SPrAcc to see if the
attempt will be successful (i.e., there was an access
pending and a legal Fastdata area address was used).
Downloads will also shift in the data to be used to
satisfy the load from the DMSEG segment Fastdata
area, while uploads will shift out the data being stored
to the DMSEG segment Fastdata area.
As noted above, two conditions must be true for the
Fastdata access to succeed. These are:
PrAcc must be 1 (i.e., there must be a pending
processor access)
The Fastdata operation must use a valid Fastdata
area address in the DMSEG segment
(0xFF200000 to 0xFF20000F)
DS61145L-page 59
PIC32
20.0
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
TABLE 20-1:
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Standard Operating Conditions

Operating Temperature: 0C to +70C. Programming at +25C is recommended.
Param.
Symbol
No.
D111
Characteristic
Min.
Max.
Units
Conditions
VDD
Supply Voltage During Programming
See Note 1
D113
IDDP
Supply Current During Programming
mA
See Note 1
D114
IPEAK
Instantaneous Peak Current During Start-up
mA
See Note 1
D031
VIL
Input Low Voltage
See Note 1
D041
VIH
Input High Voltage
See Note 1
D080
VOL
Output Low Voltage
See Note 1
D090
VOH
Output High Voltage
See Note 1
D012
CIO
Capacitive Loading on I/O pin (PGEDx)
pF
See Note 1
D013
CF
Filter Capacitor Value on VCAP
See Note 1
P1
TPGC
Serial Clock (PGECx) Period
100
ns
P1A
TPGCL
Serial Clock (PGECx) Low Time
40
ns
P1B
TPGCH
Serial Clock (PGECx) High Time
40
ns
P6
TSET2
VDD Setup Time to MCLR
100
ns
P7
THLD2
Input Data Hold Time from MCLR
500
ns
P9A
TDLY4
PE Command Processing Time
40
P9B
TDLY5
Delay between PGEDx by the PE to PGEDx

Released by the PE
15
P11
TDLY7
Chip Erase Time
ms
See Note 1
P12
TDLY8
Page Erase Time
ms
See Note 1
See Note 1
P13
TDLY9
Row Programming Time
ms
P14
TR
MCLR Rise Time to Enter ICSP mode
1.0
P15
TVALID
Data Out Valid from PGECx
10
ns
P16
TDLY8
Delay between Last PGECx and MCLR
P17
THLD3
MCLR to VDD
100
ns
P18
TKEY1
Delay from First MCLR to First PGECx for Key

Sequence on PGEDx
40
ns
P19
TKEY2
Delay from Last PGECx for Key Sequence on

PGEDx to Second MCLR
40
ns
P20
TMCLRH MCLR High Time
500
Note 1:
Refer to the Electrical Characteristics chapter in the specific device data sheet for the Minimum and
Maximum values for this parameter.
DS61145L-page 60
PIC32
APPENDIX A:
FIGURE A-1:
PIC32 FLASH
MEMORY MAP
FLASH MEMORY MAP

0x1D000000
APPENDIX B:
HEX FILE FORMAT
Flash programmers process the standard hexadecimal

(hex) format used by the Microchip development tools.
The format supported is the Intel HEX32 Format
(INHX32). Please refer to Section 1.75 Hex file
Formats in the MPASM Assembler, MPLINK
Object Linker, MPLIB Object Librarian Users Guide
(DS33014) for more information about hex file formats.
The basic format of the hex file is:
:BBAAAATTHHHH...HHHHCC
PFM
Each data record begins with a 9-character prefix and

always ends with a 2-character checksum. All records
begin with :, regardless of the format. The individual
elements are described below.
Program Flash Memory
0x1D007FFF
0x1F000000
0x1F001FFF
Because the Intel hex file format is byte-oriented, and

the 16-bit program counter is not, program memory
sections require special treatment. Each 24-bit
program word is extended to 32 bits by inserting a socalled phantom byte. Each program memory
address is multiplied by 2 to yield a byte address.
0x1F002FF0
As an example, a section that is located at 0x100 in

program memory will be represented in the hex file as
0x200.
BFM
Boot Page 0
Boot Page 1
Boot Page 2
Debug Page
Configuration Words
(4 x 32 bits)
Note:
BB is a two-digit hexadecimal byte count

representing the number of data bytes that appear
on the line. Divide this number by two to get the
number of words per line.
AAAA is a four-digit hexadecimal address
representing the starting address of the data
record. Format is high byte first followed by low
byte. The address is doubled because this format
only supports 8 bits. Divide the value by two to
find the real device address.
TT is a two-digit record type that will be 00 for
data records, 01 for end-of-file records and 04
for extended-address record.
HHHH is a four-digit hexadecimal data word.
Format is low byte followed by high byte. There
will be BB/2 data words following TT.
CC is a two-digit hexadecimal checksum that is
the 2s complement of the sum of all the
preceding bytes in the line record.
0x1F002FFF
The memory map shown is for reference

only. Refer to the Memory Organization
chapter in the specific device data sheet for
the memory map for your device.
The hex file will be produced with the following

contents:
:020000040000fa
:040200003322110096
:00000001FF
Notice that the data record (line 2) has a load
address of 0200, while the source code specified
address 0x100. Note also that the data is
represented in little-endian format, meaning the
Least Significant Byte appears first. The phantom
byte appears last, just before the checksum.
DS61145L-page 61
PIC32
APPENDIX C:
REVISION HISTORY
Revision A (August 2007)

This is the initial released version of the document.
Revision B (February 2008)

Update records for this revision are not available.
Revision C (April 2008)

Revision D (May 2008)

Revision E (July 2009)

This version of the document includes the following
additions and updates:
Minor changes to style and formatting have been
incorporated throughout the document
Added the following devices:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
Updated MCLR pulse line to show active-high
(P20) in Figure 7-1
Updated Step 7 of Table 11-1 to clarify repeat of
the last instruction in the step
The following instructions in Table 13-1 were
updated:
- Seventh, ninth and eleventh instructions in
Step 1
- All instructions in Step 2
- First instruction in Step 3
- Third instruction in Step 4
Added the following devices to Table 17-1:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX575F512L
- PIC32MX675F512H
- PIC32MX675F512L
- PIC32MX795F512H
- PIC32MX795F512L
Updated address values in Table 17-2
DS61145L-page 62
Revision E (July 2009) (Continued)

Added the following devices to Table 17-5:
- PIC32MX565F256H
- PIC32MX575F512H
- PIC32MX675F512H
- PIC32MX795F512H
- PIC32MX575F512L
- PIC32MX675F512L
- PIC32MX795F512L
Added Notes 1-3 and the following bits to the
DEVCFG - Device Configuration Word Summary
and the DEVCFG3: Device Configuration Word 3
(see Table 18-1 and Register ):
- FVBUSIO
- FUSBIDIO
- FCANIO
- FETHIO
- FMIIEN
- FPBDIV<1:0>
- FJTAGEN
Updated the DEVID Summary (see Table 18-1)
Updated ICESEL bit description and added the
FJTAGEN bit in DEVCFG0: Device Configuration
Word 0 (see Register 16-1)
Updated DEVID: Device and Revision ID register
Added Device IDs and Revision table (Table 18-4)
Added MCLR High Time (parameter P20) to
Table 20-1
Added Appendix B: Hex File Format and
Appendix D: Revision History
Revision F (April 2010)

The following global bit name changes were
made:
- NVMWR renamed as WR
- NVMWREN renamed as WREN
- NVMERR renamed as WRERR
- FVBUSIO renamed as FVBUSONIO
- FUPLLEN renamed as UPLLEN
- FUPLLIDIV renamed as UPLLIDIV
- POSCMD renamed as POSCMOD
Updated the PIC32MX family data sheet
references in the fourth paragraph of Section 2.0
Programming Overview
Updated the note in Section 5.2.2 2-Phase
ICSP
Updated the Initiate Flash Row Write Op Codes and
instructions (see steps 4, 5 and 6 in Table 13-1)
PIC32
Revision F (April 2010) (Continued)
Added the following devices:
- PIC32MX534F064H
- PIC32MX534F064L
- PIC32MX564F064H
- PIC32MX564F064L
- PIC32MX564F128H
- PIC32MX564F128L
- PIC32MX575F256L
- PIC32MX664F064H
- PIC32MX664F064L
- PIC32MX664F128H
- PIC32MX664F128L
- PIC32MX675F256H
- PIC32MX675F256L
- PIC32MX695F512H
- PIC32MX605F512L
- PIC32MX764F128H
- PIC32MX764F128L
- PIC32MX775F256H
- PIC32MX775F256L
- PIC32MX775F512H
- PIC32MX775F512L
Revision G (August 2010)

This revision of the document includes the following
updates:
Updated Step 3 in Table 11-1: Download the PE
Minor corrections to formatting and text have
been incorporated throughout the document
Revision H (April 2011)

Updates to formatting and minor typographical
changes have been incorporated throughout the
document
The following devices were added:
- PIC32MX110F016B
- PIC32MX110F016C
- PIC32MX110F016D
- PIC32MX120F032B
- PIC32MX120F032C
- PIC32MX120F032D
- PIC32MX210F016B
- PIC32MX210F016C
- PIC32MX210F016D
- PIC32MX220F032B
- PIC32MX220F032C
- PIC32MX220F032D
The following rows were added to Table 17-1:
- PIC32MX1X0
- PIC32MX2X0
Added a new sub section Section 17.4.6
Checksum Values While Device Is CodeProtected
Removed Register 18-1 through Register 18-5.

Removed Table 17-2
Removed Section 17.5 Checksum for PIC32
Devices and its sub sections
The Flash Program Memory Write-Protect
Ranges table was removed (formerly Table 18-4)
Added DEVCFG Locations for PIC32MX1X0 and
PIC32MX20X Devices Only (see Table 18-3)
In Section 18.0 Configuration Memory and
Device ID, removed Table 18-1 and updated
Table 18-2: DEVID Summary as Table 18-1
Added the NVMERR bit to the MCHP Status
Value table (see Table 19-3)
The following Silicon Revision and Revision ID
are added to Table 18-4:
- 0x5 - B6 Revision
- 0x1 - A1 Revision
Added a note to the Flash Memory Map (see
Figure A-1)
Added Appendix C: Flash Program Memory
Data Sheet Clarification
Revision J (August 2011)

Note:
The revision history in this document

intentionally skips from Revision H to
Revision J to avoid confusing the
uppercase letter I (EY) with the
lowercase letter l (EL).
This revision includes the following updates:

All occurrences of VCORE/VCAP have been changed
to VCAP
Updated the fourth paragraph of Section 2.0
Programming Overview
Removed the column, Programmer Pin Name, from
the 2-Wire Interface Pins table and updated the Pin
Type for MCLR (see Table 4-2)
Added the following new devices to the Code
Memory Size table (see Table 5-1) and the Device
IDs and Revision table (see Table 18-4):
- PIC32MX130F064B
- PIC32MX130F064C
- PIC32MX130F064D
- PIC32MX150F128B
- PIC32MX150F128C
- PIC32MX150F128D
- PIC32MX230F064B
- PIC32MX230F064C
- PIC32MX230F064D
- PIC32MX250F128B
- PIC32MX250F128C
- PIC32MX250F128D
Added Row Size and Page Size columns to the
Code Memory Size table (see Table 5-1)
DS61145L-page 63
PIC32
Revision J (August 2011) (Continued)
Updated the PGCx signal in Entering Enhanced
ICSP Mode (see Figure 7-1)
Updated the Erase Device block diagram (see
Figure 9-1)
Added a new step 4 to the process to erase a target
device in Section 9.0 Erasing the Device
Updated the MCLR signal in 2-Wire Exit Test
Mode (see Figure 15-2)
Updated the PE Command Set with the following
commands and modified Note 2 (see Table 16-2):
- PROGRAM_CLUSTER
- GET_DEVICEID
- CHANGE_CFG
Added a second note to Section 16.2.11
GET_CRC Command
Updated the Address and Length descriptions in the
PROGRAM_CLUSTER Format (see Table 16-13)
Added a note after the CHANGE_CFG Response (see
Figure 16-27)
Updated the DEVCFG0 and DEVCFG1 values for
All PIC32MX1XX and All PIC32MX2XX devices in
Table 17-1
The following changes were made to the AC/DC
Characteristics and Timing Requirements
(Table 20-1):
- Updated the Min. value for parameter D111 (VDD)
- Added parameter D114 (IPEAK)
- Removed parameters P2, P3, P4, P4A, P5, P8
and P10
Removed Appendix C: Flash Program Memory
Data Sheet Clarification
Minor updates to text and formatting were
incorporated throughout the document
Revision K (July 2012)

All occurrences of PGC and PGD were changed to:
PGEC and PGED, respectively
Updated Section 1.0 Device Overview with a list
of all major topics in this document
Added Section 2.3 Data Sizes
Updated Section 4.0 Connecting to the Device
Added Note 2 to Connections for the On-chip
Regulator (see Figure 4-2)
Added Note 2 to the 4-wire and 2-wire Interface Pins
tables (see Table 4-1 and Table 4-2)
Updated Section 7.0 Entering 2-Wire Enhanced
ICSP Mode
Updated Entering Serial Execution Mode (see
Figure 10-1)
Updated step 11 in Section 10.2 2-wire Interface
DS61145L-page 64
Updated Section 12.2 With the PE

Updated Step 3 in Initiate Flash Row Write Op
Codes (see Table 13-1)
Updated Step 1 in Verify Device Op Codes (see
Table 14-1)
Updated the interval in Section 15.1 4-wire
Interface and Section 15.2 2-wire Interface
Added a note regarding the PE location in
Section 16.0 The Programming Executive
Added references to the Operand field throughout
Section 16.2 The PE Command Set
Updated the PROGRAM Command Algorithm (see
Figure 16-9)
Updated the mask values for All PIC32MX1XX
and PIC32MX2XX devices, and DEVCFG3 for all
devices (see Table 17-1)
Updated the DCR value (see Section 17.4.3
Calculating for DCR in the Checksum
Formula and Table 17-2)
Updated the Checksum Calculation Process (see
Example 17-1)
Added these new devices to the Code Memory Size
table (see Table 5-1) and the Device IDs and
Revision table (see Table 18-4):
-
PIC32MX420F032H
PIC32MX330F064H
PIC32MX330F064L
PIC32MX430F064H
PIC32MX430F064L
PIC32MX340F128H
PIC32MX340F128L
PIC32MX350F128H
PIC32MX350F128L
PIC32MX350F256H
PIC32MX350F256L
PIC32MX440F128H
PIC32MX440F128L
PIC32MX450F128H
PIC32MX450F128L
PIC32MX440F256H
PIC32MX450F256H
PIC32MX450F256L
PIC32MX460F256L
PIC32MX340F512H
PIC32MX360F512H
PIC32MX370F512H
PIC32MX370F512L
PIC32MX440F512H
PIC32MX460F512L
PIC32MX470F512H
PIC32MX470F512L
Added a Note to Section 18.2 Device Code

Protection bit (CP)
Added the EJTAG Control Register (see
Register 19-1)
Updated Section 19.2.4 ETAP_EJTAGBOOT
Command
AC/DC Characteristics and Timing Requirements
updates (see Table 20-1):
- Removed parameter D112
- Replaced Notes 1 and 2 with a new Note 1
- Updated parameters D111, D113, D114, D031,
D041, D080, D090, D012, D013, P11, P12, and
P13
incorporated through the document
PIC32
Revision L (January 2013)
The following sections were added or updated:
- Section 2.1 Devices with Dual Flash
Panel and Dual Boot Regions (new)
- Section 4.3 Power Requirements
- Section 13.0 Initiating a Flash Row Write
- Section 16.1.1 2-wire ICSP EJTAG RATE
Updated the Device Configuration Register Mask
Values (see Table 17-1)
The following devices were added to the Code
Memory Size table and the Device IDs and Revision
table (see Table 5-1 and Table 18-4):
- PIC32MZ0256ECE064
- PIC32MZ1024ECF064
- PIC32MZ0256ECE100
- PIC32MZ1024ECF100
- PIC32MZ0256ECE124
- PIC32MZ1024ECF124
- PIC32MZ0256ECE144
- PIC32MZ1024ECF144
- PIC32MZ0256ECF064
- PIC32MZ1024ECG064
- PIC32MZ0256ECF100
- PIC32MZ1024ECG100
- PIC32MZ0256ECF124
- PIC32MZ1024ECG124
- PIC32MZ0256ECF144
- PIC32MZ1024ECG144
- PIC32MZ0512ECE064
- PIC32MZ1024ECH064
- PIC32MZ0512ECE100
- PIC32MZ1024ECH100
- PIC32MZ0512ECE124
- PIC32MZ1024ECH124
- PIC32MZ0512ECE144
- PIC32MZ1024ECH144
- PIC32MZ0512ECF064
- PIC32MZ2048ECG064
- PIC32MZ0512ECF100
- PIC32MZ2048ECG100
- PIC32MZ0512ECF124
- PIC32MZ2048ECG124
- PIC32MZ0512ECF144
- PIC32MZ2048ECG144
- PIC32MZ1024ECE064
- PIC32MZ2048ECH064
- PIC32MZ1024ECE100
- PIC32MZ2048ECH100
- PIC32MZ1024ECE124
- PIC32MZ2048ECH124
- PIC32MZ1024ECE144
- PIC32MZ2048ECH144
Note 3 and Note 4 and the GET_CHECKSUM and

QUAD_WORD_PRGM commands were added to the
PE Command Set (see Table 16-2)
Added Section 16.2.15 GET_CHECKSUM
Command
Added Section 16.2.16
QUAD_WORD_PROGRAM Command
Updated all addresses in DEVCFG Locations
(see Table 18-1 and Table 18-2)
Added Configuration Word Locations for
PIC32MZ EC Family Devices (see Table 18-3)
Updated Section 18.2 Device Code Protection
bit (CP)
Updated Section 18.3 Program Write Protection
bits (PWP)
All references to Test mode were updated to
Programming mode throughout the document
incorporated through the document
DS61145L-page 65
PIC32
NOTES:
DS61145L-page 66
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device

applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyers risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
2007-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-856-3
QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV
== ISO/TS 16949 ==
Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchips quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61145L-page 67
Worldwide Sales and Service

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Technical Support:
http://www.microchip.com/
support
Web Address:
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DS61145L-page 68
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11/29/12

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PIC32

PIC32 Flash Programming Specification

This document defines the programming specification

An external tool programming setup consists of an

The major topics of discussion include:

Section 1.0 Device Overview

Devices with Dual Flash Panel and

The PIC32MZ Embedded Connectivity (EC) family of

The self-programming method requires that the target

A development tool used for production programming

The external tool programming method does not

Insuring that the SWAP bit (NVMCON<7>) is in the

All PIC32 devices can be programmed through two

This document describes the external tool

2007-2013 Microchip Technology Inc.

All PIC32 devices provide two physical interfaces to the

Enhanced JTAG (EJTAG)

The 2-wire and 4-wire interfaces use the EJTAG

Per the EJTAG Specification, data sizes are defined as

One Word: 32 bits

2007-2013 Microchip Technology Inc.

All tool programmers must perform a common set of

The following sequence lists the steps, with a brief

Connect to the Target Device.

Place the Target Device in Programming Mode.

Enter Enhanced ICSP

For the 4-wire programming methods,

See Section 7.0 Entering 2-Wire Enhanced

Check Device Status

Check the Status of the Device.

See Section 8.0 Check Device Status for

If the target memory block in the device is not

See Section 9.0 Erasing the Device for

Download a Data Block

See Section 10.0 Entering Serial Execution

Enter Programming Mode.

Initiate Flash Write

Erase the Target Device.

Download the Programming Executive (PE).

Exit Programming Mode

If the programming method being used

2007-2013 Microchip Technology Inc.

Download the Block of Data to Program.

Initiate Flash Write.

Repeat Steps 7 and 8 until all data blocks are

10. Verify the program memory.

2007-2013 Microchip Technology Inc.

CONNECTING TO THE DEVICE

The PIC32 family provides two possible physical

TCK Test Clock Input

These signals are described in the following four

TEST CLOCK INPUT (TCK)

TCK is the clock that controls the updating of the TAP

One possible interface is the 4-wire JTAG (IEEE

TEST MODE SELECT INPUT (TMS)

TMS is the control signal for the TAP controller. This

+ MCLR, VDD, VSS

TEST DATA INPUT (TDI)