DIGITAL INTEGERATED

CIRCUITS II PRACTICAL
FILE

SUBMITTED BY
XYZ
ROLLNO
COE-I
SEM-VII

Table of Contents
S.No

Assignment

Characterization of Logic Family. Find out logic

threshold values and noise margins. Delay time
measurement of inverter using ring oscillator.

Design of combinational circuit, 2-4 Decoder, 4-2 encoder,

Binary to gray code converter using VHDL.

Model flip-flop, register, latch in VHDL. Implement

Asynchronous and synchronous reset

Design traffic light controller using VHDL.

Binary and BCD counter using VHDL.

Data demultiplexer. Data is required on a high speed

4-bit input bus, output to one of the three 4-bit output bus.

Serial in parallel out register using VHDL.

ALU using VHDL

Page

Assignment # 2
Design of 2x4 Decoder
--code for 2x4 decoder
library ieee;
use ieee.std_logic_1164.all;
entity Decoder2x4 is
port(i :in std_logic_vector(1 downto 0);e :in
std_logic;o std_logic_vector(3 down to 0));
end Decoder2x4;
architecture Behv of Decoder2x4 is
begin
process(i,e)
begin
if(e=1) then
o(0)<= (not i(0)) and (not i(1));
o(1)<= i(0) and (not i(1));
o(2)<= (not i(0)) and i(1);
o(3)<= i(0) and i(1);
else
o<-ZZZZ;
end if;
end process;
end architecture;
Test Bench
--test bench
entity TB is
end TB;
architecture TB_arch of TB is
component Decoder2x4 is
port(i :in std_logic_vector(1 downto 0);e :in
std_logic;o std_logic_vector(3 down to 0));
end component;
signal i:std_logic_vector(1 downto 0);
signal e:std_logic;
signal o:std_logic_vector(3 downto 0);
begin

inst:Decoder2x4 port map(i,e,o);

process
begin
e<= not e after 80 ns;
i<= transport 00;
wait for 20ns;
i<= transport 01;
wait for 20ns;
i<= transport 10;
wait for 20 ns;
i<= transport 11;
wait for 20 ns;
end process;
end architecture;

Design of 4x2 Encoder

--code for 4x2 encoder
library ieee;
use ieee.std_logic_1164.all;
entity encoder4x2 is
port(i:in std_logic_vector(3 downto 0);o:out
std_logic_vector(1 downto 0);e:in std_logic);
end encoder4X2;
architecture behv of encoder4x2 is
begin
process(i,e)
begin
if e=1 then
case i is
when 0001=> o<=00;
when 0010=> o<=01;
when 0100=> o<=10;
when 1000=> o<=11;
when others=> o<=ZZ;
else
o<=ZZ;
end if;
end process;
end architecture;
Test Bench
-- test bench
entity tb is
end tb;
architecture tb_arch of tb is
component encoder4x2 is
port(i:in std_logic_vector(3 downto 0);o:out
std_logic_vector(1 downto 0);e:in std_logic);
end component;
signal i:std_logic_vector(3 downto 0);
signal o:std_logic_vector(1 downto 0);
signal e:std_logic;
begin
inst:encoder4x2 port map(i,o,e);

process
begin
e<= not e after 40 ns;
i<=0001;
wait 10 ns;
i<=0010;
wait 10 ns;
i<=0100;
wait 10 ns;
i<=1000;
wait 10 ns;
end process;
end architecture;

Design of Binary to Gray Code Converter

-- code for binary to gray converter
library ieee;
use ieee.std_logic_1164.all;
entity b2g is
port(i:in std_logic_vector(3 downto 0);
o:out std_logic_vector(3 downto 0);e:in std_logic);
end b2g;
architecture behv of b2g is
begin
process(i,e)
begin
if e=1 then
o(0)<= i(0) xor i(1);
o(1)<= i(1) xor i(2);
o(2)<= i(2) xor i(3);
o(3)<= i(3);
else
o<=ZZZZ;
end if;
end process;
end architecture;
Test Bench
-- test bench
entity tb is
end tb;
architecture tb_arch of tb is
component b2g is
port(i:in std_logic_vector(3 downto 0);
o:out std_logic_vector(3 downto 0);e:in std_logic);
end component;
signal i:std_logic_vector(3 downto 0);
signal o:std_logic_vector(3 downto 0);
signal e:std_logic;
begin
inst:b2g port map(i,o,e);
process
begin
e<=not e after 30 ns;
i<=0000;
wait for 10 ns;
i<=0011
wait for 10 ns;

i<=1010;
wait for 10 ns;
end process;
end architecture;

Assignment # 3
Design of Synchronous and Asynchronous Register
--synchronous register
library ieee;
use ieee.std_logic_1164.all;
entity syn_8_reg is
port(d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
clk:in std_logic;rst:in std_logic);
end syn_8_reg;
architecture behv_syn of syn_8_reg is
begin
process(clk)
begin
if clk=1 then
if rst=1 then
q<=00000000;
else
q<=d;
end if;
end if;
end process;
end architecture;
--asynchronous register
library ieee;
use ieee.std_logic_1164.all;
entity asyn_8_reg is
port(d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
clk:in std_logic;rst:in std_logic);
end asyn_8_reg;
architecture behv_asyn of asyn_8_reg is
begin
process(clk,rst)
begin
if rst=1 then
q<=00000000;
elsif clk=1 then
q<=d;
end if;
end process;

end architecture;
Test Bench
--test bench
entity tb is
end tb;
architecture tb_arch of tb is
component syn_8_reg is
port(d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
clk:in std_logic;rst:in std_logic);
end component;
component asyn_8_reg is
port(d:in std_logic_vector(7 downto 0);
q:out std_logic_vector(7 downto 0);
clk:in std_logic;rst:in std_logic);
end component;
signal d:std_logic_vector(7 downto 0);
signal qsyn,qasyn:std_logic_vector(7 downto 0);
signal clk:std_logic;
signal rst:std_logic;
begin
inst1:syn_8_reg port map(d,qsyn,clk,rst);
inst2:asyn_8_reg port map(d,qasyn,clk,rst);
clk<=not clk after 15 ns;
rst<=not rst after 10 ns;
process
begin
d<=00000000;
wait for 30 ns;
d<=00011100;
wait for 30 ns;
end process;
end architecture;

Design of Synchronous and Asynchronous D Flip-flop

--synchronous D flip-flop
library ieee;
use ieee.std_logic_1164.all;
entity syn_d_ff is
port(d:in std_logic;q:out std_logic;clk:in std_logic;
rst:in std_logic);
end syn_d_ff;
architecture behv_syn of syn_d_ff is
begin
process(clk)
begin
if clk=1 then
if rst=1 then
q<=0;
else
q<=d;
end if;
end if;
end process;
end architecture;
--asynchronous D flip-flop
library ieee;
use ieee.std_logic_1164.all;
entity asyn_d_ff is
port(d:in std_logic;q:out std_logic;clk:in std_logic;
rst:in std_logic);
end asyn_d_ff;
architecture behv_asyn of asyn_d_ff is
begin
process(clk,rst)
begin
if rst=1 then
q<=0;
elsif clk=1 then
q<=d;
end if;
end process;
end architecture;

Test Bench
--test bench
entity tb is
end tb;
architecture tb_arch of tb is
component syn_d_ff is
port(d:in std_logic;q:out std_logic;clk:in std_logic;
rst:in std_logic);
end component;
component asyn_d_ff is
port(d:in std_logic;q:out std_logic;clk:in std_logic;
rst:in std_logic);
end component;
signal d,qsyn,qasyn,rst,clk: std_logic;
begin
inst1: syn_d_ff port map(d,qsyn,clk,rst);
inst2: asyn_d_ff port map(d,qasyn,clk,rst);
process
begin
d<=1;
wait for 30 ns;
d<=0;
wait for 30 ns;
end process;
clk<=not clk after 15 ns;
rst<=not rst after 10 ns;
end architecture;

Design of Latch
--dlatch
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port(d:in std_logic;q:out std_logic;clk:in std_logic;
rst:in std_logic);
end dlatch;
architecture behv_latch of dlatch is
begin
process(d,rst)
begin
if rst=1 then
q<=0;
elsif clk=1 then
q<=d;
end if;
end process;
end architecture;
Test Bench
--test bench
entity tb is
end tb;
architecture tb_arch of tb is
component dlatch is
port(d:in std_logic;q:out std_logic;clk:in std_logic;
rst:in std_logic);
end component;
signal d,q,rst,clk: std_logic;
begin
inst: dlatch port map(d,q,clk,rst);
process
begin
d<=1;
wait for 30 ns;
d<=0;
wait for 30 ns;
end process;
clk<=not clk after 15 ns;
rst<=not rst after 10 ns;
end architecture;

Assignment # 4
Design of Traffic Light Controller
--traffic light controller
library ieee;
use ieee.std_logic_1164.all;
entity tlc is
port(clk:in std_logic;red:out std_logic;yellow:out
std_logic;green:out std_logic);
end tlc;
architecture tlc_arch of tlc is
type state is (SRED,SYELLOW,SGREEN);
variable tlcstate :state:=SRED;
variable count:integer:=0;
begin
process(clk)
begin
if clk=1 then
case tlcstate is
when SRED=>
if count=10 then
tlcstate:=SGREEN;
count:=0;
else
count:=count+1;
red<=1;
yellow<=0;
green<=0;
end if;
when SYELLOW=>
if count=2 then
tlcstate:=SRED;
count:=0;
else
count:=count+1;
red<=0;
yellow<=1;
green<=0;
end if;
when SGREEN=>
if count=10 then
tlcstate:=SYELLOW;

count:=0;
else
count:=count+1;
red<=0;
yellow<=0;
greem<=1;
when others=> tlcstate:=SRED;
count:=0;
end case;
end if;
end process;
end architecture;
Test Bench
--test bench
entity tb is
end tb;
architecture tb_arch of tb is
component tlc is
port(clk:in std_logic;red:out std_logic;yellow:out
std_logic;green:out std_logic);
end component;
signal clk:std_logic:=0;
signal red, yellow, green : std_logic;
begin
clk<=not clk after 10 ns;
inst:tlc port map(clk,red,yellow,green);
end architecture;

Assignment # 5
Design of Binary Counter and BCD Counter
--binary counter
library ieee;
use ieee.std_logic_1164.all;
entity bincnt is
port(count:out std_logic_vector(3 downto 0);clk:in
std_logic;rst:in std_logic);
end bincnt;
architecture bincnt_arch of bincnt is
begin
process(clk,rst)
begin
if rst=1 then
count<=0000;
elsif clkevent and clk=1 then
count<=count+1;
end if;
end process;
end architecture;
--bcd counter
library ieee;
use ieee.std_logic_1164.all;
entity bcdcnt is
port(count:out std_logic_vector(3 downto 0);clk:in
std_logic;rst:in std_logic);
end bcdcnt;
architecture bcdcnt_arch of bcdcnt is
begin
process(clk,rst)
begin
if rst=1 then
count<=0000;
elsif clkevent and clk=1 then
if count=1001 then
count<=0000;
else
count<=count+1;
end if;
end if;

end process;
end architecture;
Test Bench
--testbench
entity tb is
end tb;
architecture tb_arch of tb is
component bincnt is
port(count:out std_logic_vector(3 downto 0);clk:in
std_logic;rst:in std_logic);
end component;
component bcdcnt is
port(count:out std_logic_vector(3 downto 0);clk:in
std_logic;rst:in std_logic);
end component;
signal clk,rst:std_logic:=0;
signal bcdcount,bincount:std_logic_vector(3 downto 0);
begin
clk<=not clk after 20 ns;
rst<=not rst after 400 ns;
inst1: bincnt port map(bincount,clk,rst);
inst2: bcdcnt port map(bcdcount,clk,rst);
end architecture;

Assignment # 6
Design of 4 Bit Data Demultiplexer
--Demultiplexer 4 bit data on three 4 bit output bus
library ieee;
use ieee.std_logic_1164.all;
entity demux is
port(din:in std_logic_vector(3 downto 0);sel:in
std_logic_vector(1 downto 0);dout1, dout2,dout3:out
std_logic_vector(3 downto 0));
end demux;
architecture demux_arch of demux is
begin
process(din,sel)
begin
case sel is
when 00=> dout1<=din;
dout2<=zzzz;
dout3<=zzzz;
when 01=> dout1<=zzzz;
dout2<=din;
dout3<=zzzz;
when others=>dout1<=zzzz;
dout2<=zzzz;
dout3<=din;
end case;
end process;
end architecture;

Test Bench
-- testbench
entity tb is
end tb;
architecture tb_arch of tb is
component demux is
port(din:in std_logic_vector(3 downto 0);sel:in
std_logic_vector(1 downto 0);dout1, dout2,dout3:out

std_logic_vector(3 downto 0));

end component;
signal din,dout1,dout2,dout3:std_logic_vector(3 downto 0);
signal sel:std_logic_vector(1 downto 0);
begin
inst:demux port map(din,sel,dout1,dout2,dout3);
p1:process
begin
din<=0010;
wait for 20 ns;
din<=1001;
wait for 20 ns;
end process;
p2:process
begin
sel<=00;
wait for 25 ns;
sel<=01;
wait for 25 ns;
sel<=10;
wait for 25 ns;
sel<=01;
wait for 25 ns;
sel<=11;
wait for 25 ns;
end process;
end architecture;

Assignment # 7
ALU Design
--serial in parallel out register
library ieee;
use ieee.std_logic_1164.all;
entity sipo is
port(sin,clk,rst,enable:in std_logic; o:out
std_logic_vector(3 downto 0));
end sipo;
architecture sipo_arch of sipo is
signal temp:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rst=1 then
temp=0000;
else
if clk=1 and enable=1 then
temp(3)<=temp(2);
temp(2)<=temp(1);
temp(1)<=temp(0);
temp(0)<=sin;
end if;
end if;
end process;
o<=temp;
end architecture;
--testbench
entity tb is
end tb;
architecture tb_arch of tb is
component sipo is
port(sin,clk,rst,enable:in std_logic; o:out
std_logic_vector(3 downto 0));
end component;
signal sin,clk,rst,enable:std_logic;
signal o:std_logic_vector(3 downto 0);
begin

inst: sipo(sin,clk,rst,enable,o);
clk<=not clk after 10 ns;
process
enable<=1;
rst<=0;
sin<=1;
wait for 10 ns;
sin<=1;
wait for 10 ns;
sin<=0;
wait for 10 ns;
sin<=1;
wait for 10 ns;
end process;
end architecture;

Assignment # 8
--ALU
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity alu is
port(a,b:in std_logic_vector(6 downto 0);
z:out std_logic_vector(7 downto 0);
sel:in std_logic-vector(3 downto 0);
c:in std_logic);
end alu;
architecture alu_d_arch of alu is
begin
process(a,b,sel)
begin
case sel is
when 0000=> z(6 downto 0)<=a and b;
when 0001=> z(6 downto 0)<=a or b;
when 0010=> z(6 downto 0)<=a xor b;
when 0011=> z(6 downto 0)<=not a;
when 0100=> z<=a+b;
when 0101=> z<=a-b;
when 0110=> z<=a+1;
when 0111=> z<=a-1;
when 1000=> z(6 downto 1)<=a(5 downto 0);
z(0)<=0;
when 1001=> z(5 downto 0)<=a(6 downto 1);
z(6)<=0;
when others=> z<=(others=>z);
case end;
end process;
end architecture;