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Mejores Practicas

The document summarizes the instruction set for AVR microcontrollers. It describes the main categories of instructions including arithmetic/logic instructions like ADD, SUB, AND; branch instructions like JMP, CALL, RET; bit/bit-test instructions like SBI, CBI, BST; data transfer instructions like MOV, LDI, ST; and MCU control instructions like NOP, SLEEP. For each instruction category, it provides examples of common instructions and briefly explains their functions.

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jerry3128
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72 views9 pages

Mejores Practicas

The document summarizes the instruction set for AVR microcontrollers. It describes the main categories of instructions including arithmetic/logic instructions like ADD, SUB, AND; branch instructions like JMP, CALL, RET; bit/bit-test instructions like SBI, CBI, BST; data transfer instructions like MOV, LDI, ST; and MCU control instructions like NOP, SLEEP. For each instruction category, it provides examples of common instructions and briefly explains their functions.

Uploaded by

jerry3128
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Microprocesadores

y Microcontroladores
Instrucciones AVR

Instrucciones AVR
Arithmetic and Logic instructions
Branch instructions
Bit and Bit-Test instructions
Data Transfer instructions
MCU Control instructions

Arithmetic and Logic instructions


ADD

SUB

AND

ADD Rd, Rr Add two Registers


ADC Rd, Rr Add with Carry two Registers
ADIW Rdl,K Add Immediate to Word

SUB Rd, Rr
SUBI Rd, K
SBC Rd, Rr
SBCI Rd, K
SBIW Rdl,K
AND Rd, Rr
ANDI Rd, K

Subtract two Registers


Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
3

Arithmetic and Logic instructions


OR

OR Rd, Rr
ORI Rd, K

Logical OR Registers
Logical OR Register and Constant

EOR Rd, Rr
COM Rd
NEG Rd
SBR Rd,K
CBR Rd,K
TST Rd
CLR Rd
SER Rd

Exclusive OR Registers
Ones Complement
Twos Complement
Set Bit(s) in Register (OR)
Clear Bit(s) in Register (AND)
Test for Zero or Minus
Clear Register
Set Register

Arithmetic and Logic instructions

MUL

MUL Rd, Rr
MULS Rd, Rr
MULSU Rd, Rr
FMUL Rd, Rr
FMULS Rd, Rr
FMULSU Rd, Rr

Multiply Unsigned
Multiply Signed
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned

Branch instructions
JMPs

RJMP k
IJMP
JMP

Relative Jump
PC PC + k + 1
Indirect Jump to (Z) PC Z
k Direct Jump
PC k

CALLs

RCALL k
ICALL
CALL k

Relative Subroutine Call PC PC + k + 1


Indirect Call to (Z)
PC Z
Direct Subroutine Call PC k

RETs

RET
RETI

Subroutine Return
Interrupt Return

PC STACK
PC STACK

Branch instructions
CMP

CPSE Rd,Rr
CP Rd,Rr
CPC Rd,Rr
CPI Rd,K

Compare, Skip if Equal


Compare
Compare with Carry
Compare Register with Immediate

Skips

SBRC Rr, b
SBRS Rr, b
SBIC P, b
SBIS P, b

Skip if Bit in Register Cleared


Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set

Branch instructions

BRANCH

BRBS s, k
BRBC s, k
BREQ k
BRNE k
BRCS k
BRCC k
BRSH k
BRLO k
BRMI k
BRPL k
BRGE k
BRLT k

Branch if Status Flag Set


Branch if Status Flag Cleared
Branch if Equal
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
8

Branch instructions

BRANCH

BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID

k
k
k
k
k
k
k
k

Branch if Half Carry Flag Set


Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled

Bit and Bit-Test instructions


SBI P,b
CBI P,b
LSL Rd
LSR Rd
ROL Rd
ROR Rd
ASR Rd
SWAP Rd

Set Bit in I/O Register


Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles

10

Bit and Bit-Test instructions


BSET s
BCLR s
BST Rr, b
BLD Rd, b
SEC
CLC
SEN
CLN
SEZ
CLZ

Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag

11

Bit and Bit-Test instructions


SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH

Global Interrupt Enable


Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG

12

Data Transfer instructions

MOVs

MOV Rd, Rr
MOVW Rd, Rr

Move Between Registers


Copy Register Word

13

Data Transfer instructions

LDs

LDI Rd, K
LD Rd, X
LD Rd, X+
LD Rd, - X
LD Rd, Y
LD Rd, Y+
LD Rd, - Y
LDD Rd,Y+q
LD Rd, Z
LD Rd, Z+
LD Rd, -Z
LDD Rd, Z+q
LDS Rd, k

Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
14

Data Transfer instructions

STs

ST X, Rr
ST X+, Rr
ST - X, Rr
ST Y, Rr
ST Y+, Rr
ST - Y, Rr
STD Y+q,Rr
ST Z, Rr
ST Z+, Rr
ST -Z, Rr
STD Z+q,Rr
STS k, Rr

Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
15

Data Transfer instructions


Flash

LPM
LPM Rd, Z
LPM Rd, Z+
SPM

Load Program Memory


Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory

I/O

IN Rd, P
OUT P, Rr

In Port
Out Port

Stack

PUSH Rr
POP Rd

Push Register on Stack


Pop Register from Stack

16

MCU Control instructions

MCU

NOP
SLEEP
WDR
BREAK

No Operation
Sleep
Watchdog Reset
Break (For On-chip Debug Only)

17

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