Concept and Design and Fabrication of a 2 Bit

Comparator
(A design report for ECEN 5375)
By
Kendra Krueger
May 4th 2010

Outline
Concept and Design and Fabrication of a 2 Bit Comparator...............................................1
Outline..............................................................................................................................2
1.Introduction...................................................................................................................3
2.Circuit description.........................................................................................................3
3.Circuit simulation..........................................................................................................7
4.Worst case analysis.....................................................................................................10
5.Circuit Layout.............................................................................................................12
6.Testing Procedure.......................................................................................................13
7.Circuit Fabrication......................................................................................................14
8.Device Testing............................................................................................................15
9.Circuit Testing............................................................................................................20
10.Possible improvements.............................................................................................23
11.Conclusion................................................................................................................24
12.Final Conclusion.......................................................................................................24

1.Introduction
The concept of this design is to produce a 2 bit comparator using pMOS transistors. A
comparator consists of two XOR gates which combine in a NOR to determine if the
inputs are equal or not, the logic is described in equation 1.1. Transient and DC
simulations were conducted on the circuit to determine proper width to length ratios and
worse case scenarios. The layout was then created using a stick diagram which was then
converted into a final design layout using CleWin.
(A0 O B0)+(A1 O B1)=D
Equation 1.1: Comparator Logic Equation

2.Circuit description
A comparator can be simplified into NAND and NOR gates which make it easier to
implement with pMOS technology. Figure 2.1 and 2.2 show the conversion from XOR
to NAND. From this point using these diagrams, and the pMOS implementation of a
NAND and NOR, a full circuit can be designed as displayed in figure 2.3. Table 2.1 is
the truth table for the comparator logic
A0

C0

B0

74HC386D

C0

C1

74HC36D

A1

C1

B1

74HC386D

Figure 2.1: Comparator Logic Gates

1

74HC03D
A0
B0

C0

74HC03D

74HC03D
1

2
C0

74HC03D

D
C1

74HC36D

74HC03D
A1
B1

C1

74HC03D

74HC03D
1
3

74HC03D

Figure 2.2: Comparator Logic with NAND gates

A0 A1 B0 B1 C0 C1 D
0

Table 2.1: Device Logic

The first design was implemented using NMOS technology as illustrated in figure 2.3.
However since the materials and processes used in fabrication are based on pMOS
technology the circuit was implemented using pMOS technology as visualized in figure
2.4. The only problems faced when converting the logic was confusion between high and
low logic levels. For nMOS logic, positive values are high and 0 is low. For pMOS
negative values are high, and 0 is low.
Figure 2.3: Comparator Circuit with CMOS transistors

Figure 2.4: Comparator Circuit with pMOS transistors

Initially the basic provided model for the pMOS transistor was used, displayed in
equation 2.1 with w/l ratios of 12/20 for load transistors, and 120/12 for drivers.

.MODEL PMOS PMOS (LEVEL=2 L=20u W=120u VTO=-3 KP=8.64E-6 NSUB=2E15

TOX=80n)
Equation 2.1

3.Circuit simulation
After building the circuit in LTspice, DC and transient simulations could be run to
confirm the truth tables of the device. The initial parameters as discussed in section 2.1
were first used. For the DC analysis, one input was varied from -10 to 0 volts. The
signal was then observed on the CO,C1 and D outputs. Figure 3.1 are the results from the
first DC analysis, transistors with threshold voltages of -3V and gate voltages of -10V

Figure 3.1: First DC Analysis

In this graph A0 changes from low to high, as B0 stays low. This changes the value of
C0 from a low of -1V to a high of -6V, as C1 remains unchanged at 0. As this changes,
D then transitions from a low of -6V to a high of -3.5V. This behavior is consistent with
the logic of a comparator, but the difference between high and low values for the D
output was not sufficient enough. By changing the pMOS model to the following in
equation 3.1, the output voltage swing was greatly improved, as can be seen in figure 3.2.
.MODEL KFET PMOS (LEVEL=2 PHI=.6 VTO=-5 KP=1.95E-5 LAMBDA=0.0416
NSUB=2E15 XJ=1U VMAX=2.64E5 DELTA=2.3 CJ=1.97E-4 CJSW=1.27E-10
CGBO=.357N TPG=-1 LD=1E-6 CGDO=3.7E-10 CGSO=3.7E-10 RSH=66 TOX=10E8 UO=236 UEXP=.25 UCRIT=8.3E4 GAMMA=.5 NFS=3.23E11 MJ=.49
MJSW=1.96E-3 PB=.7)

Equation 3.1: Improved pMOS model

Figure 3.2:Improved DC Analysis

The next step was to run a transient analysis which allows for all of the states of the
device to be observed. Pulses of 40 and 80us were used on the inputs to drive the states.
Figure 3.3 displays the behavior of the system with changing inputs.

Figure 3.3: Transient Analysis

By comparing the states to the logic diagram, it can be seen that the simulated device is
indeed functioning as a comparator. Notable in figure 3.3 are peaks and dips which
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appear mid state. These are caused by conditions when both inputs change
simultaneously on the pulse edge. The following list displays the nodes of the simulation
* C:\Users\Kendra K\Documents\micro lab\8-16and40-8wl-goodsim.asc
V1 $G_Vdd 0 -15
V2 $G_A0 0 PULSE(-15 0 40us 1us 1us 40us 80u)
V3 B0 0 PULSE(-15 0 80u 1u 1u 80u 160u)
M1 $G_VDD $G_VDD N007 0 kfet l=16u w=8u
M5 $G_Vdd $G_Vdd N002 0 kfet l=16u w=8u
M9 N014 B0 0 0 kfet l=8u w=40u
M12 $G_Vdd $G_Vdd $G_C0 0 kfet l=16u w=8u
M2 N010 N007 N014 0 kfet l=8u w=40u
M3 $G_Vdd $G_Vdd N010 0 kfet l=16u w=8u
M4 N004 N007 0 0 kfet l=8u w=40u
M6 N002 $G_A0 N004 0 kfet l=8u w=40u
M7 N012 B0 0 0 kfet l=8u w=40u
M8 N007 $G_A0 N012 0 kfet l=8u w=40u
M10 N008 N010 0 0 kfet l=8u w=40u
M11 $G_C0 N002 N008 0 kfet l=8u w=40u
M25 D $G_C0 0 0 kfet l=8u w=40u
M26 D $G_C1 0 0 kfet l=8u w=40u
M27 $G_Vdd $G_Vdd D 0 kfet l=16u w=8u
V5 $G_A1 0 PULSE(-15 0 200us 1us 1us 40us 80u)
V6 B1 0 PULSE(-15 0 280u 1u 1u 80u 160u)
M13 $G_VDD $G_VDD N005 0 kfet l=16u w=8u
M14 $G_Vdd $G_Vdd N001 0 kfet l=16u w=8u
M15 N013 B1 0 0 kfet l=8u w=40u
M16 $G_Vdd $G_Vdd $G_C1 0 kfet l=16u w=8u
M17 N009 N005 N013 0 kfet l=8u w=40u
M18 $G_Vdd $G_Vdd N009 0 kfet l=16u w=8u
M19 N003 N005 0 0 kfet l=8u w=40u
M20 N001 $G_A1 N003 0 kfet l=8u w=40u
M21 N011 B1 0 0 kfet l=8u w=40u
M22 N005 $G_A1 N011 0 kfet l=8u w=40u
M23 N006 N009 0 0 kfet l=8u w=40u
M24 $G_C1 N001 N006 0 kfet l=8u w=40u
.model NMOS NMOS
.model PMOS PMOS
.lib C:\PROGRA~1\LTC\LTSPIC~1\lib\cmp\standard.mos
.MODEL PMOS PMOS (LEVEL=2 L=20u W=120u VTO=-1.44 KP=8.64E-6 NSUB=2E15
TOX=80n)
.tran 0 1000us 1us
.MODEL KFET PMOS (LEVEL=2 PHI=.6 VTO=-5 KP=1.95E-5 LAMBDA=0.0416
NSUB=2E15 XJ=1U VMAX=2.64E5 DELTA=2.3 CJ=1.97E-4 CJSW=1.27E-10
CGBO=.357N TPG=-1 LD=1E-6 CGDO=3.7E-10 CGSO=3.7E-10 RSH=66 TOX=10E-8
UO=236 UEXP=.25 UCRIT=8.3E4 GAMMA=.5 NFS=3.23E11 MJ=.49 MJSW=1.96E-3
PB=.7)
;tran 0 1000ns 1ns
.backanno
.end

List 3.1: Netlist for Simulation

4.Worst case analysis

In order to determine worse case scenarios, the threshold voltage of the devices was
changed to -5V instead of 1.6V. Initially with a gate voltage of -10, the device would
not properly perform, as displayed in figure 4.1.
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Figure 4.1: Insufficient Gate Voltage at -5V Vth

Here it can be seen that the CO output is not being properly activated with the A0 input.
When the input voltage and VDD is increased to -15 volts, the outputs are then properly
initialized as seen in figure 4.2

Figure 4.2:Increased Gate Voltage at -5V Vth

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However, even after increasing the gate voltage the swing between positive high and
low values was not large enough on the D output, so the width and length ratios were
increased to better contrast high and low. Comparing the final circuit at -5V threshold
voltage (figure 4.3) to the transient at 1.6V threshold (figure 3.3), the high to low swing is
much more significant.

Figure 4.3: Final Transient with -15V Gate Voltage, -5 Threshold Voltage

5.Circuit Layout
The first step of configuring the layout was to draw a stick diagram. The stick diagram
portrays the location of the different layers and their connections to one another. The
stick diagram in figure 5.1 portrays metal in blue, gate oxide in red, field oxide in green,
and via holes with black circles. Via holes are connections where field oxide makes
contact with metal.

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Figure 5.1: Stick Diagram

From the stick diagram an appropriate layer diagram could be created using CleWin
Software. Figure 5.2 below shows the final layout design. A few features needed to be
altered from the stick diagram in order to fit all the components in. One notable change
is the removal of 4 center testing pads on the left and right sides. Requirements for the
layout included minimum feature size of 8m and minimum layer overlap of 4m.

Figure 5.2: Final Layout Design

6.Testing Procedure
After the device has completed fabrication multiple tests must be run to confirm its
functionality. The first steps will be to test the C0 output, which is the output of one
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XOR gate, coming from AO and BO inputs. By varying the input signals, high and low
at values similar to simulation (high -10, low 0, Vg=-15) the outputs should mimic those
in the simulation. Next the same should be done with C1, A1, and B1. Finally the total
output D should be tested, varying the inputs A0, B0, A1, and B1. The values should
follow the truth table for the comparator. If the results do not match, both XORs and the
NOR gates can be tested individually since testing pads were connected to input/output
lines C1 and C0.

7.Circuit Fabrication
The circuit was fabricated using multiple lithography steps. The process started with a ntype ~ 10 cm 14 mil thick (100) silicon wafer which was oxidized in a steam
atmosphere at 1100C for 110 min. The following steps were taken to fabricate the wafer

Table 7.1: Fabrication Steps

The following images where taken after fabrication had been completed.

Figure 7.1: Final Micrograph of Circuit

This is the final grand circuit, fully designed and fabricated. The fabrication
process did have a few bumps along the way, but did not have a significant effect on the
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end result. Some issues observed during fabrication included the bubbles formed during
the gate oxide step of the process. Also the gate oxide etch may have over etched and
reduced width of the gate, which could result in different voltage output. Furthermore
Alignments were not perfect, which could lead to some non functional circuits due to
alignment rotation. However it did seem that there were a significant amount of properly
aligned circuits, which are suitable for testing.

Figure 7.2: Circuit throughout fabrication (from top left clockwise) Field oxide, Gate Oxide,
Via holes, Aluminum.

8.Device Testing
Testing was performed on the various devices and structures on the wafer. The
following data was obtained through these tests in order to compare quality and
functionality with other wafers fabricated in the class.
8.a

Provide the data measured on the transmission line structure by plotting the
measured resistance multiplied with the width (20 micron) as a function of the
contact spacing (10, 20, 40 and 80) micron. Extract the sheet resistance, Rs, (= the
slope) and the contact resistance, Rc, (half the Y-axis intercept, in units of Ohmcm). Calculate the contact resistivity, c, from Rc = Rs c

14

Figure 8.1: Transmission Line Resistance

8.b

What is the thickness of the gate, "diffusion" and field oxide as measured with the
ellipsometer? What are the thicknesses of the gate oxide and "diffusion" oxide as
obtained from the C-V measurements? What values are the most accurate and why?

Figure 8.2: Capacitance

Oxide Thickness

15

Measurements using interferometry and elipsometry were not used.

7.c

What is the doping concentration, the threshold voltage and the flatband voltage as
obtained from the C-V measurement? Carefully scrutinize the minimum capacitance
the C-V system used to calculate the doping concentration and adjust the value if
necessary. As additional information, keep in mind that the sheet resistance (as
measured with the M-gage) of the starting wafers was 100 - 200 Ohm per square.
The wafers are 14 mils thick. What doping concentration would you expect from
this M-gage measurement?
Flat Band Voltage
Threshold Voltage

Oxide Area
Diffusion Capacitance

Oxide Capacitance

Oxide Thickness

Depletion Region

Doping Concentration

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Theoretical Flat Band voltage and Capacitance

8.d

List the measured values of the output conductance, the threshold voltage and the
slope on the versus VG curve of the larger driver transistor. Calculate the surface
mobility based on your measurements. What value did you use for the W/L ratio of
the transistor? How does your calculated value compare to the bulk mobility
expected from the substrate doping concentration? Calculate the transconductance
for the gate and drain voltage at which the output conductance was measured (take
the drain voltage to be halfway between the two values used to draw the straight
line). Calculate the ratio between the transconductance and output conductance at
that bias point.

Figure 8.3: Output Conductance

Output Conductance:

Threshold Voltage

17

Figure 8.4: Transconductance

Carrier Mobility

Transconductance
5.83
Width to Length Measurement

8.e

Describe the measured p-n diode characteristics. Provide the extracted parameters.
How do these compare to the expected values?
After gold was sputtered on the back of the wafer, the I-V characteristics of a PN diode
were measured, both in ambient light and in the dark.

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Figure 8.5

The data extracted from the devices is summarized in the table below:
Parameter

expected

actual

Threshold voltage
Hole mobility

-5 V
100 cm2/V-s

-7 V
196 cm2/V-s

Gate capacitance
Doping density

37nF
2 x 1015 cm-3

18.5nF
1.43 x 1015 cm-3

Value obtained
from
Transfer curve
Calculated from K
and Cox
C-V measurement
C-V measurement

Table 8.1: Captured Device Parameters.

9.Circuit Testing
Circuit testing began with little results, but this was probably caused by poor
connections, or a testing on a bad circuit. The first test included measuring the current
leakage from power to ground. There did not seem to be significant leakage so testing
continued on chosen circuit. Next the output was measured while varying the two inputs.
Power was set to -30V, and A0 input was varied from 0 to -20V. Two measurements
were run, one with B0=0V and another with B0=-20V. The following diagram displays
the behavior at the output C0

19

Figure 9.1: First Output Measurement

A second device was then tested for repeatability.

Figure 9.2: Second Output Measurement

From these two graphs it is apparent that the behavior is functional and somewhat
repeatable. In the first the voltage starts to go high at around -10V input, and has a half
maximum at -12V. This is good for power propagation through the rest of the circuit. In
order to power on other devices, the mid range power should be higher than where the

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voltage starts to turn on. Device 2 shows similar results but with a higher turn on voltage
at around -15V.
Below are the simulated results using -30Vdd input, noting that this circuit has a
threshold of -5V and not -7V.

Figure 9.3: Simulated Output Voltage

The simulated results actually look worse than the experimentally obtained data.
However, when the threshold voltage of the simulation is changed to -7V, the output
becomes much more similar.

Simulation with Vt= -7, Vdd=-30

-25
-20
-15
B0=0

()
0
C
ge
la
o
tV
p
u
O

-10

B0= -20V

-5
0
0

-5

-10

-15

-20

-25

Input Voltage A0 (V)

Figure 9.4: Simulation with Higher Threshold Voltage

Comparing the results it is apparent that the fabricated circuit was a successes and
fulfilled the 1 bit comparator mode of the device. Unfortunately there was a design error
in the layout and the final two transistors of the NOR gate were not connected to ground.

21

This resulted in two symmetric 1 bit comparators that were testable, but not the final
output of the combined 2 bit comparator.

10.Possible improvements
The circuit could have been improved with further error proofing of the original design.
Furthermore some of the W/L ratios could have been changed to increase power
propagation through out the circuit. If more space were available ideal W/L ratios would
be 8/64. Figure 7.1 below shows responses with pulses of 4s, instead of the previously
used 40s. When width to length ratio is decreased for loads to 8/64 from 8/16, figure
7.2 shows better response time.

Figure 7.1: 8/16 width to length ratio response to 4s pulse

Figure 7.2: 8/64 W/L ratio response to 4s pulse

22

Furthermore during testing, it would have been useful to have more pads
connected to certain outputs, such as specific NAND gates within the circuit, to test for
individual functionality.

11.Conclusion
The design and fabrication of the comparator was in general a success. There
were a few kinks along the way, but the process proved to be reliable, and simulated
functionality was obtained during testing. The 2-bit comparator had to be reduced to a 1bit comparator due to design error, but both1 bit comparators were functional. The power
supply voltage necessary was -30V, with a threshold voltage of -7V. The simulation with
-30V and a threshold of -6V shows very similar results.
After fabrication there were approximately 20 working circuits . Half were lost
when the wafer cracked, and the rest were visually defective due to scratches or bubbles
caused during etching. The final color was silver on the device region, and a
purple/green around the edges depending on the angle the chip was held. My wafer was
chosen for testing because functionality of the transistors and other devices were
consistent.

12.Final Conclusion
At first 27 transistors seemed as like an intimidating number, but after the fabrication
yielded a working device Im less skeptical. The results seem to come down to having
enough pads in order to test different regions of the circuit and various outputs in case a
mistake was made further down the line. If the whole class were to work on a more
complex circuit, it should have sub functionality within in it that can easily be tested.
Since an average of 30 transistors seemed a challenging enough task to design without
flaw, it seems that would be a good number to have per student. However, building a
more complex circuit would require something to be chosen ahead of time, and some of
the creative challenge would be lost to the individual. I think a really incredible part of
this class was the start to finish design and implementation of something we were able to
decide upon ourselves, and within that comes the task of determining what is doable
within the time and resource limits. All of those factors lead to the course being a hands
on learning adventure that I really enjoyed.

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