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ECEN 248 Lab 5 Report

This lab report describes designing and implementing a 4-bit arithmetic logic unit (ALU) that can perform addition, subtraction, and AND operations. The ALU uses multiplexers to select between performing different logic functions. Truth tables and K-maps are provided for a 2:1 multiplexer design. The final physical ALU circuit is shown and test results demonstrate it works as intended by switching between logic operations.

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Rebecca Sontheimer
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626 views4 pages

ECEN 248 Lab 5 Report

This lab report describes designing and implementing a 4-bit arithmetic logic unit (ALU) that can perform addition, subtraction, and AND operations. The ALU uses multiplexers to select between performing different logic functions. Truth tables and K-maps are provided for a 2:1 multiplexer design. The final physical ALU circuit is shown and test results demonstrate it works as intended by switching between logic operations.

Uploaded by

Rebecca Sontheimer
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Lab 5: Simple Arithmetic

Logic Unit
Rebecca Sontheimer
ECEN 248-511
TA: Mehnaz Rahman
Date: October 15, 2014

Objectives
The purpose of this lab is to design and implement a 4-bit ALU which can add,
subtract, and AND bits.

Design
Truth Table for 2:1 Multiplexor
S
A
B
F
0

K-Map for 2:1 Multiplexor:


AB\S 0 1
00
0 0
01
0 1
11
1 1
10
1 0
Minimized expression:
F = S * A + S * B
Gate Level Schematic of a 2:1 MUX
4-bit addition/subtraction circuit
4-bit 2:1 MUX
Operations of the MUX within the ALU:
c0 c1 Op
0 0 AND
0 1 Add
1 0 AND
1 1 Sub
Final ALU design

Physical ALU circuit

Results
The circuit worked the way that it was supposed to work after fighting with it for
a while and finally finding out what wires had been improperly placed. It was a lot of trial
and error, but it worked in the end and was able to switch between the AND block and
the add/sub block. The final physical circuit is pictured on the previous page.

Conclusions
Post-Lab Deliverables
1. All items are in the design section of this lab report.

Control
C1
1
1
1
1
1
1
0
0

Control
C0
1
1
1
1
1
1
1
1

Result

S3

S2

S1

S0

Overflow

6
5
4
3
2
6
5
3

2
3
2
1
1
5
2
4

4
2
2
2
1
1
7
7

0
0
0
0
0
0
0
0

1
0
0
0
0
0
1
1

0
1
1
1
0
0
1
1

0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

1
1
1
1
1
1
0
0

2
1
4
6
8
10
6
6

5
6
3
2
8
10
1
2

7
7
7
8
16
20
0
2

0
0
0
1
0
0
0
0

1
1
1
0
0
1
0
0

1
1
1
0
0
0
0
1

1
1
1
0
0
0
0
0

1. Above is a table with values from the breadboard.


2. The maximum gate delay possible on my particular ALU is shown below with a
time delay of 5 units.
3. Construct an 8:1 MUX from 4:1 and 2:1 multiplexors:

4:1 MUX

2:1 MUX

4:1 MUX

Feedback

0
0
0
0
1
1
0
0

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