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EE-2171 Digital Logic: Course Specification

This document provides information about the EE-2171 Digital Logic course at Michigan Technological University. The 3-sentence summary is: EE-2171 Digital Logic is a required course for electrical and computer engineering students that introduces analysis, design, and application of digital logic including Boolean algebra, number representation, logic gates, combinational and sequential logic. The course objectives are to teach students combinational logic design, number representation and calculations, sequential logic, and logic design using Verilog. Topics covered include Boolean algebra, multiplexers, flip flops, synchronous and asynchronous logic design, and Verilog.

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Harold Wilson
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50 views2 pages

EE-2171 Digital Logic: Course Specification

This document provides information about the EE-2171 Digital Logic course at Michigan Technological University. The 3-sentence summary is: EE-2171 Digital Logic is a required course for electrical and computer engineering students that introduces analysis, design, and application of digital logic including Boolean algebra, number representation, logic gates, combinational and sequential logic. The course objectives are to teach students combinational logic design, number representation and calculations, sequential logic, and logic design using Verilog. Topics covered include Boolean algebra, multiplexers, flip flops, synchronous and asynchronous logic design, and Verilog.

Uploaded by

Harold Wilson
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Michigan Technological University

Electrical and Computer Engineering

Course Specification
EE-2171
Digital Logic

Curricular Designation:

CpE: required EE: required

Catalog Description:
Introduces analysis, design, and application of digital logic. Includes Boolean algebra, binary numbers,
logic gates, combinational and sequential logic, storage elements, schematic and hardware-descriptionlanguage based synthesis. Credits: 2.0 Lec-Rec-Lab: (2-0-0) Semesters Offered: Fall Spring Prerequisites: CS 1121 or CS 1131
Textbooks(s) and/or Other Required Materials:
1. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design,
McGraw-Hill Higher Education, 2003, ISBN 0-07-283878-7.
2. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, 2003, ISBN 0-13089161-4 (Reference text).
Prerequisites by Topic:
1. Familiarity with computer programming.
Course Objectives:
1. Combinational logic design including familiarity with Boolean algebraic equations and mastery of
Karnaugh maps.
2. Mastery of number representation in binary, octal and hexadecimal, twos complement addition,
binary multiplication, and BCD addition.
3. Introduction to multiplexers, decoders, encoders and code converters.
4. Introduction to SR, JK, & T flip flops, familiarity with D flip flops
5. Familiarity with synchronous sequential logic design using D flip flops, including finite state
machines.
6. Introduction to asynchronous sequential logic design, including races and hazards.
7. Familiarity with Verilog logic design.

.DOC

10/29/04

Topics Covered:
1. Combinational logic design
a. Boolean algebra, algebraic manipulation of Boolean equations with 2-3 variables, &
Karnaugh maps with 4-5 variables
b. Multiplexers, decoders, encoders and code converters
c. programmable logic devices, practical aspects
2. Number representation and calculations
a. Binary, octal, hexadecimal and twos complement
b. Binary addition and multiplication, twos complement and BCD addition
3. Sequential logic
a. Latches, master-slave and edge-triggered flip flops
b. Introduction to RS, T and JK flip flops
c. Synchronous logic analysis and design with D flip flops
d. Asynchronous design with simplified assignments, hazards and races
4. Logic design with Verilog
Relationship of Course to Program Outcomes (See UPAC SOP, Tables 1 and 2):

EE:

Outcome: a
Outcome: c
Outcome: k

via topic(s): 1a, 2a, 2b, 3


via topic(s): 1a, 3b, 3c, 4
via topic(s): 4

CpE:

Outcome: a
Outcome: k
Outcome: n
Outcome: p
Outcome: s

via topic(s): 1a, 2a, 2b, 3


via topic(s): 4
via topic(s): all
via topic(s): all
via topic(s): all

Contribution of Course to Meeting the Professional Component:


EE:
Engineering Topics

CpE:

Engineering Topics

Class/Laboratory Schedule (note: 1 hour = 50 minutes):


Lecture: 30 hours = 2 hours/week for 15 weeks
Prepared by:
Jindong Tan, Assistant Professor, June 1, 2004
.DOC

10/29/04

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