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Test Bench For Exponential Function

this document talk about how to write a HDL testbench for a verilog code.various data generation for input have presented

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184 views4 pages

Test Bench For Exponential Function

this document talk about how to write a HDL testbench for a verilog code.various data generation for input have presented

Uploaded by

farzian1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Assignment 1 Design and writing a Testbench for

an Exponentiation Module
Mohammad Ebrahimi
810192234

Electrical and Computer Engineering


School of Engineering Colleges, Campus 2
University of Tehran, 1450 North Amirabad, 14395-515 Tehran, Iran
[email protected]

Abstract In this homework we are to design and implement a


module named Exp that calculates ex using Tailor series. This
module accepts a n bit input x in fixed point representation
system. x is assumed to be in range 0
. When the
module detects a positive pulse on start signal, computation is
started and output busy signal issues to be 1 meanwhile
computation. At the end of computation busy signal becomes low
indicating that outputs are valid. Two outputs are considered to
showing the result. Two bit resultIntegralpart to represent
integral part of the result and 16 bit resultFractionalpart to
represent fractional part of the result. Array multiplier is the
main portion of Exp in which multiplication is done. The
design is flexible and user could determine bit width of x.

Keywords Fixed point representation, Array multiplier.


I.INTRODUCTION
Tailor series is one of well-known methods to compute
mathematical functions such as sin(x), cos(x), ex, and etc.
The following algorithm can be used to approximate ex:

As can be seen multiplication is the main function to calculate


ex. from the algorithm we can conclude that two multiplication
and one adding are needed in each iteration. Moreover , values
of term (1/i) for 1
have been computed before and
stored in a table. All components will discussed in details in
next sections. Sec. II introduces the the data path. Sec. III
presents the controller of the Exp module. Testbench and
data provision methods to apply inputs will describe in sec.
IV. results will be shown in sec. V and finally sec. VI
concludes the report.

II.DATA PATH
Figure 1 shows the circuit of data path. Data path component
consist of several components including Multiplier that
gives 3 n-bit inputs and an n-bit output. Multiplier itself
consists of two cascaded array multiplier. Array multiplier
accepts two n-bit inputs and result is available on n-bit output.
Note that the array multiplier ignores n-bit least significant
bits. Multiplier has three inputs. One of inputs comes from x
input, another multiplier input(1/i) comes from look-up-table,
and the other one is the previous output that comes from
rega output. An up-counting counter has been considered
two address look-up-table entries sequentially. Up-counter
counts while its start signal is high. Start signal come from
controller and connected to controller busy output. after
each multiplication the intermediate results are accumulate
using n+2 bit adder, n bit for fractional part and 2 bit for
integral part of the result. Counter and registers are common
and clear so we describe array multiplier and look up table
details in the rest of this section:
Array multiplier: multiplication of binary operands in a
digital system can be performed in a variety of ways that are
different in speed and gate count. A combinational n*n
multiplier requires an array on n*n multiplier cells each of
which is responsible for multiplying a bit of multiplier with a
bit of multiplicand and adding the result with the product bit
coming from a previous multiplication stage.
Therefore an AND gate for 1*1 multiplication and a full-adder
for the add operation constitute the required multiplier cell
hardware, as shown in Figure 2.
The cell shown in Figure 2 multiplies its xi and yi inputs using
the AND gate and adds this result with its input partial
product p0, a carry output c0, and passes xi and yi inputs on to
its outputs(xo and yo).

of a bit-multiplier at location i, j to xi of the bit-multiplier to


its left.
Look up table: look up table is a table in which (1/i) terms
have been saved in fixed point representation system. We
assume
1
. So the table has 16 16-bit entries.
table.v includes High level description Verilog code for
generating table.
Figure 2: Multiplier Cell

Figure 3 shows a 4 * 4 array multiplier that uses 16 of the


multiplier cells of Figure 2. A 32 bit multiplier requires 1024
such cells. Figure 4 shows the Verilog code of a multiplier cell
bit_multiplier corresponding to the diagram of Figure 2.

III.CONTROLLER
Controller receives 3 signals as input CLK, start, and
finish. First, controller is in Waiting state and wait for
positive pulse on start. After detecting positive pulse on
start, controller changes its state to Busy. The controller has
been written according to Huffman coding style so that
sequential and combinational parts of controller is separated.
Controller has 3 outputs including busy, waiting and
done. Figure 7 shows the state machine of the controller.
(start,finish)
(0X)

Waiting

(10)

Busy

(x0)

(X1)

Figure 3: 4*4 Multiplier

The logical architecture of bit_multilier has a full adder, an


AND gate and pass-through wires connecting inputd xi and yi
to their corresponding outputs, xo and yo.
module bit_mutiplier(
xi,yi,pi,ci,
xo,yo,po,co
);
input xi,yi,pi,ci;
output xo,yo,po,co;
reg xy;
always @(xi,yi)
begin
xy <= xi & yi;
end
assign co = (pi & xy) | (pi & ci) | (xy & ci);
assign po = pi ^ xy ^ ci;
assign xo = xi;
assign yo = yi;
endmodule
Figure 4: One-bit Multiplier

array_mutiplier.v includes the Verilog code of an n*n


unconstrained array multiplier. In the declarative part of this
architecture xv,yv,cv, and pv n*n array are declared. These
signals are used for connecting signals of the bit-multipliers of
the array multiplier to their adjacent bit-multiplier. These
arrays are for connecting intermediate x inputs, y inputs,
carry, and partial products. For example xv(i,j) connects the x0

Done

Figure 7: State diagram of the controller

IV.TestBench
tester.v includes testbench for module Exp. Data
provision methods including deterministic, arithmetic,
periodic, random and Text IO have been used to apply data to
Exp. Data has been applied in random and equal time slots
and results collected after falling edge of busy signal.
V.Simulation Results
Figure 8-a and 8-b show the result waveforms after running
testbench. In addition to waveform, results have been
displayed on screen using $diplay command in figure 9.
VI.CONCLUSION
In this homework we designed and implemented a module
that calculates ex using tailor series. In order to do
multiplication we design a generic array multiplier. The Exp
module start calculating after active pulse detection on start
signal on the rise edge of clk signal and issues busy signal to
high simultaneously . After completion of calculation busy
signal is deactivated and the module is ready to accept another
input on x vector.

Data path
Multiplier
Rega(16 bit)

Array
Multiplier

Array
Multiplier

Set

CLK

Set

Regb_out[17:16]

Start
Counter(4 bit)

Look
up
table

Set

Adder

CLK

CLK

Finish

Regb_out[15:0]

Regb(18 bit)
Regb_out

done
Controller

Start

busy

CLK

Figure 1:Data path and Controller

Figure 8-a: result waveforms(x= 1001100110001101, result = 01.1101001001011001)

ResultIntegralpart
ResultFractionalpart

Figure 8-b: result waveforms(x= 0101001000010010, result = 01.0110000010111010)

Figure 9: result using $display command

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