Expt. No.

Date

: 01
:

LOGIC GATES

AIM
To verify the functionalities of XOR & AND logic gates using ModelSim software.
CODE
xor2.vhdl
library ieee;
use ieee.std_logic_1164.all;
--entity declaration
entity xor2 is
port(a,b : in BIT; y : out BIT);
end xor2;
--architecture declaration
architecture dataflow of xor2 is
begin
y <= a xor b;
end dataflow;
and2.vhdl
library ieee;
use ieee.std_logic_1164.all;
--entity declaration
entity and2 is
port(a,b : in BIT; y : out BIT);
end and2;
--architecture declaration
architecture dataflow of and2 is
begin
y <= a and b;
end dataflow;

SAMPLE OUTPUT
xor2.vhdl

and2.vhdl

RESULT
The functionalities of logic gates using their truth tables had been verified successfully using VHDL
programming.

Expt. No.
Date

: 02
:

HALF ADDER

AIM
To verify the functionality of half adder in structural and dataflow architectures using
ModelSim software.
CODE
half_adder.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port(a,b : in BIT; sum,carry : out BIT);
end half_adder;
--architecture declaration dataflow
architecture dataflow of half_adder is
begin
sum <= a xor b;
carry <= a and b;
end dataflow;
--architecture declaration structural
architecture structural of half_adder is
component xor2
port(a,b: in BIT; y: out BIT);
end component;
component and2
port(a,b: in BIT; y: out BIT);
end component;
begin
x1: xor2 port map(a,b,sum);
x2: and2 port map(a,b,carry);
end structural;

SAMPLE OUTPUT

RESULT
The functionality of half adder using dataflow and structural architectures is verified successfully
using VHDL programming.

Expt. No.
Date

: 03
:

2 : 4 DECODER

AIM
To verify the functionality of 2 : 4 decoder using ModelSim software.
CODE
inv1.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity inv1 is
port(a : in BIT; y : out BIT);
end inv1;
architecture dataflow of inv1 is
begin
y <= not (a);
end dataflow;
nand3.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity nand3 is
port(a,b,c : in BIT; y : out BIT);
end nand3;
architecture dataflow of nand3 is
begin
y <= not (a and b and c);
end dataflow;
decoder2x4.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity decoder2x4 is
port(a,b,en : in BIT; z : out BIT_Vector(0 to 3));
end decoder2x4;

architecture structural of decoder2x4 is

component inv1
port(a : in BIT; y : out BIT);
end component;
component nand3
port(a,b,en : in BIT; y : out BIT);
end component;
signal abar,bbar : BIT;
begin
I0 : inv1 port map(a,abar);
I1 : inv1 port map(b,bbar) ;
N0 : nand3 port map(abar,bbar,en,z(0));
N1 : nand3 port map(abar,b,en,z(1));
N2 : nand3 port map(a,bbar,en,z(2));
N3: nand3 port map(a,b,en,z(3));
end structural;

SAMPLE OUTPUT

RESULT
The functionality of 2x4 Decoder is successfully verified using VHDL programming.

Expt. No.
Date

: 04
:

FULL ADDER

AIM
To verify the functionality of Full Adder in ModelSim software using
1. Dataflow architecture programming
2. Two half adders as a combination to form a full adder.
CODE
or2.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity or2 is
port(a,b : in BIT; y : out BIT);
end or2;
architecture dataflow of or2 is
begin
y <= a or b;
end dataflow;
full_adder.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity full_adder is
port(a,b,cin : in BIT; sum,carry : out BIT);
end full_adder;
--architecture declaration - dataflow
architecture dataflow of full_adder is
begin
sum <= (a xor b) xor cin;
carry <= ((a xor b) and cin) or (a and b);
end dataflow;
--architecture declaration structural with two half adders
architecture structural of full_adder is
component half_adder
port(a,b : in BIT; sum,carry : out BIT);
end component;
component or2
port(a,b : in BIT; y : out BIT);
end component;
signal I0, I1, I2 : BIT;

begin
HA0 : half_adder port map(a,b,I0,I1);
HA1: half_adder port map(I0,cin, sum,I2);
OR0: or2 port map(I2,I1,carry);
end structural;

SAMPLE OUTPUT

RESULT
The functionality of full adder using various architectures is verified successfully using VHDL
programming.

Expt. No.
Date

: 05
:

SUBTRACTORS

AIM
To verify the working functionalities of the following using structural architecture of VHDL
programming in ModelSim software.
1. Half subtractor
2. Full subtractor
CODE
half_subtractor.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity half_subtractor is
port(a,b : in BIT; d,borrow : out BIT);
end half_subtractor;
architecture structural of half_subtractor is
component xor2
port(a,b : in BIT; y : out BIT);
end component;
component and2
port(a,b : in BIT; y : out BIT);
end component;
signal abar : BIT;
begin
abar <= not(a);
DIFF: xor2 port map(a,b,d);
BORR: and2 port map(abar,b,borrow);
end structural;

full_subtractor.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity full_subtractor is
port(a,b,cin : in BIT; d,borrow : out BIT);
end full_subtractor;

architecture structural of full_subtractor is

component half_subtractor
port(a,b : in BIT; d,borrow : out BIT);
end component;
component or2
port(a,b : in BIT; y : out BIT);
end component;
signal I0,I1,I2 : BIT;
begin
HS0 : half_subtractor port map(a,b,I0,I1);
HS1 : half_subtractor port map(I0,cin,d,I2);
ORC: or2 port map(I2,I1,borrow);
end structural;

SAMPLE OUTPUT

RESULT
The functionalities of half subtractor and full subtractor are verified successfully using VHDL
programming.

Expt. No.
Date

: 06
:

4 BIT ADDER

AIM
To verify the functionalities of 4 bit adder in structural style of programming using
ModelSim software.
CODE
add4.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity add4 is
port(a0,a1,a2,a3,b0,b1,b2,b3,cin : in BIT; s0,s1,s2,s3,cout : out BIT);
end add4;
architecture structural of add4 is
component full_adder
port(a,b,c : in BIT; sum,cout : out BIT);
end component;
signal c1,c2,c3 : BIT;
begin
K0 : full_adder port map(a0,b0,cin,c1,s0);
K1 : full_adder port map(a1,b1,c1,s1,c2);
K2 : full_adder port map(a2,b2,c2,s2,c3);
K3 : full_adder port map(a3,b3,c3,cout,s3);
end structural;
SAMPLE OUTPUT

RESULT
The functionality of 4 bit adder has been verified successfully using VHDL programming.

Expt. No.
Date

: 07
:

4 BIT ADDER USING PACKAGE

AIM
To verify the functionality of 4 bit adder using package using ModelSim Software.
CODE
packadd.vhdl
library ieee;
use ieee.std_logic_1164.all;

package packadd is
component full_adder
port(a,b,cin : in BIT; sum,carry : out BIT);
end component;
end packadd;
add4bit.vhdl
library ieee;
use ieee.std_logic_1164.all;
use work.packadd.all;
entity add4bit is
port(z0,z1,z2,z3,n0,n1,n2,n3,m:in BIT;
s0,s1,s2,s3,cout:out BIT);
end add4bit;
architecture structural of add4bit is
signal f1,f2,f3:BIT;
begin
A1:full_adder port map(z0,n0,m,s0,f1);
A2:full_adder port map(z1,n1,f1,s1,f2);
A3:full_adder port map(z2,n2,f2,s2,f3);
A4:full_adder port map(z3,n3,f3,s3,cout);
end structural;

SAMPLE OUTPUT

RESULT
The functionality of half adder using dataflow and structural architectures is verified successfully
using VHDL programming.

Expt. No.
Date

: 08
:

MULTIPLEXERS

AIM
To verify the functionality of 2 : 1 MUX and 4 : 1 MUX using behavioural style of programming in
ModelSim Software.
CODE
mux_2to1.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity mux_2to1 is
port(w0, w1 : in std_logic; s : in std_logic; f : out std_logic);
end mux_2to1;
architecture behaviour of mux_2to1 is
begin
with s select
f <= w0 when 0,
w1 when others;
end behaviour;
mux_4to1.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;
entity mux_4to1 is
port(w0, w1,w2,w3 : in std_logic;
s : in std_logic_vector(1 downto 0);
f : out std_logic);
end mux_4to1;
architecture behaviour of mux_4to1 is
begin
with s select
f <= w0 when 00,
w1 when 01,
w2 when 10,
w3 when others;
end behaviour;

SAMPLE OUTPUT

RESULT
The functionalities of Multiplexers are successfully verified using VHDL programming.

Expt. No.
Date

: 09
:

16 : 1 MUX USING 4 : 1 MUX

AIM
To verify the functionality of 16 : 1 MUX using 4 : 1 MUX using ModelSim software.
CODE
mux_16to1.vhdl
library ieee;
use ieee.std_logic_1164.vhdl;

entity mux_16to1 is
port(w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15 : in std_logic;
s : std_logic_vector(3 downto 0); f : out std_logic);
end mux_16to1;
architecture structural of mux_16to1 is
component mux_4to1
port(w0, w1,w2,w3 : in std_logic;
s : in std_logic_vector(1 downto 0);
f : out std_logic);
end component;
signal I0, I1, I2,I3 : std_logic;

begin
M1: mux_4to1 port map(w0,w1,w2,w3,s(1 downto 0),I0);
M2: mux_4to1 port map(w4,w5,w6,w7,s(1 downto 0),I1);
M3: mux_4to1 port map(w8,w9,w10,w11,s(1 downto 0),I2);
M4: mux_4to1 port map(w12,w13,w14,w15,s(1 downto 0),I3);
M5: mux_4to1 port map(I0,I1,I2,I3,s(3 downto 2),f);
end structural;

SAMPLE OUTPUT

RESULT
The functionality of full adder using various architectures is verified successfully using VHDL
programming.

Expt. No.
Date

: 10
:

3 : 8 DECODER USING 2 : 4 DECODER

AIM
To verify the working functionality of 3:8 Decoder with 2:4 Decoder (Active Low)
using ModelSim Software.
CODE
decoder2x4.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity decoder2x4 is
port (a,b,en : in BIT; z : out BIT_vector(0 to 3));
end decoder2x4;
architecture dataflow of decoder2x4 is
signal abar,bbar : BIT;
begin
abar <= not(a);
bbar <= not(b);
z(0) <= (abar and bbar and en);
z(1) <= (abar and b and en);
z(2) <= (a and bbar and en);
z(3) <= (a and b and en);
end dataflow;

decoder3x8.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity decoder3x8 is
port(w0,w1,w2,en : in BIT; y : out BIT_VECTOR(0 to 7));
end decoder3x8;

architecture structural of decoder3x8 is

component decoder2x4
port (a,b,en : in BIT; z : out BIT_vector(0 to 3));
end component;
component and2
port(a,b : in BIT; y : out BIT);
end component;
component inv
port(a : in BIT; y : out BIT);
end component;
signal m0,m1,m2 : BIT;
begin
I0 : inv port map(w2,m0);
A0 : and2 port map(m0,en,m1);
A1 : and2 port map(en,w2,m2);
S0 : decoder2x4 port map(w0,w1,m1,y(0 to 3));
S1 : decoder2x4 port map(w0,w1,m2,y(4 to 7));
end structural;

SAMPLE OUTPUT
decoder2x4.vhdl

decoder3x8.vhdl

RESULT
The functionality of 3x8 Decoder constructed with 2x4 Decoder is executed and verified successfully
using ModelSim Software.

Expt. No.
Date

: 11
:

D FLIP FLOP

AIM
To verify the working functionality of D LATCH and D Flip Flop using ModelSim Software.
CODE
dlatch.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity dlatch is
port(d,clk : in std_logic; Q : out std_logic);
end dlatch;
architecture behaviour of dlatch is
begin
process(d,clk)
begin
if clk=1 then
Q <= d;
endif;
end process;
end behaviour;
dff.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity dff is
port(D,clk,reset : in std_logic; Q : out std_logic);
end dff;
architecture behaviour of dff is
signal d_out : std_logic;
begin
process(clk)
begin
if(clkevent and clk=1) then
if(reset=0) then
d_out <= D;
elseif(D=0) then
d_out <= D;
end if;
end if;
end process;
q <= d_out;
end behaviour;
RESULT
The working functionalities of D LATCH and D FLIP FLOP has been verified successfully.

Expt. No.
Date

: 12
:

POSITIVE AND NEGATIVE TRIGGERED

D LATCH & FLIP FLOP

AIM
To verify the working functionality of positive and negative edge trigged D Latch
and D Flip Flop using ModelSim Software.
CODE
d_latch.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity d_latch is
port(d,clk : in std_logic; Q : out std_logic);
end d_latch;
architecture behavioural of d_latch is
begin
process(d,clk)
begin
if clk=1 then
Q <= d;
end if;
end process;
end behavioural;
d_ff.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity d_ff is
port(D,Clk : in std_logic; q : out std_logic);
end d_ff;
architecture structural of d_ff is
component d_latch
port(d,clk : in std_logic; Q : out std_logic);
end component;

signal Qm,Qs,nclk : std_logic;

begin
nclk <= not(Clk);
d1 : d_latch port map(D,nclk,Qm);
d2 : d_latch port map(Qm,Clk,Qs);
q <= Qs;
end structural;
d_tpn.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity d_tpn is
port(D,Clk : in std_logic; Qa,Qb,Qc : out std_logic);
end d_tpn;
architecture structural of d_tpn is
component dlatch
port(d,clk : in std_logic; q : out std_logic);
end component;
signal nclk : std_logic;
begin
nclk <= not(Clk);
d1 : d_latch port map(D,Clk,Qa);
d2 : d_ff port map(D,Clk,Qb);
d3 : d_ff port map(D,nclk,Qc);
end structural;

RESULT
The positive and negative triggering of D latch and D Flip Flop is executed and verified successfully.

Expt. No.
Date

: 13
:

T FLIP FLOP

AIM
To verify the working functionality of T Flip Flop using ModelSim Software.
CODE
tff.vhdl
library ieee;
use ieee.std_logic_1164.all;

entity tff is
port(t,clk,rst : in std_logic; q,qb : out std_logic);
end tff;

architecture behaviour of tff is

begin
process(clk,rst)
begin
if rst=1 then
q <= 0;
qb <= 1;
elseif
clkevent and clk=1 then
q<=not t;
qb <= t;
end if;
end process;
end behaviour;

RESULT
The working functionality of T Flip Flop has been verified successfully.

Expt. No.
Date

: 14
:

BCD TO SEVEN SEGMENT DECODER

AIM
To display the binary equivalent numbers in 7 segment display using ModelSim Software.
CODE
bcd7seg.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity bcd7seg is
port(bcd : in std_logic_vector(3 downto 0); display : out std_logic_vector(0 to 6));
end bcd7seg;
architecture behaviour of bcd7seg is
begin
process(bcd)
begin
case bcd is when 0000 => display <= 0000001;
when 0001 => display <= 1001111;
when 0010 => display <= 0010010;
when 0011 => display <= 0000110;
when 0100 => display <= 1001100;
when 0101 => display <= 0100100;
when 0110 => display <= 0100000;
when 0111 => display <= 0001111;
when 1000 => display <= 0000000;
when 1001 => display <= 0001100;
when others => display <= 1111111;
end case;
end process;
end behaviour;

RESULT
The BCD to 7 segment display code has been successfully executed, displayed and verified.

Expt. No.
Date

: 15
:

RS LATCH

AIM
To verify the working functionality of RS Latch using ModelSim Software.
CODE
rslatch.vhdl
library ieee;
use ieee.std_logic_1154.all;

entity rslatch is
port(r,clk,s : in std_logic; Q : out std_logic);
end rslatch;

architecture dataflow of rslatch is

signal r_g,s_g,Qa,Qb:std_logic;
begin
r_g <= r and clk;
s_g <= clk and s;
Qa <= not(r_g or s_g);
Qb <= not(Qa or s_g);
Q <= Qa;
end dataflow;

RESULT
The RS Latch working functionality has been successfully executed and verified.

Expt. No.
Date

: 16
:

BCD COUNTER

AIM
To verify the working functionality of BCD Counter with two 7 segment displays using
ModelSim Software.
CODE
bcdcounter.vhdl
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bcdcounter is
port (clock_50 : in std_logic; hex0 : out std_logic_vector(0 to 6));
hex1 : out std_logic_vector(0 to 6));
end bcdcounter;
architecture behavior of bcdcounter is
component bcd7seg
port (bcd : in std_logic_vector(3 downto 0);
display : out std_logic_vector(0 to 6));
end component;
signal bcd_a : std_logic_vector(3 downto 0);
signal bcd_b : std_logic_vector(3 downto 0);
signal slow_count : std_logic_vector(24 downto 0);
signal digit_flipper_a : std_logic_vector(3 downto 0);
signal digit_flipper_b : std_logic_vector(3 downto 0);
begin
process (clock_50)
begin
if (clock_50'event and clock_50 = '1') then
slow_count <= slow_count + 1;
end if;
end process;

process (clock_50)
begin
if (clock_50'event and clock_50 = '1') then
if (slow_count = 0) then
if (digit_flipper = "1001") then
digit_flipper_a <= "0000";
digit_flipper_b <= digit_flipper_b + 1;
else
digit_flipper_a <= digit_flipper_a + 1;
end if;
end if;
end if;
end process;
bcd_a <= digit_flipper_a;
bcd_b <= digit_flipper_b;
digit_0: bcd7seg port map(bcd_a, HEX0);
digit_1: bcd7seg port map (bcd_b, HEX0);
end behavior;

RESULT
The working functionality of BCD Counter is executed and verified successfully.

Expt. No.
Date

: 17
:

ASYNCHRONOUS AND SYNCHRONOUS

UP COUNTER

AIM
To verify the working functionality asynchronous and synchronous up counter using
ModelSim Software.
CODE
aup.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity aup is
port(clk,rest : in std_logic; Q0,Q1,Q2 : inout std_logic);
end aup;
architecture structural of aup is
component tff
port(T,Clock,rest : in std_logic; Q : out std_logic);
end component;
signal I0,I1 : std_logic;
begin
I0 <= not(Q0);
I1 <= not(Q1);
t1 : tff_ff port map(1,clk,rest,Q0);
t2 : tff_ff port map(1,I0,rest,Q1);
t3 : tff_ff port map(1,I1,rest,Q2);
end structural;
sup.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity sup is
port(clk,rest : in std_logic; Q0,Q1,Q2 : inout std_logic);
end sup;

architecture structural of sup is

component tff
port(T,Clock,rest : in std_logic; Q : out std_logic);
end component;
signal I0,I1:std_logic;
begin
I0 <= Q0;
I1 <= Q1;
t1 : tff_ff port map(1,clk,rest,Q0);
t2 : tff_ff port map(I0,clk,rest,Q1);
t3 : tff_ff port map(I1,clk,rest,Q2);
end structural;

RESULT
The working functionalities of asynchronous and synchronous up counter has been
verified successfully.

Expt. No.
Date

: 18
:

TWO BIT COMPARATOR

AIM
To verify the working functionality 2 bit comparator using ModelSim Software.
CODE
comp.vhdl
library ieee;
use ieee.std_logic_1164.all;
entity comp is
port(A : in std_logic_vector(1 downto 0); B : out std_logic_vector(1 downto 0);
less : out std_logic; equal : out std_logic; greater : out std_logic);
end comp;
architecture behaviour of comp is
begin
process(A,B)
begin
if(A<B) then
less <= 1;
equal <= 0;
greater<=0;
elseif(A=B) then
less <= 0;
equal <= 1;
greater <= 0;
else
less <= 0;
equal <= 0;
greater <= 1;
end if;
end process;
end behaviour;

RESULT
The working functionality of 2 bit comparator has been executed and verified successfully.

Expt. No.
Date

: 19
:

PRIORITY ENCODER

AIM
To verify the working functionality 2 bit comparator using ModelSim Software.
CODE
priorityencoder.vhdl
library ieee;
use ieee.std_logic_1164.all;

entity priorityencoder is
port(w : in std_logic_vector(7 downto 0);
y : out std_logic_vector(2 downto 0));
end priorityencoder;

architecture behaviour of priorityencoder is

begin
y <= 111 when w(7)=1 else
110 when w(6)=1 else
101 when w(5)=1 else
100 when w(4)=1 else
011 when w(3)=1 else
010 when w(2)=1 else
001 when w(1)=1 else
000 when others;
end behaviour;

RESULT
The working functionality of Priority Encoder has been executed and verified successfully.

Expt. No.
Date

: 20
:

SEQUENCE DETECTOR FSM

AIM
To write a VHDL program to implement a Mealy state machine with behavioral model to
detect a given sequence 1110
CODE
fsm.vhdl
library ieee;
use ieee.std_logic_1164.all;

entity fsm is
port(ip,clock : in bit; op : out bit);
end fsm;

architecture seq_det of fsm is

type state is (s0,s1,s2,s3);
signal present_state:state;
begin
process(clock,present_state,ip)
begin
if clock 'event and clock='1' then
case present_state is
when s0 =>
if ip = '0' then present_state <= s0; op <='0';
elsif ip='1' then present_state<=s1; op<='0';
end if;
when s1 =>
if ip = '0' then present_state <= s0; op <='0';
elsif ip='1' then present_state<=s2; op<='0';
end if;

when s2=>
if ip = '0' then present_state <= s0; op <='0';
elsif ip='1' then present_state<=s3; op<='0';
end if;

when s3 =>
if ip = '0' then present_state <= s0; op <='1';
elsif ip='1' then present_state<=s3; op<='0';
end if;
end case;
end if;
end process;
end seq_det;

RESULT
The sequence detector FSM has been implemented in VHDL programming successfully.

Expt. No.
Date

: 01
:

HALF ADDER

AIM
To verify the working functionality Half Adder in Verilog coding using ModelSim Software.
CODE
module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
and(carry,a,b);
xor(sum,a,b);
endmodule
module halfadder(a,b,sum,carry);
input a,b;
output sum,carry;
assign sum=a^b;
assign carry=a&b;
endmodule

SAMPLE OUTPUT

RESULT
The coding for Half Adder in Verilog has been executed and verified successfully.

Expt. No.
Date

: 02
:

FULL ADDER

AIM
To verify the working functionality Full Adder in Verilog coding using ModelSim Software.
CODE
module fulladder(a,b,cin,sum,cout);
input a,b,cin;
wire i0,i1,i2;
output sum,cout;
xor(i0,a,b);
and(i1,a,b);
and(i2,10,cin);
xor(sum,i0,cin);
or(cout,i1,i2);
endmodule;
SAMPLE OUTPUT

RESULT
The working functionality of Full Adder in Verilog coding has been verified successfully.

Expt. No.
Date

: 03
:

INVERTER

AIM
To verify the working functionality Inverter in Verilog coding using ModelSim Software.
CODE
module inverter(x,y);
input x;
output y;
supply1 vdd;
supply0 gnd;
pmos p1(vdd,y,x);
nmos n1(y,gnd,x);
endmodule;
SAMPLE OUTPUT

RESULT
The working functionality of Inverter in Verilog coding has been verified successfully.

Expt. No.
Date

: 01
:

DISPLAYING HELLO WORLD!

AIM
To use Bluespec SystemVerilog workstation to display the message Hello World! on the screen.
CODE
package Tb;
(* synthesize *)
module mkTb (Empty);
rule greet;
$display ("Hello World!\n");
$finish (0);
endrule
endmodule: mkTb
endpackage: Tb
SAMPLE OUTPUT

RESULT
The message Hello World! has been displayed using Bluespec SystemVerilog successfully.

Expt. No.
Date

: 02
:

SUM OF N NUMBERS

AIM
To use Bluespec SystemVerilog workstation to find the sum of first N numbers.
CODE
package Tb;
(* synthesize *)

module mkTb();
Ifc_type m1 <- mkLoop;
rule ansdisplay;
$display("The answer is %d\n", m1.the_iteration(10));
$finish(0);
endrule
endmodule:mkTb

interface Ifc_type;
method int the_iteration(int x);
endinterface: Ifc_type

(* synthesize *)
module mkLoop(Ifc_type);
method int the_iteration(int x);
for (int i = 0; i < 10; i = i+1)
x = x + i;
return x;
endmethod
endmodule:mkLoop

endpackage:Tb

SAMPLE OUTPUT

RESULT
The sum of N numbers using Bluespec SystemsVerilog has been executed and
verified successfully.